DE102006060429B4 - Electrical component with leadframe structures - Google Patents

Abstract

Electrical component
With first leadframe structures 91, which are provided as electrical connections of the component,
With at least one second leadframe structure (92, 93) on which at least two chips (21, 22) are fastened next to one another via their rear sides,
- wherein the at least two chips (21, 22) each have on their upper side connecting surfaces (81) which are connected to the first leadframe structure (91) by means of first bonding wires (97),
Wherein semiconductor elements of the circuit realized in the component are arranged in the first chip (22),
- Wherein in the second chip (21) in passive circuit blocks of the circuit, a function selected from a transmission filter, a reception filter, a crossover and a balun is realized, and the second chip is free of semiconductor elements.

Description

From the pamphlets EP 00455245 A2 and US 2005/0206010 A1 are electrical components with a chip known, which is connected to leadframe terminals.

From the publication US 2005/0040512 A1 are electrical components with two semiconductor chips and interconnections via bonding wires known.

From the publication US 2005/0006730 A1 are known electrical components with two stacked chips. A semiconductor chip is arranged vertically between a chip with passive circuit elements and a leadframe structure.

From the publication US 2004/0238934 A1 For example, RF semiconductor modules having a semiconductor chip and a chip with passive circuit elements are known.

An object to be solved is to provide an electrical component that allows a high degree of integration in a compact design.

An electrical component with first leadframe structures, which are provided as electrical connections of the component, and at least one second leadframe structure, on which at least two chips are mounted, are specified.

The advantage of the specified component is to separate the mechanical carrier function for the at least two chips and the electrical connections of the component from each other and to use a separate leadframe structure for both functions. As a result, compared with a highly integrated module having a multi-layer substrate and chips mounted thereon, the overall height can be reduced. It is possible to realize functional blocks of a circuit in the chips and to arrange these chips next to one another on a leadframe structure.

In the device, an electrical circuit is realized, the circuit blocks, d. H. electrical circuits with a specific function, having. As a circuit block can z. For example, a switch, an amplifier, a filter, a balun, a crossover, a directional coupler, a detector, etc. may be referred to. The respective filter may include a bandpass, a lowpass, a highpass, a bandstop or their combination.

The circuit is divided into at least two functional blocks. Each functional block comprises at least one circuit block. At least one functional block is implemented in each chip. At least one further functional block can also be realized in at least one of the chips.

The advantage of the specified component is that the height can be reduced by the arrangement of functional blocks realized in the chips of a circuit side by side compared to a highly integrated module with a multi-layer substrate and chips mounted thereon.

Below, advantageous embodiments of the specified component will be explained.

A leadframe is understood to mean a leadframe which has structures provided as electrical connections and chip carriers, i. H. first and second leadframe structures. These structures are after the encapsulation of the device from the rest of the lead frame z. B. separated by sawing.

The at least one second leadframe structure consists in a variant of a single leadframe structure. In an advantageous variant, the at least one second leadframe structure comprises at least two second separate leadframe structures. Preferably, at least two second leadframe structures are provided which are not interconnected.

The at least one second leadframe structure has at least one conductive surface on which the chips are mounted. The conductive surface is provided as a support for the at least one chip.

The respective second leadframe structure can have a plurality of conductive surfaces, which are connected to one another, for example, by means of a conductive web. At least one chip is arranged on each conductive surface. On at least one of these conductive surfaces and at least two chips can be arranged.

The respective second leadframe structure preferably has at least one conductive web connected to the conductive surface, which extends up to the line which runs along an outwardly facing edge of at least one of the first leadframe structures. This line also corresponds to a sawing line when singulating the originally formed on the leadframe component.

The component is preferably formed as a chip component, the Surface mounting is suitable. The first leadframe structures represent SMD contacts of the device. SMD stands for Surface Mounted Design.

The underside of the component is divided into a central region and a peripheral edge region. At least one conductive surface of the at least one second leadframe structure is arranged in the middle region and the first leadframe structures provided as electrical connections of the component are arranged in the edge region.

The chips comprise in a variant a first chip and a second chip. The chips may also include additional chips. In an advantageous variant, at least two of the chips or all the chips of the component are arranged on a common conductive surface.

The conductive surface of the respective second leadframe structure has, in a variant, a first conductive surface and a second conductive surface, which are connected to one another by means of a conductive web. This applies to at least one of the second leadframe structures.

The first chip may be mounted on the first conductive surface and the second chip may be mounted on the second conductive surface. In one variant, the chips which form a first chip group are arranged on the first conductive surface and the chips which form a second chip group are arranged on the second conductive surface. The first chip group comprises a first chip or at least two first chips. The second chip group comprises a second chip or at least two second chips.

At least two of the second leadframe structures may not be electrically connected to each other. For each of the unconnected second leadframe structures, the following applies: the leadframe structure has at least one conductive web connected to the conductive surface, which extends to a line, which forms an outwardly facing edge of at least one of the first leadframe structures touched. By means of this web, a connection between each of the second leadframe structures and the entire original leadframe is ensured before the component is singulated, which is divided into first and second leadframe structures after the component has been singulated.

The chips are connected to the first leadframe structures by means of first bonding wires. The chips are connected to each other by means of second bonding wires. These chips may be arranged on a common conductive surface or on different conductive surfaces of the same leadframe structure. These chips can also be arranged on conductive surfaces of various second leadframe structures.

A direct Drahtbondverbindung between the chips has the advantage that can be dispensed with an elaborate wiring using the leadframe. The direct wiring via bonds can be dispensed with in particular a complex wiring and signal routing within a multi-layer substrate as a chip carrier. Instead, a leadframe is used as a carrier.

Particularly advantageous are flat bonding wires or wedge bonds at least on the side of the chip connections. In this case, the height of the component can be reduced. It can be wire bonded by means of ultrasound or thermocompression.

The leadframe structures preferably provide sheet metal structures, i. H. made of sheet metal conductive surfaces, dar. The leadframe may contain a metal or a metal alloy. The leadframe may in particular contain Fe, Ni and / or Co.

For the leadframe is z. B. a metal sheet suitable whose thickness is about 200 microns. The side of the metal sheet facing the bonding wires is preferably coated with a Ni layer and an Au layer. The outwardly facing surface of the first leadframe structures may have a solderable coating. The solderable coating preferably contains tin. It can contain lead or be lead-free.

The first leadframe structures may have additional conductive structures that have no electrical connection to the chips. Such structures may be provided, for example, in order to achieve the most symmetrical distribution of electrical connections of the component and thus to prevent mechanical stresses.

The arrangement of the chips, the first and second leadframe structures is preferably mechanically stabilized by a cured potting compound. As casting compound are plastics, in particular resins such. As epoxy resin or other potting materials suitable.

The second leadframe structures are preferably connected to the ground of the device. The respective second lead frame structure may, for. B. connected to the ground of the chip attached thereto. The connection to a ground terminal of the device then takes place by means of a bonding wire. The ground connection of the component is then formed by at least one of the first leadframe structures. The at least one conductive surface may in principle be at least one be connected to the first leadframe structures by means of a conductive web.

In an advantageous embodiment, at least one function is implemented in the first chip, selected from a power amplifier, a low-noise amplifier, a switch, a detector and a directional coupler. In the second chip, preferably at least one function is realized, selected from a transmission filter, a reception filter, a crossover and a balun. A balun is understood to mean a transformer with a ground-symmetrical and a ground-symmetrical electric gate.

In the first and second chip, for example, a multiband multimode WLAN front-end module can be realized. The front-end module can, for. B. be designed for two frequency bands that differ by at least one octave. For example, a first frequency band at about 2.4 GHz and a second frequency band at about 4.9 GHz.

Per frequency band, a transmission path and a reception path is provided. Each transmission path has its own power amplifier, its own transmission filter and possibly its own balun. Each reception path has its own low-noise amplifier, its own receive filter and, if necessary, its own balun.

The switch is provided for switching between the transmission and reception paths of the respective frequency band. For each frequency band, a separate switch is provided in one variant.

The crossover is preferably a diplexer, with which it is possible to separate signals from two different frequency bands from each other. The diplexer is preferably arranged between an antenna and the switches.

The component preferably has an amplifier block in which the power amplifiers for all frequency bands are arranged next to one another. The component preferably has a second amplifier block, in which the low-noise amplifiers for all frequency bands are arranged side by side.

The electrical circuit, which is at least partially realized in the specified component, comprises in an advantageous variant of a transceiver circuit. The transceiver circuit includes u. a. at least one mixer, at least one oscillator, amplifier elements, logic modules and optionally further circuits which are suitable for processing high-frequency signals and / or demodulated signals.

The specified component is conductively connected in a variant with a transceiver circuit, which is realized as an integrated chip component. The transceiver circuit can also be realized in the first chip of the device.

The attachment of chips, the amplifier and switches or other semiconductor circuit elements such. B. comprise detectors, on one of the second leadframe structures is advantageous because a good thermal connection of these chips can be ensured to a connected to this second leadframe structure heat sink. Thus, in principle, the heat loss generated in active components of the device can be dissipated.

In the specified device, a high mechanical stability can be ensured by dividing a circuit to be realized in the component into relatively small spatially separated, interconnected by bonding wires and preferably encapsulated by means of a potting compound blocks.

The electrical circuit of the device has at least one signal path in which the circuit blocks are arranged. The circuit preferably has at least two signal paths, wherein in each signal path preferably at least two series-connected circuit blocks are arranged.

The respective circuit block may form a functional block with another circuit block. The circuit blocks can be arranged in a common signal path. But they can also be arranged in different signal paths of the electrical circuit. The signal paths can each be formed by a transmit-receive path, a transmit path or a receive path. A transmit-receive path has an antenna-side portion that is used for both transmission and reception, and that branches into a transmit path and a receive path. With multiple transmit-receive paths, each transmit-receive path is assigned to its own transmission system and frequency band.

For example, at least two or all of the power amplifiers of the component can form a functional block. At least two or all of the low-noise amplifiers of the component can form a further functional block. At least two or all switches of a device provided for a multiband application may form a separate functional block or be implemented together with the low-noise amplifiers in a common block. The low-noise amplifiers that Power amplifiers and the switches can also form a common functional block.

In a functional block circuit blocks can be realized, which are arranged in different signal paths. For example, a functional block may comprise a circuit block arranged in the first signal path and at least one further circuit block arranged in the second signal path. The first and second signal paths may be a transmit path or a receive path. In an advantageous variant, circuit blocks are realized in a function block, which fulfill similar functions in the respective signal path.

The function blocks comprise, in a variant, circuit blocks which are arranged in one and the same signal path and follow one another. In a functional block, at least two circuit blocks of at least two independent signal paths, that is to say a total of at least four circuit blocks, can also be integrated.

Each chip has at least one function block. Each functional block has at least one circuit block. The partitioning of the electrical circuit to be realized in the component into functional blocks takes place in an advantageous variant according to the technology used for the realization of circuit elements of the circuit. It is advantageous to realize the circuit components to be executed in one and the same technology in a common chip. For example, it is advantageous to integrate preferably all the semiconductor components of the circuit implemented in one and the same technology in a common semiconductor chip and at least some of the passive circuit elements of this circuit in at least one multilayer substrate. According to this concept, the chips are relatively simple to manufacture components that can be very easily and inexpensively electrically connected together and encapsulated to form the device by a potting compound.

The device may comprise at least one semiconductor chip, which is embodied for example in SiGe technology or GaAs technology. The component can also have at least two semiconductor chips, each comprising at least one functional block of the circuit, these chips being implemented, for example, in various semiconductor technologies.

As a base material for the multilayer substrate in particular ceramic, laminate and liquid crystal polymers (in English Liquid Crystal Polymer or LCP) into consideration. As a ceramic LTCC is particularly suitable. LTCC stands for Low Temperature Cofired Ceramics.

It is possible, for example, a first part of the passive circuit elements in a first multilayer substrate preferably made of ceramic and a second part of the passive circuit elements in a second multilayer substrate z. B. from LCP to realize.

The circuit may be partitioned according to the frequency bands, wherein the different frequency bands associated with function blocks are realized in different chips.

Partitioning the circuit according to the transmission mode, e.g. As sending or receiving, is particularly advantageous. It may be advantageous to implement the circuit circuits arranged in a transmission path and the circuit circuits arranged in a reception path in separate chips in order to reduce the crosstalk between the transmission path and the reception path.

It is possible to partition the multiband circuit with a number N1 transmission paths and a number N2 reception paths such that in a first functional block at least N1 circuit blocks of the transmission paths and in a second functional block at least N2 circuit blocks of the reception paths are integrated. For example, at least two, preferably all passive circuit blocks of the transmission paths and in the second functional block at least two, preferably all passive circuit blocks of the reception paths can be arranged in the first function block.

As a passive circuit block, a circuit block is referred to exclusively the passive circuit elements such. B. comprises a capacitance, an inductance and / or a line. The passive circuit blocks of the transmission paths each comprise at least one circuit selected from at least one transmission filter, a diplexer, a duplexer and a balun. The passive circuit blocks of the transmission paths each comprise at least one circuit selected from at least one reception filter, a diplexer, a duplexer and a balun.

The passive circuit blocks of the transmission paths and the reception paths may in one further embodiment belong to one and the same function block.

The component preferably has a plurality of functional blocks which are electrically connected to one another. The distribution of the circuit to be realized in the component in functional blocks can in principle be arbitrary.

Each functional block of the respective chip is preferably assigned a separate three-dimensional region of the chip which does not overlap with the regions of other functional blocks or is separated from it by an insulating zone. The isolation zone is substantially free of conductive structures, in particular of such structures which are provided in the circuit to be realized as circuit elements except for connecting lines which connect the functional blocks with each other.

In the following, the specified component and its advantageous embodiments will be explained with reference to schematic and not to scale figures. Show it:

1 in cross-section, a component with leadframe structures and multiple chips;

2A the equivalent circuit of a transceiver with a transceiver circuit and a front-end circuit, which is divided into two functional parts;

2 B a view of the still connected to the leadframe device with the circuit according to the 2A from above through the device;

3A the equivalent circuit of a transceiver with a transceiver circuit and a front-end circuit, which is divided into three functional parts;

3B a view of the isolated device with the circuit according to the 3A from above through the device;

3C a view of another device with the circuit according to the 3A from above through the device;

3D a view of another device with the circuit according to the 3A with two second leadframe structures, one of which has two interconnected conductive surfaces;

4A an equivalent circuit diagram of a fully integrated transceiver with a transceiver circuit and a front-end circuit, which is divided into three functional parts, all three functional parts are realized in a common component;

4B a view of the isolated device with the circuit according to the 4A from above through the device.

In the 2A the equivalent circuit diagram of a transceiver circuit is shown, which at least partially in a device according to the 1 and 2 B is realized. In the 3A the equivalent circuit diagram of a component is shown, the structure of which based on variants in accordance with 3B . 3C and 3D is explained. In the 4A the equivalent circuit of another device is shown, the exemplary structure in the 4B is explained.

The in the 2A . 3A shown circuit is designed for a multiband transceiver. This circuit comprises a front-end module circuit 20 , preferably as a chip component 1 is realized, and electrically connected to the circuit 20 connected transceiver circuit 30 that in another chip component or together with the circuit 20 in the chip component 1 is realized. With dashed and dash-dotted lines, the partitioning of this circuit is indicated in the function blocks corresponding to the chips.

The front-end module circuit 20 has two transmit-receive paths that pass through a crossover 10 to an antenna 41 are connected. The crossover 10 has a first filter 111 which is arranged in the first transmission reception path TR1 and a second filter 112 which is arranged in the second transmission reception path TR2. The filters 111 . 112 are realized as bandpass filters. Alternatively, the filter 111 as a low pass and the filter 112 be realized as a high pass, or vice versa. Between the crossover 10 and the antenna 41 A separation capacity C is arranged to block DC components of transceiver signals.

The first transmission reception path TR1 is by means of a first switch 131 alternately connected to a first transmission path TX1 or a first reception path RX1. The second transmission reception path TR2 is by means of a second switch 132 alternately connected to a second transmission path TX2 or a second reception path RX2.

In the first transmission path TX1 is a Leistungsverstarker 171 and a transmission filter 181 arranged. In the second transmission path TX2 a power amplifier 172 and a transmission filter 182 arranged. The filters 151 . 152 . 171 . 172 are realized as band passes. The transmission filters 171 . 172 may alternatively be realized as low passes.

In the first reception path RX1 is a low-noise amplifier 141 and a receive filter 151 arranged. In the second reception path RX2 is a low-noise amplifier 142 and a receive filter 152 arranged.

The desk 131 . 132 is between the crossover 10 and the respective amplifier 141 . 142 . 171 . 172 arranged. The amplifier 141 . 142 . 171 . 172 is between the switch 131 . 132 and the respective filter 151 . 152 . 181 . 182 arranged.

Due to the selected circuit topology are the switches 131 . 132 in close proximity to the amplifier modules 141 . 142 . 171 . 172 , Thus, an advantageous integration of the amplifiers and the switches within a common semiconductor chip 22 possible. The filters 151 . 152 . 181 . 182 and the baluns 161 . 191 are according to the in 2A featured variant also integrated in this chip.

Between the receive filter 151 and the output of the first receive path RX1 is a balun 161 arranged. Between the transmission filter 172 and the input of the second transmission path TX2 is a balun 191 arranged. Instead of a series connection of the filter and the balun, a balanced filter can be used. The paths RX2 and TX1 may also be provided with baluns in a corresponding manner if the electrical ports of the transceiver circuit connected to these paths 30 are formed symmetrical.

The crossover 10 and the separation capacity C are in a common chip 21 integrated.

The amplifiers 141 . 142 and the switches 131 . 132 are arranged side by side and in a functional block 14 integrated. The amplifiers 171 . 172 are arranged side by side and in another functional block 17 integrated. The functional blocks 14 . 17 , the filters 151 . 152 . 181 . 182 and the baluns 161 . 191 are in a common chip 22 integrated. The filters 151 . 152 . 181 . 182 and the baluns 161 . 191 are preferably arranged side by side and together form a filter block of the chip 22 ,

In 3A a further Partitionierungsmoglichkeit the already explained front-end circuit is shown. According to the in 3A presented variant are the function blocks 14 and 17 in an amplifier chip 23 realized. The crossover 10 is here as in 2A in the chip 21 realized, with the filters 151 . 152 . 181 . 182 as well as the baluns 161 . 191 in another, with the chips 21 and 22 not identical, chip 24 are realized, see the 3A ,

In principle, there is the possibility of the function blocks 14 and 17 in an amplifier chip 23 to realize while the crossover 10 , the filters 151 . 152 . 181 . 182 and the baluns 161 . 191 all in a common chip, z. B. the chip 21 , are realized.

In 1 is designed as a chip component, isolated device 1 shown the chips 21 and 22 , first leadframe structures 91 and a second leadframe structure 92 . 93 having. The chips 21 and 22 are on the preferably grounded conductive surface 92 the second leadframe structure arranged side by side. The chips are over their backs by means of a bonding layer 96 such as B. an adhesive layer with the conductive surface 92 firmly connected.

The connection layer can be electrically insulating. The connection layer may also be electrically conductive. It is preferably characterized by a high thermal conductivity.

On top of the chips 21 . 22 are connection surfaces 81 arranged. The connection surfaces 81 the chips 21 and 22 are by means of bonding wires 97 conductive with the first lead frame structures 91 connected. The chips 21 and 22 are by means of bonding wires 98 conductively connected. The chips 21 . 22 , the bonding wires 97 . 98 and the leadframe structures 91 . 92 . 93 are by means of a potting compound 99 shed.

The device according to the 1 is in the 2 B shown as not yet isolated component. The leadframe has a leadframe 90 and more coupled to these leadframe structures 91 . 92 . 93 on. The component 1 is firmly connected to the leadframe and can be singulated along the dot-and-dash sawing lines. In the 3B . 3C . 3D and 4B Isolated components are shown, from the ladder frame 90 were separated.

The ladder frame 90 is fixed to the first leadframe structures prior to singulation of the device 91 connected. The ladder frame 90 is also via at least one conductive web, in this case via two conductive webs 93 with a conductive surface 92 firmly connected, which serves as a carrier substrate for the chips 21 . 22 is provided. The structures 92 . 93 together form a second leadframe structure.

The structures 90 . 91 . 92 and 93 form before the separation of the component 1 together a piece. In other words, the leadframe is structured in such a way that, in addition to the preferably rectangular or square leadframe, the first leadframe structures opening into this frame 91 , at least one relatively large area second leadframe structure 92 and at least one jetty 93 are formed.

The bridges 93 connect the conductive surface 92 with the ladder frame 90 , The bridges 93 are in the variant according to the 2 B . 3B opposite the ladder frame 90 or the edges of the device obliquely aligned. But you can also like in the 3C . 3D . 4D be aligned at right angles to the edges of the device.

The first leadframe structures 91 have structures among other things 91a on, which represent floating conductive surfaces as they touch the chips 91 . 92 not connected. The structures 91a represent dummy terminals of the device. They are used for example for reasons of symmetry.

The outward-facing edges of the first leadframe structures 91 fall with the edges of the bottom of the device 1 together.

The arrangement of all first leadframe structures 91 and possibly conductive surfaces 92 . 921 . 922 . 923 forms the footprint of the component.

In all variants presented in the figures except for the 3C the bottom of the device is divided into a central area and a peripheral edge area. The first leadframe structures 91 are arranged in the edge region along the outline of the base of the device. The conductive surfaces 92 . 921 . 922 . 923 are arranged in the middle area.

In the 3C is presented a variant in which the first leadframe structures 91 form two parallel rows that are parallel to the first edges of the bottom of the device. Along the second edges, which are perpendicular to the first edge, no electrical connections of the device are provided. In this case, the underside of the component is divided in a lateral direction into two edge regions and a middle region arranged between them. The first leadframe structures 91 are arranged in the border areas. The conductive surface 92 and the conductive bars 93 are arranged here in the middle area of the bottom.

The conductive surface 92 is in the in 3C retracted variant withdrawn from the edges of the device. In principle, there is a possibility that the conductive surface 92 in this case, extends to the second edge of the device, with the first leadframe structures 91 are not busy.

In variants according to 3B . 3C are on a common conductive surface 92 three chips 21 . 23 . 24 arranged. In contrast, in the variant according to the 3D a separate conductive area per chip provided. The chip 21 is on the conductive surface 921 , the amplifier chip 23 on the conductive surface 922 and the chip 24 on the conductive surface 923 arranged.

The conductive surface 921 . 923 is in the variant according to 3D by means of the bridge 93 to a first leadframe structure 91b connected. The conductive surfaces 921 . 922 are by means of the footbridge 925 connected together and form together with the structures 91b . 93 and 925 a second leadframe structure. The interconnected, in the 3D right arranged structures 91b . 93 and the conductive surface connected to it 923 together form another second leadframe structure.

The arrangement of chips on separate, non-interconnected or only by a narrow web coupled to each other conductive surfaces has the advantage that heat transfer from one chip to the other can be reduced or substantially prevented. In this way, in particular with respect to the temperature changes sensitive functional block of the device such. B. the chip 24 in which the transmission filter 181 . 182 , the receive filter 151 . 152 and the baluns 161 . 191 integrated, thermally of chips 21 . 23 be insulated with other functional blocks, in which more heat is generated. The latter is especially true for the amplifier block that is in the chip 23 is realized. See the 3A ,

In 4A is the block diagram of a WiMAX dual band radio presented. The circuit is preferably provided for processing transceiver signals of a 2 GHZ band and a 3 GHz band. With dashed and dash-dotted lines, the partitioning of this circuit is indicated in the function blocks corresponding to the chips.

In this example, there are two antennas 41 . 42 intended. The antenna 41 only serves to receive received signals of the two frequency bands. The antenna 42 serves both for receiving received signals and for transmitting transmission signals of the two frequency bands.

To the receiving antenna 41 is a diplexer 100 connected, which separates the received signals of the two frequency bands from one another and in the receive path RX11, RX21 of the corresponding transmission system passes.

To the antenna 42 is a switch 131 connected, which connects the antenna path optionally with a transmit path TX or a receive path RX. In the transmission path TX, the transmission signals of the two frequency bands are transmitted by the diplexer 102 separated and directed into the transmission path TX1, TX2 of the corresponding transmission system. In the reception path RX, the reception signals of the two frequency bands are transmitted by the diplexer 101 separated and fed into the receive path RX1, RX2 of the corresponding transmission system.

The transmission paths TX1, TX2 have unbalanced inputs. Receive paths RX1, RX2, RX11, RX21 have balanced outputs. For balancing the signal paths, a balun is used 161 . 191 or a balanced filter.

In this case, the component additionally has the transceiver circuit 30 integrated. The transceiver circuit 30 forms a functional block of the realized in the device circuit, which is realized as an IC, ie an integrated circuit or as a separate chip.

Another function block comprises the passive circuit blocks arranged in the transmission path: the transmission filters, the baluns and the diplexer 102 , This functional block is in the chip 27 realized.

Another functional block comprises the passive circuit blocks arranged in the reception path: the reception filters 151 . 152 . 153 . 154 , the baluns 161 and the diplexers 100 . 101 , This functional block is in the chip 26 realized.

Another functional block includes the circuit blocks with semiconductor components: the switch 131 and the amplifier block 17 with two power amplifiers. This functional block is in the chip 25 realized.

The chip 25 is with the chips 26 and 27 Conductive connected by bonding wires. The chip 27 is with the chips 25 and 30 Conductive connected by bonding wires. chip 26 is with the chips 25 and 30 conductively connected by means of the bonding wires. All chips 25 . 26 . 27 . 30 are on a common conductive surface 92 attached and with the first leadframe structures 91 conductively connected by means of the bonding wires.

In a variant of in 4A presented circuit is arranged in at least one receiving path an LNA. All LNAs are preferably implemented in a functional block and integrated in a common chip.

The device is not on the circuits according to the 2A . 3A and 4A , Restricting the relative arrangement of circuit blocks or the proposed partitioning of the circuits in functional blocks. The switch blocks can be combined with each other to form a function block. There are no restrictions on the number of frequency bands for which the device is designed or the number of signal paths. For example, it is possible to transmit transmission signals from two different frequency bands in a common transmission path.

Instead of switches, duplexers, diplexers or their combination can be used. The material information is not a restriction.

LIST OF REFERENCE NUMBERS

1

module

10

crossover

100, 101, 102

diplexer

111, 112

Filter the crossover

131, 132

switch

141, 142

LNA

151, 152

receive filter

153, 154

receive filter

161

balun

171, 172

transmission amplifier

181, 182

transmission filter

191

balun

14

first amplifier block

17

second amplifier block

20

Front-End Module

21, 22, 24

chip

23

Amplifier chip

25, 26, 27

chip

30

integrated transceiver circuitry

41, 42

antenna

81

pads

90

leadframe

91

first leadframe structure

91a

floating first leadframe structure

91b

to the conductive surface 92 connected first leadframe structure

92

conductive area of the second leadframe structure

93

conductive footbridge

96

link layer

97, 98

bonding wire

99

potting compound

C

cutting capacity

RX

receive path

RX1, RX11

first reception path

RX2, RX22

second reception path

TR1

first transceiver path

TR2

second transceiver path

TX

transmission path

TX1

first transmission path

TX2

second transmission path

Claims (15)

Electrical component - with first leadframe structures ( 91 ), which are provided as electrical connections of the component, with at least one second leadframe structure ( 92 . 93 ), on the at least two chips ( 21 . 22 ) are fastened next to one another via their rear sides, - the at least two chips ( 21 . 22 ) on their upper side each connection surfaces ( 81 ), which by means of first bonding wires ( 97 ) with the first leadframe structure ( 91 ), wherein - in the first chip ( 22 ) Semiconductor elements of the device realized in the circuit are arranged, - wherein in the second chip ( 21 ) in passive circuit blocks of the circuit, a function selected from a transmit filter, a receive filter, a crossover and a balun is realized, and the second chip is free from semiconductor elements. Component according to claim 1, - wherein the at least one second leadframe structure ( 92 . 93 ) at least one conductive surface ( 92 . 921 . 922 . 923 ), on the at least one of the two chips ( 21 . 22 ), wherein the at least one second leadframe structure ( 92 . 93 ) at least one to the conductive surface ( 92 ) connected conductive web ( 93 extending to a line extending along an outwardly facing edge of at least one of the first leadframe structures (FIG. 91 ) runs Component according to Claim 1 or 2, - the at least two chips ( 21 . 22 ) on a common conductive surface ( 92 ) are arranged. Component according to Claim 2, - the chips ( 21 . 22 . 23 ) a first chip ( 21 ) and a second chip ( 23 ), wherein the at least one conductive surface ( 92 . 921 . 922 . 923 ) a first conductive surface ( 921 ) and a second conductive surface ( 922 ), wherein the first chip ( 21 ) on the first conductive surface ( 921 ) and the second chip ( 23 ) on the second conductive surface ( 922 ) is arranged. Component according to one of claims 1 to 4, - Wherein at least two of the second leadframe structures are not electrically connected to each other. The component according to claim 5, wherein the following applies to each of the second leadframe structures which are not electrically connected to each other: the leadframe structure has at least one of the conductive surface ( 921 . 923 ) connected web ( 93 extending to a line extending along an outwardly facing edge of at least one of the first leadframe structures (FIGS. 91 ) runs. Component according to one of Claims 1 to 6, - the following applies to at least one of the second leadframe structures: the second leadframe structure has at least two conductive surfaces ( 922 . 923 ), which by means of a conductive web ( 925 ), wherein on each conductive surface ( 922 . 923 ) at least one of the chips ( 21 . 23 ) is arranged. Component according to one of Claims 1 to 7, - the chips ( 21 . 22 . 23 ) by means of second bonding wires ( 98 ) are electrically connected together. Component according to one of Claims 1 to 8, - the first leadframe structures ( 91 ) conductive structures ( 91a ), which are not electrically connected to the chips ( 21 . 22 ) to have. Component according to one of Claims 1 to 9, - the arrangement of the chips ( 21 . 22 ) and the first and second leadframe structures by a cured potting compound ( 99 ) is mechanically stabilized. Component according to one of claims 2 to 10, - wherein the at least one conductive surface ( 92 ) with at least one of the first leadframe structures ( 91b ) by means of a conductive web ( 93 ) connected is. Component according to one of Claims 1 to 11, - the chips ( 21 . 22 ) a first chip ( 21 ) and a second chip ( 22 ), wherein - at least one function is realized in the first chip, selected from a power amplifier, a low-noise amplifier, a switch, a detector, a directional coupler. Component according to Claim 12, - Wherein in the first and second chip, a multiband multimode WLAN front-end module is realized. Component according to Claim 12 or 13, - in the first chip a transceiver circuit ( 30 ) is realized. Component according to Claim 12 or 13, characterized - Wherein a transceiver circuit is realized in at least one other chip.

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