DE102006055742A1 - Semiconductor component arrangement, has control electrodes controlled in operating condition in which transistor is blocked such that potentials of control electrodes gradually provide potential gradient in drift zone - Google Patents

Abstract

The The invention relates to a semiconductor device arrangement with a Semiconductor body (1), a MOS transistor having a gate electrode (90) and in the Semiconductor body a source zone (2), a body zone (3), a drift zone (4) and a Drain zone (5), at least two control electrodes (91, 92, ..., 9n) arranged adjacent to the drift zone (4) and of these are separated by a dielectric (62), and with a Drive circuit (10) connected to the gate electrode (90), the control electrodes (91, 92, ..., 9n) and the drain zone (5) is connected and the is adapted to, in a first operating state, in which the MOS transistor which has at least two control electrodes (91, 92, ..., 9n) in such a way that a conductive channel along of the second dielectric in the drift zone (4) is formed, and in a second operating state in which the MOS transistor blocks, the control electrodes (91, 92, ..., 9n) in such a way that potentials of the control electrodes (91, 92, ..., 9n) gradually the potential course in the drift zone (4) follow.

Description

The The invention relates to a semiconductor device arrangement, in particular a power semiconductor device arrangement.

One Goal in the development of power semiconductor devices consists in it, components with as possible produce high reverse voltage, yet a low on-resistance have and at the same time as possible have low switching losses.

One way to reduce the on-resistance of a power semiconductor device for a given blocking capability is to use the compensation principle described in, for example, US Pat US 4,754,310 (Coe) US 5,216,275 A1 (Chen) US 5,438,215 or DE 43 09 764 C2 (Tihanyi) is described.

A further possibility for reducing the on-resistance of a semiconductor component consists in the provision of a field electrode which is dielectrically insulated in relation to the drift zone. Such components are in US 4,903,189 (Ngo) US 4,941,026 (Temple), US 6,555,873 B2 (Disney) US 6,717,230 B2 (Kocon) or US 6,853,033 B2 (Liang) described.

The The object of the present invention is a semiconductor device arrangement with a MOS transistor, which has a low on-resistance at the same time having high reverse voltage available put.

These The object is achieved by a semiconductor device arrangement according to claim 1 solved. Different embodiments and further developments are the subject of the dependent claims.

The inventive semiconductor device arrangement comprises a semiconductor body and a MOS transistor having one disposed in the semiconductor body Source zone of a first conductivity type, one adjacent to the source zone Bodyzone of a second conductivity type, one arranged in the semiconductor body Drain zone, a drift zone located between the drain zone and the body zone and a gate electrode adjacent to the body zone arranged and separated from this by a first dielectric is. Furthermore, the semiconductor device arrangement comprises at least two control electrodes adjacent to the drift zone along a surface of the semiconductor body arranged and separated from this by a second dielectric are.

The Component arrangement also includes a drive circuit connected to the gate electrode, the control electrodes and the drain is connected and that is designed to in a first operating state in which the MOS transistor conducts, to control the at least two control electrodes such that a conductive channel along the second dielectric in the drift zone forms, and in a second operating state in which the MOS transistor blocks the control electrodes in such a way that potentials the control electrodes stepwise the potential profile in the drift zone consequences.

The Formation of a conductive channel in the drift zone controlled by the control electrodes arranged adjacent to the drift zone serve to reduce the on-resistance in comparison to MOS transistors without such control electrodes. The adaptation of the electrical potentials the control electrodes in the case of blocking to the electrical potential in The drift zone reduces the stress load on the second dielectric and allows with it, a thin one Dielectric layer to provide as a second dielectric, which in turn in the conducting state, the formation of the conductive channel is favored. The conducting channel here is an accumulation channel, if the Drift zone of the same conductivity type as the source zone is and a Inversion channel when the drift zone doped complementary to the source zone is.

at blocking MOS transistor, one between the drain zone and the Sourcezone adjacent reverse voltage mainly absorbed by the drift zone, in which a space charge zone spreads. An electrical potential in the drift zone this starts in the direction of the body zone the drain zone - ever according to conductivity type of the drift zone - linear to or from linear if the drift zone is doped very low.

embodiments The invention will be explained in more detail with reference to figures. The figures serve only to embodiments of the To explain the invention the structures shown in the figures are therefore not necessarily to scale and not necessarily scalable.

1 shows an embodiment of a semiconductor device arrangement according to the invention, comprising a semiconductor body, a MOS transistor having a drift path, a plurality of adjacent to the drift path control electrodes and a drive circuit for the control electrodes.

2 illustrates drive potentials of the control electrodes during a blocking and a conducting state of the MOS transistor.

3 shows a first embodiment the drive circuit.

4 shows a further embodiment of the drive circuit.

5 shows a detail of an embodiment of the semiconductor device arrangement according to the invention, in which the control electrodes are arranged in a trench of the semiconductor body.

6 shows a detail of another embodiment of a semiconductor device arrangement according to the invention, in which the control electrodes are arranged above a surface of the semiconductor body.

7 shows a modification of the in 6 illustrated semiconductor device arrangement.

In denote the figures, unless otherwise indicated, like reference numerals same components with the same meaning.

1 shows an embodiment of a semiconductor device arrangement according to the invention. This component arrangement comprises a semiconductor body 100 in the example, two semiconductor layers 101 . 102 of which a first semiconductor layer 101 For example, a semiconductor substrate and a second semiconductor layer is, for example, an epitaxial layer applied to the substrate. These two semiconductor layers 101 . 102 are doped complementary to each other in the illustrated example.

The device arrangement further comprises a MOS transistor with one in the semiconductor body 100 integrated source zone 2 a first conductivity type, one to the source zone 2 subsequent body zone 3 a second conductivity type, one spaced from the body zone 3 arranged drainage zone 5 of the first conductivity type and one between the drain zone 5 and the bodyzone 3 arranged drift zone 4 , The illustrated MOS transistor is realized as a lateral MOS transistor by the source zone 2 and the drainage zone 5 in a lateral direction of the semiconductor body 100 spaced apart from each other. The MOS transistor also has a gate electrode 90 on, which is adjacent to the bodyzone 3 arranged and through a first dielectric layer 61 , hereinafter referred to as gate dielectric layer, dielectric to the body zone 3 is isolated. The gate electrode serves to control an inversion channel in the body zone 3 of the MOS transistor and is in the example above a front side 103 of the semiconductor body 100 arranged and connected to a gate terminal G.

The source zone 2 is through a source electrode 21 , which forms a source terminal S of the device, and the drain zone 5 is through a drain electrode 51 , which forms a drain terminal D of the device, contacted. The source zone 2 and the bodyzone 3 are in basically known manner via the source electrode 21 shorted, with the source electrode 21 in the example over a heavily doped junction zone 31 to the bodyzone 3 connected.

The in 1 illustrated MOS transistor is realized as an n-channel MOSFET. The source zone 2 , the drain zone 5 and the drift zone 4 are n-doped in this device, the body zone 3 is p-doped, with a doping concentration of the drift zone 4 less than that of the source zone 2 and the drainage zone 5 , Of course, the invention is not limited to n-channel MOSFET but may rather be applied to p-channel MOSFET or IGBT. In a p-channel MOSFET, the individual device zones are complementary to the device zones of in 1 doped n-MOSFET shown. In an IGBT, the drain zone is p-doped, and thus doped complementary to the drift zone.

The semiconductor device arrangement further comprises at least two control electrodes 91 . 92 , ..., 9n which is adjacent to the drift zone 4 are arranged and the opposite of the drift zone by a second dielectric layer 62 are dielectrically isolated. The gate dielectric layer 61 and this further dielectric layer 62 can be realized as a common dielectric layer of uniform thickness, the gate dielectric layer 61 and this further dielectric layer 62 However, they can be different in thickness. The two dielectric layers 61 . 62 may for example consist of a semiconductor oxide, for example silicon oxide when using a semiconductor body made of silicon. However, materials with a higher dielectric constant, in particular so-called high-k materials, such as HfO ₂ , which have a relative dielectric constant greater than 30, are particularly suitable as the dielectric material for the second dielectric layer.

For controlling the control electrodes 91 , ..., 9n is a drive circuit 10 present to the control electrodes 91 , ..., 9n , the gate electrode 90 and the drain electrode 51 is coupled.

The semiconductor device arrangement shown can assume two different operating states, a first operating state in which the MOS transistor is turned on, and a second operating state in which the MOS transistor is driven in a blocking manner. The MOS transistor conducts at applied voltage between at the source and drain terminals, if at its gate electrode 90 an electrical potential is sufficient that is sufficient in the bodyzone 3 an inversion channel between the source zone 2 and the drift zone 4 along the gate dielectric 61 train. The MOS transistor blocks if no suitable for forming an inversion channel electrical potential at the gate electrode 90 is present and when a reverse voltage between the drain and source D, S is applied. This blocking voltage is a positive drain-source voltage for an n-MOSFET. During this blocking state, a space charge zone spreads in the drift zone 4 starting from the pn junction between the bodyzone 3 and the drift zone 4 out.

The withstand voltage of the illustrated device is of the doping concentration in the drift zone 4 dependent, wherein the dielectric strength is higher, the lower the doping of the drift zone 4 is. The dielectric strength of the illustrated MOS transistor is further complemented by the drift zone 4 doped semiconductor substrate 101 influenced, in a manner not shown to the source electrode 21 or the source zone 2 connected. In the case of a blocking MOS transistor, a space charge zone forms at the pn junction between the drift zone 4 and the substrate, resulting in the drift zone 4 existing dopant charges are at least partially compensated.

The drive circuit 10 In the case of the device arrangement shown in the example, during operation it generates one between the gate electrode 90 and the drain electrode 51 voltage applied to the MOS transistor driving potentials for the adjacent to the drift zone 4 arranged control electrodes 91 , ..., 9n , These drive potentials are selected such that, when the MOS transistor is turned on, an accumulation channel in the drift zone occurs 4 between the drain zone 5 and the bodyzone 3 along the second dielectric layer 62 formed. The thickness of the further dielectric layer 62 is here so on the drive potential of the control electrodes 91 , ..., 9n tuned that the accumulation channel can form, the effect of the charge carrier accumulation in the drift zone 4 the more pronounced the thinner the further dielectric 62 is.

The charge carrier density in a drift zone 4 forming accumulation channel is in this case so high that the on resistance of the MOS transistor, which is essentially determined by the ohmic resistance of the drift zone, compared to conventional MOS transistors at the same doping concentration of the drift zone is substantially reduced. The control electrodes thus allow for the same Dotierungskon concentration of the drift zone, a reduction of the on-resistance or the same on-resistance, a reduction of the doping concentration of the drift zone, and thus an increase in the dielectric strength.

The dopant charge in the drift zone 4 In particular, it can be substantially smaller than the so-called breakdown charge, which in the case of silicon is 2 × 10 ¹² cm ^-2 . There is even the possibility of the drift zone being complementary to the drain zone 5 to dope, in which case an inversion channel along the control electrodes 91 , ..., 9n in the drift zone 4 forms and the space charge zone is formed at blocking driven component starting from a then existing between the drift zone and the drain zone pn junction in the drift zone. The term "conductive channel in the drift zone" is used below for both an accumulation channel and an inversion channel.

The drive potentials of the control electrodes 91 , ..., 9n when the MOS transistor is conductive can correspond to the gate potential, which can be achieved in that the drive circuit, the control electrodes 91 , ..., 9n connected to gate potential at the conducting MOS transistor.

With the MOS transistor blocked and the space charge zone propagating in the drift zone, the electrical potential in the drift zone increases 4 approximately linear starting from the body zone 3 to the drain zone 5 at. To limit or limit a voltage load of the control electrodes 91 , ..., 9n with blocking MOS transistor controls the drive circuit 10 the control electrodes 91 , ..., 9n such that the potentials of the in the lateral direction of the semiconductor body 100 juxtaposed control electrodes 91 . 92 , ..., 9n the potential in the drift zone 4 gradually so that one over the second dielectric layer 62 applied voltage is not greater than a predetermined limit or a predetermined "step height", which is matched to the thickness of the dielectric layer and selected so that the dielectric layer 62 does not break if this voltage is applied.

In 2 are the potential course in the drift zone 4 and the electrical potentials of the control electrodes 91 . 92 , ..., 9n for a semiconductor device arrangement - with six control electrodes in the example. Such a semiconductor device arrangement is for better understanding in the upper part of 2 shown. In the lower part of the figure, the potential curves as a function of a spatial coordinate x are shown, wherein the potentials shown refer to the source potential and it is assumed that in the second operating state, ie with blocking MOS transistor the gate-source voltage is zero. A position of the pn junction between the bodyzone 3 and the drift zone 4 for purposes of explanation, has the location coordinate x = 0, a transition between the drift zone 4 and the drainage zone 5 has the (normalized) location coordinate x = 1. The potential U _DRIFT in the drift zone 4 increases with increasing distance x to the pn junction at least approximately linear and reaches at the boundary to the drain zone 5 (x = 1) an applied reverse voltage U _s , which corresponds to the drain-source voltage in the second operating state. With U91, ..., U9n, the individual potentials of the control electrodes are shown in FIG 91 , ..., 9n designated.

The potentials U91, ..., U9n of the control electrodes 91 . 92 , ..., 9n Gradually increase from control electrode to control electrode in the direction of the higher potential in the drift zone 4 , in the example in the direction of the drain zone 5 , and thus gradually follow the potential U _DRIFT in the drift zone 4 , A voltage drop between each of the control electrodes 91 . 92 , ..., 9n and the drift zone 4 is not greater than a "step height". The dielectric strength of the second dielectric 6 can thus be chosen much smaller, as in a comparison case, in which the potentials of the control electrodes would remain in the blocking case at gate potential.

Due to the lower voltage stress, the thickness of the dielectric can 62 be chosen correspondingly small, whereby a pronounced accumulation effect is achieved. For a previously described semiconductor device arrangement with a MOS power transistor having a breakdown voltage of 60 V, a reduction of the on-resistance by a factor of 5 compared to a known lateral DMOS transistor was determined by simulations. The charge carrier mobility at the surface 103 of the semiconductor body was for simulation two thirds of the charge carrier mobility in the drift zone in the interior of the semiconductor body 100 , As dielectric layers 61 . 62 For the purposes of the simulation, silicon oxide layers with a thickness of 25 nm were assumed as the doping concentration of the drain zone 5 8 × 10 ¹⁵ cm ^-3 at a vertical thickness of 1 micron. The nominal gate voltage to fully turn on the transistor was in the simulation 8V ,

The 3 and 4 show embodiments of the drive circuit 10 , the previously described control of the control electrodes 91 , ..., 9n guaranteed. A particular advantage of the embodiments described below is that the drive circuit 10 no additional power sources needed, as they drive potentials of the control electrodes 91 , ..., 9n derives from a voltage applied between the drain terminal D and gate G voltage.

At the in 3 illustrated embodiment, the drive circuit 10 a series circuit of rectifier elements D1, D2, ..., Dn, in the example diodes, which is connected at one end to the gate electrode G. This series connection has intermediate taps K1,..., Kn-1 between two respective diodes, to each one of the control electrodes 91 , ..., 9n-1 connected. The starting from the gate electrode 90 in the direction of the drain electrode 51 successive control electrodes 91 , ..., 9n-1 are here at the starting from the gate electrode 90 successive intermediate taps K1, ..., Kn-1 connected, ie in general is a starting from the gate electrode i-th control electrode 9i to one from the gate electrode 90 i-th intermediate tap Ki connected, with i = 1 ... n-1. One from the gate electrode 90 last control electrode 9n the control electrode chain is connected to one of the gate electrodes 90 remote terminal Kn of the diode chain D1, ..., Dn connected. The series circuit is connected via this terminal Kn via a further rectifying element D, which is also formed in the example as a diode, to the drain electrode 51 connected. This further diode D is in the example opposite to the diodes D1, ..., Dn of the diode chain, which are each oriented the same, poled.

In the first operating state, in which the MOS transistor is turned on, is - for the illustrated case of an n-channel MOS transistor - the potential of the gate electrode 90 higher than the potential of the drain zone 5 , The diodes D1, ..., Dn of the diode chain are in this case connected so that at the control electrodes 91 , ..., 9n sets an electric potential that is substantially the gate potential of the gate electrode 90 equivalent. These diodes D1, ..., Dn are for this purpose starting from the gate electrode 90 Poled in the direction of flow. In the static case, ie when the component is switched on, no current flows from the gate electrode 90 on the control electrodes 91 , ..., 9n flows, the voltage drop across the directionally poled diodes D1, ..., Dn is at least approximately zero, so that the potentials of the control electrodes 91 , ..., 9n the potential of the gate electrode 90 equivalent. One between the gate electrode 90 and the drain electrode 51 applied voltage is received in this operating state of the other diode D, which is poled at a positive voltage between the gate G and drain D in the reverse direction. By the at the control electrodes 91 , ..., 9n applied gate potential, which is higher than the potential of the drift zone when the MOS transistor is conductive 4 forms in the drift zone 4 along the second dielectric layer 62 an accumulation channel, which contributes significantly to reducing the on-resistance.

The accumulation channel is formed here only when already an inversion channel in the body zone 3 is present and if this causes the electrical potential of the drain zone 5 or the drift zone 4 in the direction of the potential of the source zone 2 decreases. The gate potential applied to the MOS transistor is in this case, in particular, at the on-resistance of the component with a formed inversion channel but not yet formed accumulation channel or the electrical potential of the drift zone 4 tuned at not yet trained accumulation channel that the formation of such a channel is made possible. In order to ensure the formation of such an accumulation channel, in the case of conductive activation of the component, it is possible, in particular, to apply a higher gate potential at the beginning of the activation process and then reduce this potential after the accumulation channel has been formed.

In the second operating state, in which the MOS transistor is driven in a blocking manner, the potential of the drain zone is-for the illustrated case of an n-channel MOS transistor 5 higher than the potential of the gate electrode 90 , In this case, the further diode D is polarized in the forward direction while the diodes D1, ..., Dn of the diode chain are poled in the reverse direction. The diode chain works here as a voltage divider, wherein the proportion of the voltage applied across the individual diodes to the total drain-gate voltage depends on the blocking behavior, ie on the diode characteristics of the individual diodes.

When using diodes, which have at least approximately identical characteristic behavior, this voltage is evenly distributed to the diodes D1, ..., Dn, ie across the diodes is in each case an equal proportion of the total clamping voltage. This proportion is in each case Udg / n, where Udg denotes the drain-gate voltage and n denotes the number of diodes D1,..., Dn of the diode chain. The applied voltage across the diodes corresponds to the difference between the electrical potentials of two adjacent control electrodes or the "step height". The electrical potentials of the control electrodes in this case start from that of the gate electrode 90 nearest control electrode 91 in the direction of the drain zone 5 gradually up to the drain zone 5 nearest control electrode 9n to. This the drain zone 5 nearest control electrode 9n is about the other diode D here approximately at drain potential. The electrical potential of the drift zone 4 With the blocking MOS transistor, it increases linearly in the direction of the drain zone, so that the potentials of the control electrodes 91 , ..., 9n gradually the potential of the drift zone 4 consequences.

The number of control electrodes 91 , ..., 9n and thus the voltage difference between two adjacent control electrodes is particularly tuned to the applied during operation drain-gate voltage that a voltage difference between the respective control electrode 91 , ..., 9n and the drift zone is less than an allowable stress load of the second dielectric. This voltage load decreases with increasing number of control electrodes. The drain-gate voltage corresponds to blocking MOS transistor approximately the applied reverse voltage U _s or drain-source voltage, since the gate-source voltage is negligible compared to the applied reverse voltage, ie usually at a self-locking n-channel MOSFET is zero.

The diodes D1, D2, ..., Dn of the diode chain and the other diode D, the in 3 are shown only in the form of switching symbols, as external components, ie outside the semiconductor body 100 arranged components can be realized, but can in the same semiconductor body 100 as the MOS transistor to be integrated and via a Wiring device level (not shown) with the control electrodes 91 , ..., 9n be electrically connected.

4 illustrates a further drive circuit for generating the drive potentials for the control electrodes 91 , ..., 9n depending on the respective operating state. Shown in 4 is an independent structure for generating these drive potentials. This structure may be realized in a semiconductor body separate from the semiconductor body with the MOS transistor, or may be realized adjacent to the MOS transistor in the same semiconductor body as the MOS transistor, which will be assumed for the following explanation.

The structure of in 4 shown drive circuit comprises in the semiconductor body 100 a semiconductor zone 24 , which is, for example, weakly n-doped and which - analogous to the drift zone 4 - extends along the surface of the semiconductor body in a lateral direction. The semiconductor zone 24 is complementarily doped to one below the semiconductor zone in the example 24 arranged semiconductor layer, which is for example the substrate. In this semiconductor zone 24 is one, with the drain zone 5 electrically connected first connection zone 22 and one with the gate electrode 90 electrically connected second connection zone 23 arranged, for example, are p-doped and which are arranged in the lateral direction of the semiconductor body spaced from each other.

In the semiconductor zone 24 are between the first and second connection zones 22 . 23 each spaced a number of columnar semiconductor zones 251 . 25_2 , ..., 25_n arranged, each complementary to the semiconductor zone 24 are endowed and in particular in regular Ab stand between the two connection zones 22 and 23 are arranged. The columns 25_i , ..., 25 n can be in a perpendicular to the in 4 plane shown extending plane have any cross section, for example, a circular or square cross-section. The individual columnar semiconductor zones 25_1 , ..., 25_n have in each case connections K1, ..., Kn whose function corresponds to the in 3 illustrated taps K1, ..., Kn and corresponds to the control electrodes (in 4 not shown) are connected.

Between the connection zone 22 and the semiconductor zone 24 can be a field stop zone 28 be arranged, which are of the same conductivity type as the semiconductor zone 24 , but is more highly doped. This field stop zone stops when the blocking MOS transistor in the semiconductor zone 24 spreading electric field. The distance between the first and second connection zones 22 . 23 to the semiconductor zone 24 can be the distance of the bodyzone 3 and the drainage zone 5 ie the dimensions of the drift zone 4 in the lateral direction of the semiconductor body 100 correspond.

In the case of a conductively controlled MOS transistor, the semiconductor zone is located 24 via the here in the flow direction poled pn junction between the second connection zone 23 and the semiconductor zone 24 approximately at the gate potential. A pn junction between the semiconductor zone 24 and the first connection zone lying at drain potential 22 is here poled in the reverse direction. The columnar zones 25_1 , ..., 25_n are also at gate potential.

In the case of a blocking-controlled MOS transistor, the drain potential D is, as explained, higher than the gate potential G. In this case, the electrical potential in the drift zone increases from the second connection zone in the direction of the first connection zone. The semiconductor zone 24 is doped so that when blocking MOS transistor, a space charge zone starting from the pn junction between the second terminal zone 23 and the semiconductor zone 24 spreads. The potential of the semiconductor substrate 101 immediately below the semiconductor zone 24 corresponds to the potential of the semiconductor zone 24 , so that the electric potentials of the columns 25_1 , ..., 25_n the electrical potentials of the semi-conductor zone 24 at the position of the respective column. The potential difference between adjacent columns depends on the distance between the columns. At even distances these potential differences, and thus the potential differences between adjacent control electrodes 91 , ..., 9n always the same. Overall, here also results in a step-shaped course of the potentials of the control electrodes 91 , ..., 9n from the gate electrode 90 in the direction of the drain electrode D, which follows the potential course in the drift zone.

5 shows an embodiment of the invention illustrated in which the gate electrode 90 and the control electrodes 91 . 92 . 93 arranged in a ditch extending from the front 101 in the semiconductor body 100 extends and in the lateral direction of the semiconductor body 100 extends in a manner not shown by the body zone to the drain zone. 5A shows a cross section through the trench 7 in the vertical direction of the semiconductor body 100 . 5B shows a plan view of the front 101 of the semiconductor body. Referring to 7B can in this embodiment, multiple trenches 7 with gate electrodes arranged therein 90 and control electrodes 91 . 92 . 93 be provided, which are arranged in a direction perpendicular to the drain-source direction spaced from each other. The provision of a plurality of such trenches with electrodes arranged therein serves to increase the channel cross section of the inversion channel in the body zone 3 and the accumulation channel in the drift zone 4 , and thus to increase the current carrying capacity of the device.

The operation of the device with arranged in trenches gate and control electrodes 90 . 91 , ..., 9n is identical to the operation of the previously discussed embodiments, with the difference that the inversion channel and the accumulation channel are not parallel to the front 101 but perpendicular to the front 101 of the semiconductor body 100 formed.

Also Combinations of the previously explained spatial Positions of the gate electrode and the control electrodes are applicable. For example, the gate electrode above the semiconductor body and the control electrodes can be arranged in a trench, and vice versa.

The 6 and 7 show further embodiments of the arrangement with those adjacent to the drift zone 4 arranged control electrodes. At the in 6 illustrated embodiment, the control electrodes, of which in the figure by way of example, any three 9i-1 . 9i . 9i + 1 are shown. These control electrodes are in this case realized so that two directly adjacent electrodes overlap in sections in the lateral direction. At the in 6 this arrangement is achieved in that every second 9i the control electrodes, the two in the lateral direction immediately adjacent control electrodes 9i-1 . 9i + 1 overlapped at their ends, but is electrically isolated from these electrodes. The control electrode 9i is this step-shaped at their ends. In a manner not shown, there is also the possibility that each of the control electrodes is a stepped End, with which it overlaps a respective immediately adjacent control electrode. Due to this overlapping realization of the control electrodes 9i-1 . 9i . 9i + 1 can be achieved that forms the accumulation channel with conducting MOS transistor gapless over the entire length of the control electrode assembly, so that no interruption of the accumulation channel occurs.

In the 6 The arrangement shown can be produced by first producing only every other one of the control electrodes, and finally by making the remaining control electrodes overlap the previously produced ones. Before producing the further control electrodes, an insulating layer is applied at least to the later overlapped ends of the control electrodes first produced.

At the in 7 illustrated embodiment are in the drift zone 4 each adjacent to gaps between two control electrodes each heavily doped semiconductor zones 8th are arranged, each of the same conductivity type as the channel in the drift zone 4 which is controlled by the control electrodes. For an n-type device these zones are 8th n-doped, in a p-type device these zones 8th p-doped, in each case independently of the doping of the drift zone 4 , These highly doped zones prevent "tearing" of the conductive channel, which depends on the doping of the drift zone 4 an accumulation channel or an inversion channel.

The basis of the 6 and 7 explained measures to prevent tearing of the conductive channel along the second dielectric in the case of conductively driven component, namely an overlapping arrangement of the control electrodes 9i-1 . 9i . 9i + 1 or the provision of highly doped semiconductor zones 8th in the drift zone 4 adjacent to gaps of the control electrodes 9i-1 . 9i . 9i + 1 Of course, the basis of 5 explained elements are taken in which the control electrodes are arranged in trenches.

Claims (17)

A semiconductor device arrangement comprising: a semiconductor body ( 1 ), a MOS transistor with one in the semiconductor body ( 100 ) arranged source zone ( 2 ) of a first conductivity type, one to the source zone ( 2 ) adjacent Bodyzone ( 3 ) of a second conductivity type, one in the semiconductor body ( 100 ) arranged Drainzone ( 5 ), one between the drain zone ( 5 ) and the Bodyzone ( 3 ) arranged drift zone ( 4 ) and with a gate electrode ( 90 ), which are adjacent to the body zone ( 3 ) and from this by a first dielectric ( 61 ) is separated, at least two control electrodes ( 91 . 92 , ..., 9n ) adjacent to the drift zone ( 4 ) and from this by a second dielectric ( 62 ) and a drive circuit ( 10 ) connected to the gate electrode ( 90 ), the control electrodes ( 91 . 92 , ..., 9n ) and the drain zone ( 5 ) and which is adapted, in a first operating state, in which the MOS transistor conducts, the at least two control electrodes ( 91 . 92 , ..., 9n ) such that a conductive channel extends along the second dielectric in the drift zone (FIG. 4 ), and in a second operating state, in which the MOS transistor blocks, the control electrodes ( 91 . 92 , ..., 9n ) in such a way that potentials of the control electrodes ( 91 . 92 , ..., 9n ) stepwise the potential course in the drift zone ( 4 ) consequences. Semiconductor device arrangement according to Claim 1, in which the drive circuit ( 10 ) has a series circuit with rectifier elements (D1, ..., Dn), a first and second (Kn) connection and intermediate taps (K1, ..., Kn-1) between each two rectifier elements (D1, ..., Dn) , wherein the first connection to the gate electrode ( 90 ) and in each case one of the intermediate taps (K1, ..., Kn-1) to one of the control electrodes ( 91 , ..., 9n-1 ) is coupled. Semiconductor component arrangement according to Claim 2, in which one of the drain zones ( 5 ) nearest control electrode ( 9n ) is connected to the second terminal (Kn) of the series circuit. Semiconductor component arrangement according to Claim 2 or 3, in which the second connection (Kn) of the series connection via a further rectifier element (D) to the drain zone (FIG. 5 ) is coupled. Semiconductor device arrangement according to claim 4, wherein the opposite rectifier element (D) opposite to the Rectifier elements (D1, ..., Dn) of the series circuit poled is. Semiconductor component arrangement according to one of claims 2 to 5, in which the rectifier elements (D1, D2, ..., Dn) of the series circuit Diodes are. Semiconductor component arrangement according to one of Claims 3 to 6, in which the further rectifier element (D) is a diode. Semiconductor component arrangement according to one of the preceding claims, in which the semiconductor body ( 100 ) a first semiconductor layer ( 101 ) and a complementary to the first semiconductor layer ( 101 ) doped second semiconductor layer ( 102 ), the drift zone ( 4 ) in the second semiconductor layer ( 101 ) is trained. Semiconductor device arrangement according to Claim 8, in which the second semiconductor layer ( 102 ) to the source zone ( 2 ) is coupled. Semiconductor device arrangement according to Claim 1, in which the drive circuit ( 10 ): - a first semiconductor zone ( 24 ) of a conductivity type in the semiconductor body ( 100 ) which extends along a surface of the semiconductor body in the lateral direction and which has a complementary doped and with the drain zone ( 5 ) electrically connected first terminal zone ( 22 ) and spaced from the first terminal zone (FIG. 22 ) a complementarily doped and electrically connected to the gate electrode second terminal zone ( 23 ), - in the first semiconductor zone ( 24 ) spaced laterally spaced apart columnar second semiconductor zones ( 25_1 , ..., 25_n ), which are complementary to the first semiconductor zone ( 24 ) are doped and which, starting from the surface in a vertical direction in the semiconductor body ( 100 ), wherein in each case one of the second semiconductor zones ( 25_i , ...) to one of the control electrodes ( 91 , ...) connected. Semiconductor device arrangement according to Claim 10, in which the doping concentration and the dimensions of the columnar second semiconductor zones ( 25_1 , ...) is chosen so that they are eliminated when the blocking MOS transistor. Semiconductor device arrangement according to Claim 10 or 11, in which the first semiconductor zone ( 24 ) above a complementary to the first semiconductor zone ( 24 ) doped semiconductor layer ( 101 ) and in which the columnar second semiconductor zones ( 25_1 , ...) to this semiconductor layer ( 101 ) pass. Semiconductor device arrangement according to one of the preceding claims, in which the gate electrode ( 90 ) and / or the control electrodes ( 91 , ...) above one side of the semiconductor body ( 100 ) are arranged. Semiconductor device arrangement according to one of the preceding claims, in which the gate electrode ( 90 ) and / or the control electrodes ( 91 , ...) in a trench of the semiconductor body ( 100 ) are arranged. Semiconductor device arrangement according to one of the preceding claims, in which the control electrodes ( 91 , ...) are partially overlapping each other. Semiconductor device arrangement according to one of the preceding claims, in which the control electrodes ( 91 , ...) in the drift zone ( 4 ) adjacent to gaps between two immediately adjacent control electrodes one higher than the drift zone ( 4 ) doped semiconductor zones ( 8th ) are arranged. A semiconductor device arrangement according to claim 16, wherein the higher doped zones are of the same conductivity type as the source zone (16). 2 ) are.