DE102006054086A1 - Multilayer capacitor - Google Patents

Abstract

The invention relates to a multilayer capacitor with a body (10) and first and second internal electrodes (14, 15) arranged in the body. The first internal electrodes (14) are conductively connected to one another by means of a first SMD contact (11) arranged on the underside of the body. The second internal electrodes (15) are conductively connected to one another by means of a second SMD contact (12) arranged on the underside of the body.

Description

A multilayer capacitor is from the publication JP 2004 228544 A known.

A to be solved Task is another suitable surface mount multi-layer capacitor specify.

It is a multilayer capacitor with a body and arranged in the body indicated first and second internal electrodes. The first internal electrodes are by means of a arranged on the bottom of the body first SMD contact conductively connected. The second internal electrodes are by means of a second arranged on the underside of the body SMD contact conductively connected. SMD stands for Surface Mounted Device.

Of the The advantage of the capacitor is that the SMD contacts on the one hand as external contacts and on the other hand for the electrical connection of internal electrodes serve, so that can be dispensed with a via in the body.

in the Below, advantageous embodiments of the capacitor will be described.

Of the Multilayer capacitor is preferably as one for surface mounting suitable chip capacity educated.

each Inner electrode is arranged in an electrode plane. Every electrode level is disposed between two dielectric layers of the body. The dielectric Layers preferably contain ceramics.

The Internal electrodes form an electrode stack in which first and second internal electrodes are alternately arranged. The internal electrodes stand perpendicular to the SMD contacts.

The electrical contacting of both first and second Internal electrodes take place on one and the same surface, namely the underside of the body.

Of the body has side surfaces each having a plan area. In an advantageous Variant, at least the flat areas of the side surfaces are free of electrical contacts. This means that the SMD contacts essentially exclusively on the bottom of the body are arranged.

Of the body has in one embodiment the Shape of a cuboid, which preferably has a preferred direction. In one variant, the internal electrodes are parallel and the SMD contacts are vertical aligned to the preferred direction. In another variant are the internal electrodes vertical and the SMD contacts parallel to the Aligned preferred direction.

Of the Cuboid may have rounded edges, with the respective SMD contact extends to at least one of the rounded edges.

In an advantageous variant is between two SMD contacts Formed gap where the ratio the length to the width is at least the factor of three. This variant draws characterized by a particularly low input Indukti tivity of what for high frequency applications is beneficial. It is to achieve a low inductance particularly advantageous when a bridge-type electrical connection, the respective inner electrode with the corresponding external contact conductive, essentially as wide as it is formed this external contact.

Of the Multilayer capacitor will now be based on schematic and not true-to-scale figures explained. Show it:

1A a multilayer capacitor in a longitudinal section;

1B the multilayer capacitor according to the 1A in a cross section along the line AA;

1C a plan view of the bottom of the multilayer capacitor according to the 1A . 1B ;

2A another multilayer capacitor in a longitudinal section;

2 B . 2C in each case the multilayer capacitor according to the 2A in a first and second cross section;

2D a plan view of the bottom of the multilayer capacitor according to the 2A - 2C ,

The in 1A . 1B featured multilayer capacitor comprises a body 10 , on the underside of which a first and second external electrical contact 11 . 12 is arranged. In the body 10 is a stack of first internal electrodes 14 arranged, each with the first external contact 11 are conductively connected. In the body 10 is a stack of second internal electrodes 15 arranged, each with the second external contact 12 are conductively connected. First and second internal electrodes alternate.

Each inner electrode lies in its own electrode plane, which is perpendicular to the bottom of the body 10 is arranged. Every first inner electrode 14 has an overlap region that is in a projection plane with an overlap region of the second inner electrode 15 overlaps. Every first inner electrode 14 also has a connection area 14a on, the overlap area of this inner electrode with the first SMD contact 11 combines. Every second inner electrode 15 analogously has a connection area 15a on, the overlap region of this inner electrode with the second SMD contact 12 combines. The first internal electrodes 14 are from the second SMD contact 12 and the second internal electrodes 15 from the first SMD contact 11 spaced.

Between the SMD contacts 11 . 12 is a narrow gap 18 formed having a width b and a length L, for which applies: L / b ≥ 3.

The edges of the body 10 are rounded off, for example, by scrubbing. The SMD contacts 11 . 12 cover a rounded area of the respective end face 16 . 17 of the body 10 , The planned areas 19 However, the side surfaces, including faces, are free of SMD contacts. This also applies to the top of the body.

On the rounding of edges can be dispensed with in principle.

In the in 1A . 1B presented variant extend the internal electrodes 14 . 15 in the preferred direction of the body 10 ,

In contrast, in the variant according to the 2A . 2 B . 2C the internal electrodes 14 . 15 perpendicular to the preferred direction of the body 10 aligned. The SMD contacts 11 . 12 extend in the preferred direction of the body 10 ,

The design options regarding the Number and shape of internal electrodes, electrode stacks, SMD contacts are not limited to the figures shown. The choice of materials is also not limited.

10

body

11

first SMD contact

12

second SMD contact

14

first internal electrodes

14a

connecting area

15

second internal electrodes

15a

connecting area

16 17

faces

18

gap

19

planner Area of the side surface

Claims (9)

Multilayer capacitor - with one body ( 10 ) and arranged in the body first and second internal electrodes ( 14 . 15 ), - wherein first internal electrodes ( 14 ) by means of a arranged on the bottom of the body first SMD contact ( 11 ) are conductively connected to each other, - wherein second internal electrodes ( 15 ) by means of a arranged on the underside of the body second SMD contact ( 12 ) are conductively connected to each other. Multilayer capacitor according to claim 1, - wherein the internal electrodes ( 14 . 15 ) are perpendicular to the SMD contacts. Multilayer capacitor according to Claim 1 or 2, - the body ( 10 ) Has side surfaces each having a plan area ( 19 ), wherein at least the planar regions of the side surfaces are free of electrical contacts. Multilayer capacitor according to one of Claims 1 to 3, - the body ( 10 ) has the shape of a cuboid with rounded edges, - wherein the respective SMD contact ( 11 . 12 ) extends to at least one of the rounded edges. Multilayer capacitor according to one of Claims 1 to 4, - the body ( 10 ) has a preferred direction, - wherein the internal electrodes ( 14 . 15 ) are aligned parallel to the preferred direction. Multilayer capacitor according to one of Claims 1 to 4, - the body ( 10 ) has a preferred direction, - wherein the internal electrodes ( 14 . 15 ) are aligned perpendicular to the preferred direction. Multilayer capacitor according to one of claims 1 to 6, wherein between two SMD contacts ( 11 . 12 ) A gap ( 18 ) is formed, wherein the ratio of the length (L) to the width (b) is at least the factor three. Multilayer capacitor according to one of Claims 1 to 7, - the body ( 10 ) Contains ceramic. Multilayer capacitor according to one of Claims 1 to 8, - in which first and second internal electrodes ( 14 . 15 ) are arranged alternately.