DE102006048392A1 - Method for producing a semiconductor memory component and semiconductor memory component - Google Patents

Abstract

A layer of electrically conductive material is deposited over an upper surface of a substrate and patterned into gate electrodes (12) in a first region provided as drive periphery. An implantation of a dopant provided for source / drain regions (17) is performed in the first region. After healing of the implants, the upper surface is planarized with an auxiliary layer (18) of dielectric material. The first region is covered with a mask, the electrically conductive layer is patterned in a second region provided for memory cells, and a further implantation of a dopant provided for source / drain regions is introduced. After healing of the implants, the memory cells in the second region are completed. A selectively deposited, electrically conductive material may be provided on the gate electrodes of the drive peripheral device.

Description

The The present invention relates to semiconductor memory devices, in particular Multi-bit charge trapping memory devices that use a memory cell array and an addressing peripheral, as well as manufacturing methods for this Memory products.

In the DE 101 10 150 a memory device with charge trapping layers is described, which can be produced together with transistors of an addressing periphery. The manufacturing method described is used for a virtual ground NOR arrangement. A conventional module for shallow trench isolation is used. Trays are implanted and the charge trapping layers are grown. In addition, different gate oxides can be formed for different transistor types. First layers of the gate stacks are deposited and patterned to provide buried bit line openings in the area provided for the memory cell array. Buried bitlines and source / drain regions of the memory cell transistors are implanted through the openings and the implants are subsequently annealed. The openings are filled and the surface is planarized. Second gate layers are deposited and patterned to form gates in the region of the memory cell array and the periphery. Junctions of the CMOS transistors are formed in the periphery by further implantations. Implants are healed and standard backend process steps follow.

The Source / drain regions of the memory cell transistors are present the implantation of the source / drain regions of the peripheral transistors implanted. Therefore, the implantation in the periphery must be cured, if the dopant atoms in the memory cell array already present and due to the comparatively high thermal budget the annealing step of increased diffusion are subject. In this way, it is not possible to have sufficiently small, preferably, minimum thermal budgets for the memory cell transistors to realize, which are those components, which are reduced to the smallest structural dimensions. A further miniaturization and scalability can not be achieved without the thermal budget to the requirements to match the memory cell transistors. But there is a bottom one Limit of the thermal budget due to the requirements of the peripheral Transistors.

task The present invention is an improved possibility to integrate largely miniaturized memory cell transistors with Specify transistors of a drive periphery. It should in particular the diffusion of the dopant atoms in the memory cell array be kept within the required limits.

These Task is with the method with the features of the claim 1 or with the semiconductor memory device having the features of claim 10 solved. Embodiments emerge from the respective dependent claims.

at the manufacturing method of a semiconductor memory device is a layer of electrically conductive material over one Substrate top applied. Gate electrodes are on the layer electrically conductive Material over formed a first region of the substrate top. An implantation a dopant which is suitable for Source / drain regions is provided is carried out in the first area, and the implantation is healed. An auxiliary layer of dielectric Material is applied and the surface is planarized. The first Area is covered with a mask and another implantation one for Source / drain regions provided dopant in a second region of the substrate top executed. The implantation is annealed, and an array of memory cells is formed in the second region of the substrate top.

at The semiconductor memory device is a first area for a drive periphery and a second area for a memory cell arrangement is provided. Located in the first area Gate electrodes connected to a selectively deposited, electrically conductive Material are provided. additionally can buried bitlines may be present in the second region, the also with selectively deposited, electrically conductive material are provided. This material may be a salicide (self-aligned Silicides), in particular CoSi.

It follows a more detailed description of examples of the method and of the component with reference to the accompanying figures.

The 1 shows a cross section of an intermediate product of an embodiment after the application of a storage layer.

The 2 shows a cross section according to the 1 after applying a layer of electrically conductive material and a hardmask layer.

The 3 shows the arrangement of the first hard mask and the active area in the Ansteu erperipherie.

The 4 shows a detail of a plan view of the memory cell array.

The 5 shows a cross section according to the 2 after applying a first auxiliary layer, with which the surface is planarized.

The 6 shows a cross section according to the 5 another embodiment.

The 7 shows a cross section according to the 5 or 6 after making openings in the layer of electrically conductive material in the region of the memory cells.

The 8th shows a plan view of the area of the storage cells for the intermediate of 7 ,

The 9 shows a cross section according to the 7 after applying a second auxiliary layer.

The 10 shows a cross section according to the 9 another embodiment with thin Seitenwandspacern.

The 11 shows a cross section according to the 9 or 10 after applying a word line layer sequence.

The 12 shows a cross section perpendicular to the cross section of 11 after the formation of the word line stacks.

The 13 shows a plan view of the arrangement of the word line stack.

The 14 shows a cross section according to the 11 after application of an intermetal dielectric.

The 15 shows a cross section according to the 11 a further embodiment.

The 16 shows a cross section according to the 15 after application of an intermetal dielectric.

The 17 shows a cross section according to the 10 a further embodiment.

The 1 shows a cross section of a substrate 1 , which may be a semiconductor body or semiconductor substrate, according to the first method steps of a first embodiment. The substrate top 2 is for a first area 3 provided in which the peripheral components are to be arranged, and for a second area 4 in which the memory cell array is to be manufactured. A first dielectric 5 that is provided for the gate dielectric of transistors becomes on the substrate top 2 in the first area 3 educated. A second dielectric 6 will be in the second area 4 educated. Additional dielectric layers intended for different transistor types may additionally be provided, for example the third dielectric 7 that in the 1 in the first area 3 is shown.

The active transistor areas are through isolation areas 8th isolated, the z. B. field insulation or shallow trench isolation can be. The isolation areas 8th can be prepared in a conventional manner by applying a nitride hard mask, reactive ion etching of the substrate material, optional application of a liner, application of an oxide filling and planarization by CMP (chemical mechanical polishing). The gate dielectrics are preferably after forming the isolation regions 8th produced. Suitable tubs 9 be z. By implantation in a manner known per se from standard CMOS processes.

Over the second area 4 can be a storage layer 10 or memory layer sequence for the memory cell transistors, in particular a memory layer made of a dielectric material which is suitable for charge trapping. The 1 shows the cross section of the intermediate product up to here.

The 2 shows another intermediate in a cross section according to the 1 , A layer of electrically conductive material 11 is deposited, which may be, for example, electrically conductive doped polysilicon, which is provided for the gate electrodes. A hard mask layer 13 , which can be nitride, is applied to the layer of electrically conductive material 11 applied. The hard mask layer 13 becomes the formation of a first hardmask 14 over the first area 3 the substrate top 2 structured. The first hard mask 14 is patterned according to the gate structures provided for the peripheral devices. While structuring the hard mask is the second area 4 covered, for example, with a photoresist layer. The structuring of the hardmask layer 13 can be achieved in a conventional manner by a standard lithography step. The structure of the first hard mask 14 gets into the layer of electrically conductive material 11 etched to the gate electrodes 12 train.

The 3 shows a plan view of the first hard mask 14 over the active area 15 which is provided for one of the peripheral transistors, which is shown here as an example.

The 4 shows a plan view of the second area 4 the substrate top 2 with the continuous hard mask layer 13 , which in this example is the storage layer 10 not completely covered.

The 5 shows a cross section according to the 2 after the application of sidewall spacers 16 and the implantation of source / drain regions 17 , In this way, source / drain junctions of various CMOS devices can be fabricated using conventional implantation and annealing steps employing suitable liner / spacer combinations. The 5 shows only a typical example. Then the first auxiliary layer 18 applied on the first area and the top planarized. The planarization can be done with CMP, which is approximately on the top of the first hardmask 14 stops.

The 6 shows a cross section according to the 5 for another embodiment in which the sidewall spacers 16 before applying the first auxiliary layer 18 have been removed.

The cross sections of the 5 and 6 show an essential feature of this method. The formation of the source / drain junctions of the peripheral transistors and the memory cell transistors in a reverse order to that of the prior art is achieved by planarizing the top of the device after forming the gate stacks in the periphery and implanting the source / drain ranges 17 in the first area 3 allows.

The 7 shows a cross section according to the 6 after structuring the layer of electrically conductive material 11 over the second area 4 , This can be achieved with a conventional lithography step, with which the hard mask layer 13 in the second hardmask 19 is structured. The second hard mask 19 and the layer of electrically conductive material 11 For example, they can be patterned by reactive ion etching. The storage layer 10 can be maintained in the openings, or it can be more or less removed. Then, preferably, a halo implant is introduced, which is for the buried bit lines 20 is provided.

The 8th shows a plan view of the second area 4 indicating the relative positions of the strip-like portions of the second hardmask 19 and the areas of the buried bit lines 20 shows.

The 9 shows a cross section according to the 7 after the complete implantation of the buried bitlines 20 comprising the source / drain regions of the individual memory cell transistors. A typical implantation suitable here uses arsenic as a dopant, which is introduced at a dose of more than 10 ¹⁵ / cm ² . The annealing is done at typically 1000 ° C to 1050 ° C for a maximum of five seconds. The openings are then filled with the second auxiliary layer 21 made of dielectric material. The top is planarized again. That can happen through CMP, what's on the hard masks 14 . 19 stops.

The 10 shows another embodiment, with thin spacers 22 on the side walls of the strip-like remaining portions of the layer of electrically conductive material 11 and, optionally, on the sidewalls of the second hardmask 19 is provided. These spacers 22 are preferably prior to the final implantation of the buried bitlines 20 educated. The second hard mask 19 will then be out of the second area 4 away. The first hard mask 14 is still on the first area 3 , She is covered with a suitable mask when the second hard mask 19 Will get removed.

The 11 shows a cross section according to the 9 after applying a word line layer sequence 23 , The word line layer sequence 23 may be a word line polysilicon layer 24 include the remaining portions of the layer of electrically conductive material 11 which are provided as gate electrodes of the memory cell transistors, and a word line metal layer 25 that z. Tungsten or tungsten silicide, and a word line hard mask layer 26 that z. B. may be nitride.

The 12 shows a cross section perpendicular to the cross section of 11 after the structuring of the word line layer sequence 23 and the layer of electrically conductive material 11 in word line stack 27 , This is preferably done with a conventional lithography step and a subsequent RIE (reactive ion etching) performed on the storage layer 10 stops, accomplishes. A canal limitation implant 28 is inserted between the gates to isolate the individual memory cells from each other.

The 13 shows a plan view of the second area 4 in which the arrangement of word line stacks 27 is recognizable.

The 14 shows a cross section according to the 11 after application of an intermetal dielectric 29 filling the spaces between the word line stacks. The intermetallic dielectric 29 can be oxide or other material with a low relative dielectric be number. The top is again planarized, z. By CMP. Subsequent process steps may include applying one or more types of contacts to the substrate, the word lines, and the gate polysilicon of the CMOS devices. The latter contacts are unique in this fabrication process because the gate electrodes of the peripheral transistors have been fabricated prior to the memory cell array. In addition, several metallization levels including intermetal dielectrics and vias as well as passivations are applied. This can be done according to conventional manufacturing processes.

The 15 shows a cross section according to the 11 a further embodiment. In this embodiment, the first hardmask becomes 14 together with the second hard mask 19 removed before the word line layer sequence 23 is brought up. The word line layer sequence 23 is in this case as a contact and electrical connection to the gate electrode 12 of the peripheral transistor and forms a gate electrode stack 30 , Like in the 15 is shown, the word line layer sequence 23 , which in this example is a word line polysilicon layer 24 , a word line metal layer 25 and a word line hard mask layer 26 includes, an overhang structure 31 over the edges of the gate electrode 12 , This means that the word line layer sequence is the gate electrode 12 projected laterally, so that edge-side sections of the word line layer sequence on the laterally adjacent first auxiliary layer 18 are arranged.

The 16 shows a cross section according to the 15 after application of the intermetal dielectric 29 in a similar way as already in connection with 14 described.

The 17 shows a cross section according to the 10 a further embodiment. In this embodiment, the first hardmask becomes 14 after the implantation of the buried bit lines and optionally after the application of thin spacers 22 from the gate electrodes 12 removed in the periphery. This can again be done by means of a lithography step. An electrically conductive material 32 is selective to the gate electrode 12 and the buried bit lines deposited. This material can be a metal such. Cobalt, with which a self-aligned silicidation is formed, which in the example is cobalt CoSi. The second auxiliary layer 21 will then also on the gate electrode 12 applied to the electrically conductive material 32 to cover. The contact of the gate electrode 12 In this example, it is of the same type as the contact on the electrically conductive material of the buried bit lines.

The described methods are particularly advantageously applicable to multi-bit charge trapping memory devices, in particular to a class of memory devices in which the current through the cells is directed parallel to the word lines. The disclosed integration concept improves scalability by minimizing the junction diffusion of the memory cell transistors. Although the properties of a virtual ground array require process steps that are different for the cell transistors and the addressing CMOS devices, and the annealing steps differ accordingly, this does not cause any disadvantages as the memory cell junctions are annealed in the latest possible stage of the fabrication process. In this way, the thermal budget to which the memory cell transistors are exposed can be minimized. This is made possible by an activation of the cell junctions after the main processing of the peripheral components. The lateral diffusion of the n ⁺ -unctions of the cell transistors can thus be limited to a distance of less than 10 nm. Variations and embodiments of the examples described are within the scope of the invention.

1

substratum

2

top of the substrate

3

first Area

4

second Area

5

first dielectric

6

second dielectric

7

third dielectric

8th

Quarantine

9

tub

10

storage layer

11

layer made of electrically conductive material

12

Gate electrode

13

Hard mask layer

14

first hard mask

15

active Area

16

sidewall

17

Source / drain region

18

first auxiliary layer

19

second hard mask

20

buried bit

21

second auxiliary layer

22

thin spacer

23

Wordline layer sequence

24

Wordline polysilicon layer

25

Word line metal layer

26

word line hard mask layer

27

Wordline stack

28

Channel stop implant

29

intermetal

30

Gate electrode stack

31

Overhang structure

32

electrical conductive material

Claims (13)

Method for producing a semiconductor memory component, in which a layer of electrically conductive material ( 11 ) on a top side ( 2 ) of a substrate ( 1 ), gate electrodes ( 12 ) over a first area ( 3 ) of the top side ( 2 ) from the layer of electrically conductive material ( 11 ), an implantation of a dopant suitable for source / drain regions ( 17 ) in the first area ( 3 ) is introduced, the implants are healed, an auxiliary layer ( 18 ) is applied from dielectric material, the upper surface is planarized, the first area ( 3 ) is covered with a mask, a further implantation of a dopant for source / drain regions ( 20 ) in a second area ( 4 ) of the top side ( 2 ), the implants are annealed and an array of memory cells in the second region ( 4 ) will be produced. Method according to Claim 1, in which, after the application of the layer of electrically conductive material ( 11 ) a hardmask layer ( 13 ) and to a first hard mask ( 14 ) and the first hardmask ( 14 ) for structuring the layer of electrically conductive material ( 11 ) in the gate electrodes ( 12 ) is used. Method according to Claim 2, in which the hard mask layer ( 13 ) into a second hard mask ( 19 ) over the second area ( 4 ), the second hardmask ( 19 ) for structuring the layer of electrically conductive material ( 11 ) over the second area ( 4 ) and the further implantation in openings of the layer of electrically conductive material ( 11 ) in the second area ( 4 ) is introduced and so buried bit lines are formed. Method according to Claim 3, in which a further auxiliary layer ( 21 ) of dielectric material into the openings of the structured layer of electrically conductive material ( 11 ), the upper surface is planarized, the second hard mask ( 19 ) and a word line layer sequence ( 23 ) and to word line stacks ( 27 ) is structured. Method according to Claim 4, in which the word line layer sequence ( 23 ) in the first area ( 3 ) in gate electrode stacks ( 30 ) and in the second area ( 4 ) in word line stacks ( 27 ) is structured. Method according to Claim 3, in which, after the further implantation, the first hard mask ( 14 ) from the first area ( 3 ), an electrically conductive material ( 32 ) selectively on the gate electrodes ( 12 ) in the first area ( 3 ) and on the implanted areas ( 20 ) in the second area ( 4 ) is deposited, another auxiliary layer ( 21 ) is applied from dielectric material, the upper surface is planarized, the second hard mask ( 19 ) from the second area ( 4 ), a word line layer sequence ( 23 ) is applied and the word line layer sequence ( 23 ) in word line stacks ( 27 ) is structured. Method according to Claim 6, in which the electrically conductive material ( 32 ) is selectively deposited such that salicidation is formed. The method of claim 7, wherein the electrically conductive Material is cobalt and CoSi is formed. Method according to one of claims 1 to 8, wherein prior to the application of the layer of electrically conductive material ( 11 ) a material suitable for charge trapping over the second area ( 4 ) as a storage layer ( 10 ) is applied. Semiconductor memory device in which a first region ( 3 ) is provided for a drive periphery and a second area ( 4 ) is provided for a memory cell arrangement, gate electrodes ( 12 ) over the first area ( 3 ) and the gate electrodes ( 12 ) a selectively deposited electrically conductive material ( 32 ) exhibit. A semiconductor memory device according to claim 10, wherein the buried bit lines ( 20 ) in the second area ( 4 ) and the buried bit lines ( 20 ) a selectively deposited, electrically conductive material ( 32 ) exhibit. A semiconductor memory device according to claim 10 or 11, wherein the selectively deposited electrically conductive material ( 32 ) forms a salicide. A semiconductor memory device according to claim 10 or 11, wherein the selectively deposited electrically conductive material ( 32 ) CoSi forms.