DE102006032951B4 - Semiconductor memory with a block-reserved programmable latency register - Google Patents

Abstract

A semiconductor memory device, comprising: at least one memory bank (100; 200) having a plurality of memory blocks (100a, 100b; 200a, 200b, 200c, 200d) for storing data, the data in the memory blocks (100a, 100b; 200a, 200b, 200c, 200d) stored data can be read in response to a read command; a control unit (106; 206) for generating a plurality of CAS latency values and for assigning the CAS latency values to predetermined blocks of the memory blocks (100a, 100b; 200a, 200b, 200c, 200d) to be read; and an output circuit (105; 205) for outputting the data in response to a read signal activated by a read command, the output circuit (105; 205) receiving the data from each of the memory blocks (100a, 100b; 200a, 200b, 200c, 200d) based on the assigned CL values, the control unit (106; 206) comprising: a CAS latency register (106b; 206b) containing a plurality of sets of mode registers, each of the sets of mode registers therefor designed to generate a variety of the CAS latency values; and a CAS latency mux unit (106a; 206a) for selecting one of the plurality of CAS latency values from each set of the mode registers in accordance with a column address included in the read command and for converting the selected CAS latency values To assign values to predetermined blocks of the memory blocks (100a, 100b; 200a, 200b, 200c, 200d) based on predetermined conditions of the memory blocks (100a, 100b; 200a, 200b, 200c, 200d), and wherein the predetermined conditions of the memory blocks (100a, 100b; 200a, 200b, 200c, 200d) comprise a location of the memory blocks (100a, 100b; 200a, 200b, 200c, 200d) in relation to the output circuit (105; 205) in which the data is output.

Description

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates to semiconductor memory devices, and more particularly to synchronous memory devices having a block-reserved programmable latency register.

2. Description of the Related Art

From the publication US 6,031,787 A For example, a variable latency memory device for read and write operations is known.

From the publication DE 102 08 716 A1 For example, a control circuit for an SDRAM is known, wherein the control circuit has a programmable mode register for storing a latency time value and a latency generator for delaying a data path control signal generated by an internal sequence control with a switchable latency. A latency decoder in the control circuit switches the latency generator in response to the latency value stored in the mode register.

From the publication US 2002/0014635 A1 For example, a mode selection circuit for a semiconductor memory device is known in which a command decoder outputs a pMRS signal in the mode selection circuit and a latency control unit receives the pMRS signal.

1 FIG. 12 is a timing chart illustrating a read operation of a semiconductor memory device (SDRAM). FIG. In 1 CLK denotes a clock signal, COMMAND in this example denotes a read command, ADDRESS denotes a signal which provides instructions for accessing a column address, and DATA OUTPUT illustrates the output of the memory device at any particular time. The latency refers to a time between the start and the completion of an event. For synchronous DRAMs, latency is usually counted by a number of clocks needed for a particular event. As in 1 As shown, CAS (column address strobe) latency refers to the time between the start and completion of a read operation in a column address of a memory space within an SDRAM, or the latency from the number of clock signals from the READ command (along with the column address command ) until the first data output. In other words, the CAS latency records a parameter used by the SDRAM to synchronize the output data obtained as a result of a READ request (command) on a particular edge of the system clock (CLK). The "burst length" denotes the number of consecutive output data as a result of a READ command (in 1 is the burst length = 4). If, as in 1 1, the consecutive number of clocks before the start of data output = CAS latency, in this example, CAS latency = 3.

2 illustrates an internal speed parameter of a DRAM data path or a number of required operations for the data access time of a DRAM from the moment a column ADDRESS command is input. As in 2 is illustrated, t _{AA is} the internal velocity parameter of a DRAM data path that fundamentally limits the number of CL required to obtain a proper data output as a result of the READ command (the data access time by the number of clocks). Therefore, CL can not exceed the value of t _AA (t _AA <CL × t _CK ). For example, if t _CK and t _AA = 5 ns (200 MHz) and 15 ns, respectively, the minimum value of CL = 4. At a t _AA of 15 ns and a t _CK of 2.5 ns (400 MHz) the minimum CL = 7. Since the column address request occurs on the column select line (CSL), the value of t _AA depends on the distance from CSL to the D _out driver.

The CL value is generally programmed using a Mode Register Set (MRS) command. A mode register is used to define the specific mode of operation of an SDRAM. In other words, the mode register stores the data for controlling the various operation modes of DDR SDRAM. 3 illustrates a mode register and a mode register set (MRS). The mode register programs the CAS latency, addressing mode, burst length, test mode, DLL reset, and various vendor-specific options to make the DDR SDRAM usable for a variety of different applications. The default value of the mode register is undefined, and therefore the mode register must be written after an external mode register set (EMRS) setting for proper DDR SDRAM operation.

The mode register is described by referring to CS, RAS. CAS. Assigns WE and BA0 low (the DDR SDRAM should be pre-charged in all banks, with CKE high before writing to the mode register). The states of the address pins A0-A11 (A12) in the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles are requested to complete the write operation to the mode register. The mode register contents may be changed using the same instruction and clock cycle requests during the operation, as long as all the banks are idle. The mode register is divided into various fields, depending on the functionality. The burst length uses A0-A2, and the addressing mode uses A3, CAS latency (read latency from the column address) uses A4-A6. A7 is used for the test mode and A8 for the DLL reset. A7 must be set low for normal MRS operation. The CAS latency table illustrates specific codes for various burst lengths, addressing modes, and CAS latencies.

As described above and also in 3 It is apparent that CL is generally programmed using an MRS instruction. 4 Figure 4 illustrates how the MRS instruction is used to set a CL value of 2, for example, when A4 is set to a logical 0, A5 is set to a logical 1, and A6 is set to a logical 0 is (see the table in 3 ). As a result, CL (CAS Latency) is programmed to have a value of 2 through the mode register.

5A FIG. 12 illustrates a memory device of a conventional SDRAM device and also how it is divided into banks, that is, a bank A, a bank B, a bank C, and a bank D. Here again, each of the banks is divided into a plurality of memory blocks (FIG. ie block 0 to block n, as in 5B is illustrated. In addition, each of the memory blocks may include a plurality of memory cells. Each of the blocks within the bank can be accessed by row and column addresses supplied as logical codes. For example, illustrated 6A a bank of a memory device, which is divided into many memory blocks. The memory blocks in the bank, which in 6A can be selected to access a read operation of data stored therein by activating a portion of the row addresses and the column addresses using binary logic, as shown in FIGS 6B and 6C is illustrated.

In view of the above-described operations of an SDRAM, a conventional synchronous memory device and the operations thereof will be explained below.

Conventional synchronous storage devices may only have a CAS latency value (CL) programmed using an MRS instruction, as described above. In other words, a first record of the burst read data is designated for the output in the same number of clocks when the READ command is input regardless of the spatial distance of the designated memory block (or cell) from a data output circuit or circuit block. contains the data output buffer which receives the data to be read. The data to be read is generally selected for reading, by an appropriate column and row address, which is addressed by ADDRESS with the read command (see 1 ) is delivered. The burst data is output to the data output circuit block containing the data output buffer stages. However, the data path to the data output circuit block may be expected to have a shorter access time from the cells in a near-side block (ie, the nearest block to the output circuit block) than a laterally-remote block (ie, the block farthest from the output circuit block ). 7 illustrates a memory bank having a plurality of blocks (blocks 0-n) and how the blocks are decoded with respect to a row decoder and column decoder. As in 7 1, block_0 is a near-end block with respect to the output circuits and pads (ie, in the output circuit block), while block_n is a remote page block with respect to the output circuits and pads. The difference in this distance can be represented by the following equation: .DELTA.t = t _{AA AA far} - t _{AA near} wherein _AA means the difference .DELTA.t of t _AA (data access time) between the near-side and far-side memory blocks.

If only a CL-value may be used, as is the case with the conventional synchronous memory devices, t _AA of the memory device is determined by the data access time of the most remote block of the storage device (ie, the far-side block). In other words the CL value refers to the time required between the start and completion of a read operation in an SDRAM (see 1 ), the CL value must be set or set in consideration of the longest data access time (the data received from the far-side block). Thus, if only a value of CL is allowed for a memory device, as in the conventional SDRAMs, the near-side block will often have to wait for a time period longer than that required for access, although in fact this data is ready for access to one happier time than that of the far-side block. In addition to the drawbacks of conventional SDRAMs noted above, there are also other disadvantages resulting from the use of conventional SDRAMs listed below.

As market demand for high density memory storage devices increases, it is certain that memory sizes continue to increase as operating clock cycle time t _{CK is} further reduced. As the memory sizes become larger, the difference between a far side block and a near side block (Δt _AA ) also becomes larger, and Δt _AA becomes larger than the clock cycle time t _CK . As a result, the growth of the memory devices continues while they have or have only a CL value, and it is certain that the overall memory performance of the memory devices will experience critical losses. For example, when t _CK becomes smaller and smaller, Δt _AA becomes larger than a t _CK, and if the memories have only CL, while the determination of their CL value continues to be on the access time from a far-side block, the data of be delayed by more than one t _CK to meet the CL requirement.

SUMMARY OF THE INVENTION

Accordingly, there is a need for memory blocks having different CL values according to the location of each memory block of data output circuits containing a data output buffer stage.

The object of the invention is achieved by a semiconductor memory device according to claim 1, a latency control unit according to claim 2 or 4, a memory device according to claim 7 or 22, a method of accessing data in a semiconductor memory device according to claim 24 or 25, a method of reading data memory device according to claim 28 or 30 and a method for managing data read commands according to claim 31.

Additional aspects and advantages of the present generic inventive concept will be set forth in part in the description which follows, and in part will be set forth in the description which follows, or may be learned by practice of the general inventive concept.

BRIEF DESCRIPTION OF THE DRAWINGS

These and / or other aspects and advantages of the present generic inventive concept will become more apparent from the following description of embodiments with reference to the accompanying drawings, in which:

1 a timing chart illustrating a read operation of a semiconductor memory device (SDRAM);

2 an internal speed parameter of a DRAM data path;

3 a mode register of a DDR SDRAM and a mode register set (MRS);

4 Figure 4 illustrates how the MRS instruction is configured to set a CL;

5A Fig. 10 illustrates a memory array of a conventional SDRAM device;

5B FIG. 12 illustrates a plurality of memory blocks of the conventional SDRAM device of FIG 5A ;

6A Fig. 10 illustrates a bank of a conventional memory array which is divided into columns and rows;

6B to 6C FIG. 12 illustrates tables showing codes for accessing row addresses and column addresses of the bank of a conventional memory array of FIG 6A contains;

7 Fig. 12 illustrates a conventional memory cell array including a plurality of blocks 0-n, and illustrates how the blocks are decoded using a row decoder and a column decoder;

8th FIG. 10 illustrates a block diagram of a synchronous memory device according to an embodiment of the general concept according to the invention; FIG.

9A illustrates a CAS latency control block diagram of a CAS latency control section of FIG 8th according to an embodiment of the present general inventive concept;

9B FIG. 12 illustrates a detailed circuit diagram of the CAS latency control portion of FIG 8th according to an embodiment of the present general inventive concept;

10 illustrates a circuit diagram of the D _out of -Freigabeschaltung 9B according to an embodiment of the present general inventive concept;

11 FIG. 12 illustrates a timing diagram of actuation signals of the CAS latency control part of FIG 8th according to an embodiment of the present general inventive concept;

12 illustrates a memory device according to another embodiment of the present general inventive concept;

13A FIG. 12 illustrates a block diagram of a CAS latency control part of FIG 12 according to an embodiment of the present general inventive concept;

13B FIG. 12 illustrates a table of CL values corresponding to respective blocks of the memory address of 12 to be used, depending on the mode in which the blocks are accessed;

14 FIG. 11 illustrates a current detailed circuit arrangement of the CAS latency control part or control section of the embodiment of FIG 12 ;

15A FIG. 12 illustrates a CL address decoder of the CAS latency control section used to access the respective memory blocks of FIG 12 is used;

15B FIG. 13 illustrates a truth table provided to the CL address decoder of FIG 15A corresponds;

16 FIG. 12 illustrates a detailed circuit diagram of an output enable circuit of the memory device of FIG 12 ;

17 Figure 4 illustrates where different memory banks of the memory device may have a separate reserved CL value corresponding to the locations of the memory banks according to an embodiment of the present general inventive concept;

18A Fig. 12 illustrates another embodiment of the present general inventive concept wherein the CL values may be reserved for portions of the memory devices in which the memory banks are in different forms, such as rows, columns, banks, etc .;

18B FIG. 12 illustrates a table of logical values indicating the location of the addresses for the zones of the banks of FIG 18A identify;

19 FIG. 12 illustrates a CL address decoder of a CAS latency control part or control section useful for accessing the memory device of FIG 18A is used;

20A illustrates a non-OCID architecture storage device according to an embodiment according to an embodiment of the present generic inventive concept;

20B illustrates an OCID architecture memory device according to another embodiment of the present general inventive concept.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals designate like elements throughout. The various embodiments will be described below to explain the general inventive concept with reference to the figures.

8th FIG. 12 illustrates a block diagram of a synchronous memory device according to an embodiment of the present general inventive concept. FIG. According to 8th contains a memory bank 100 a memory block_0 100b (ie, a near memory block) and a memory block_1 100a (ie a remote memory block). A column decoder 101 and a row decoder 104 are used to access specific sections of a block within the bank 100 using logical codes. An address buffer level 102 receives signals which consist of addresses of a block to be accessed (e.g., from a read command) and provide addresses to each column decoder 101 and row decoders 104 , The row decoder 104 and the column decoder 101 in turn decode the addresses. For example, if the nearby memory block_0 100b is selected for access provides the address buffer level 102 one or more control signals. The address buffer level 102 provides addresses of the block to be accessed (ie, the address to be read) to the column decoder 101 , The command decoder 103 provides a control signal (pMRS) to a CAS latency control part 106 to provide a CAS latency (CL) based on the block or blocks to be accessed. The command decoder 103 further provides a read enable signal (REN) in accordance with the read command. In addition to providing the addresses to each of the decoders according to the column decoder 101 and the row decoder 104 provides the address buffer level 102 also an MRS_addr (ie the MRS address of an MRS command) to the CAS latency control part 106 , The MRS_addr signal sets the CAS latency values. The command decoder 103 supplies the pMRS signal to the CAS latency control part 106 when the MRS command is input. The address buffer level 102 also supplies a block address signal to the CAS latency control part 106 while the command decoder 103 the REN signal to the CAS latency control part 106 each returns when the read command is input.

The CAS latency component 106 contains a CL Mux and an output enable part 106a and a CL register part 106b that are more specific in the 9A and 9B are illustrated. The outputs of each of the blocks (Block_0 and Block_1) are connected to an output circuit and a pad unit 105 accessed. For example, the CAS latency control part receives 106 the pMRS signal and the MRS_Addr signal, which sets a CAS latency (CL) mode for use, and a column block address (Col_Block_Addr) to which the address buffer stage 102 Each time, a CL value is added to a DOUT enable circuit 106a '' (please refer 9A ) according to the column block address to be accessed. The MRS_Addr signal consists of bits stored in the mode register of the memory device (ie the CL register part 106b in the present embodiment) received by the CL register on an address bus and containing bits (e.g., A4 and A5 - see below) indicating the CL mode to be set.

As in the embodiment of 9A is illustrated, the CL register part 106b a register_1 for storing a CL (i) value and a register_2 for storing a CL (i + 1) value. The CL Mux 106a ' receives a first CL value from one of the registers between register_1 and register_2 and a second CL value from register_2, and outputs a selected CL value to the Dout enable circuit 106a '' in response to the Col_Block Addr signal (see 8th ), which comes from the address buffer stage 102 Will be received. The Dout enable circuit 106a '' receives the selected CL value from the CL Mux 106a ' and the REN signal (read enable) from the instruction decoder 103 and outputs an OUTEN signal (output enable) to the data output circuits (eg, the output circuits and the pad unit 105 ). When a first mode is set, a nearby memory block has 100b a CL value of CL (i) in the clock cycles, and the remote memory block 100a has a CL value of CL (i + 1) in the clock cycles. Conversely, if a second mode is set, both blocks will be in accordance with the nearby and the remote memory block 100b and 100a the same CL value of CL (i + 1) in the clock cycles. If according to the

8th and 9A the first mode is set and the Col_Block_Addr signal is at a low logic value, indicating that the nearby memory block 100b should be read, the outputs are from the CL register part 106b to the CL Mux 106a ' to a logical high, for CL (i) and a low logic value for CL (i + 1), indicating that the nearby memory block 100b has the CL value of CL (i) in the first mode. Table 1 below illustrates the first and second modes of the CAS latency control part 106 from 8th and 9A as an an example. "A4" and "A5" in 9B are bits of the MRS_Addr signal received over the address bus when the MRS command is input. For example, CL values of CL7 (eg, 7-cycle cycles) and CL8 (eg, 8-cycle cycles) are used in Table 1, however, it should be understood that other CL values are also used with the present general inventive concept can be. TABLE 1 MRS_ADDR Column block addr (nearby block) CA9 = 0 Column block addr (remote block) CA9 = 1 A5 A4 1st mode 0 1 CL7 = 1, CL8 = 0 CL7 = 0, CL8 = 1 2nd mode 1 0 CL7 = 0, CL8 = 1 CL7 = 0, CL8 = 1

It should be noted. Col_Block_Addr = 0 for the nearby memory block 100b and Col_Block_Addr = 1 for the remote memory block 100a , Further, the first mode is set when the bits on the address bus are equal to A5 = 0 and A4 = 1 (which bus carries the MRS_Addr bits) and when the pMRS signal is high according to the MRS instruction, and where the second mode is set if the bits on the address bus are A5 = 1 and A4 = 0 and if the pMRS signal is high according to the MRS instruction. Thus, the switching operation of the CL mode can be controlled by the MRS_Addr signal (A4 and A5). When the first mode is set and the Col_Block_Addr (CA9) is input as low (0) with a read instruction, the nearby memory block becomes 100b through the address buffer stage 102 and the CL value of CL7 and the CL value of CL8 are set as high (1) and low (0), respectively. That is, the nearby memory block 100b works with the CL value of CL7 (7 clock cycles). These CL values become the DOut enable circuit 106a '' fed in such a way that from the nearby memory block 100b read data from the output circuits and the pad unit 105 after 7 clock cycles. Consequently, the CAS latency control part 106 used to get the CL value of the nearby memory block 100b so that it is lower than the CL value (or equal to the CL value when the CL mode is the second mode) of the remote memory block 100a , In addition, it should be noted that although a switch SW in FIG 9A For the purpose of illustration only, the switch SW shown is not actually interposed between the CL register part 106b (Register_1 and Register_2) and the CL Mux 106a ' is interposed. The CL mode is actually switched in accordance with the MRS_Addr signal that is being supplied, and the CL value may be selected according to the Col_Block_Addr (on-the-fly) signal.

As in 9B is illustrated contains the CL register part 106b individual mode registers (ie MR1 and MR2), each having an array of electronic components (eg, inverter stages, PMOS and / or NMOS transistors, etc.) to select an output (P1 and P2) depending on the inputs which are received by the MRS_Addr signal and the pMRS_signal. The MRS_Addr signal contains bits indicating the CL mode, and the pMRS signal enables bits on the address bus (ie, the MRS_Addr bits) present in the respective mode registers MR1 and MR2 of the CL register portion 106b are to be stored. However, if the address of the remote memory block 100a (CA9 = 1) in the CL Mux 106a ' (Col Block Addr signal) is input, the CL value of the remote memory block 100a is set to CL8 by setting the CL8 output to "1" regardless of the value of the MRS_Addr signal. In other words, if the address of the remote memory block 100a (eg CA9 = 1) in the CL Mux and the output enable part 106a the values of CL8 and CL7 are always set to "1" and "0", respectively, but if the address of the nearby memory block 100b (eg CA9 = 0) in the CL Mux and the output enable part 106a the values of CL7 and CL8 depend on the Col_Block_Addr signal. The in the 8th and 9A - 9B illustrated CL Mux 106a ' may include an array of electronic components, including inverter stages, NAND gate (s), and NOR gate (s), as illustrated. However, the arrangement of the electronic components and / or the types of the electronic components included in the CL register part 106b and the CL Mux 106a ' are not limited to those shown, and these may be of any type and / or Arrangement of electronic components comprising the intended output results of the CAS latency control part 106 deliver as in 8th and in the 9A - 9B is illustrated.

The following is a detailed description of the operating modes of the CL Mux 106a ' in 9B , As in 9B 1, a NAND gate receives the CL Mux 106a ' the output (P1) from the mode register MR1 of the CL register part 106b which represents a CL7 (CL value of 7) signal (since the CL mode is the first mode), while a NOR gate of the CL Mux 106a ' the output (P2) from the mode register MR2 of the CL register part 106b which represents a CL8 (the CL value of 8) signal. The CL Mux 106a ' Also receives an input "A" corresponding to the Col_Block_Addr signal, which indicates whether the remote memory block 100a or the nearby memory block 100b should be read. The received input A is supplied to each of the gates according to the NAND gate (in an inverted form) and the NOR gate (in a non-inverted form). The NAND gate and the NOR gate receive bits from the MRS_Addr signal stored in the mode registers MR1 and MR2, as well as the input A, and determine the appropriate CL value to be sent to the DOUT enable circuit 106a '' is to be output, between the CL value for the far-side block_1 100a CL (i + 1), which is equal to CL8 in this exemplary embodiment (see Table 1) or CL value for the near-side block_0 100b as one of the quantities CL (i) and CL (i + 1), which is CL7 or CL8 in the exemplified embodiment (see Table 1). As a result, CL Mux selects 106a ' the CL value which is applied according to the address block to be read, and outputs the selected CL value to the Dout enable circuit 106a '' out. As described above, in the present embodiment, the CL gives Mux 106a ' size CL8 as the CL value every time the remote memory block 100a at input A, and CL Mux 106a ' will output either CL7 or CL8 if the nearby memory block 100b at the input A, corresponding to the MRS_Addr (A4 and A5) stored in the mode registers MR1 and MR2 (see 9B ).

The CL mode is set or changed using the MRS_Addr signal sent to the CL register 106b is created. For example, the MRS_Addr signal may be changed by an MRS command that is input by a user or executable code. According to Table 1 (see above) and 9B the MRS_Addr values (bits) are applied to the mode registers MR1 and MR2. The pMRS signal may serve as a CL mode change enable (CL change enable) signal, which enables the MRS_Addr values stored in the mode registers MR1 and MR2 to be updated by instantaneous MRS_Addr values on the address buses A5 and A4, respectively to replace. Thus, the pMRS signal is asserted high when the MRS command is input. As a result, the pMRS signal can be asserted high in such a manner that when the pMRS signal is high, the current MRS_Addr values are stored in the respective mode registers MR1 and MR2, and the CL mode can then be changed. For example, the CL mode may be changed between the first mode (where a "0" is stored in the mode register MR1 and a "1" is stored in the mode register MR2) and the second mode by setting the MRS_Addr values from "1 "And" 0 "are applied to the A5 and A4 bits of the address bus to the registers MR1 and MR2, respectively, and by assigning a logic high value to the pMRS signal (CL change enable). The first mode is the CL mode in which the remote memory block (ie, the remote block_1) 100a and the nearby memory block (ie, the near-side block_0) 100b have different CL values. The mode registers MR1 and MR2 continuously output the MRS_Addr values stored between the inverter stages as outputs P1 and P2 to the CL Mux 106a ' ,

According to the present embodiment, the PMRS signal is asserted high when the MRS command is input, and at this time, the MRS_addr signal in MR1 and MR2 goes through the address buffer stage 102 fed. That is, the CL mode may be changed by the MRS command, and a user (or alternative input source) may select either a first mode or a second mode through the MRS command or operation. Further, the CL value may be changed according to the column block address corresponding to the CL Mux 106a ' is entered whenever the read command is input (eg the CL value is changed "on the fly").

Table 2, shown below, illustrates examples of MRS_Addr values stored in the CL register part 106b and resulting CL value outputs of the CL register part 106b that result from entering MRS_Addr. Table 3, shown below, illustrates exemplary values associated with the input A from the CL Mux 106a ' ( 9B ) which correspond to the Col_Block_Addr and which indicates whether the nearby memory block 100b is read on a current read command (ie CA9 = 0) or the remote memory block 100a at the current read command (ie, CA9 = 1). As a result, the CL value can be changed "on the fly". The that is, the CL value used to read the data may change depending on the memory block read in accordance with the Col_Block_Addr signal received at the A input. In other words, the input A may be from the CL Mux 106a ' be changed at any time to select a different or different CL value to use for accessing the particular block or blocks. Thus, unlike conventional synchronous memory devices in which the CL value for all blocks in the memory device is set to a CL value only at a power initialization corresponding to a block furthest from an I / O part, only upon power initialization , the synchronous storage device of the present embodiment changes the CL values on the fly during an operation thereof according to Col_Block_Addr of the current read command.

In accordance with the inputs as illustrated in Tables 2 and 3, if the input MRS_Addr (A5 and A4) is to the CL register part 106b is applied as a logical input represented [0 1], furthermore, pMRS is high, and CA9 is logic "low", the output is from the CL register part 106b for CL7 (a CL value of 7 clock cycles) a logic high output 1, while the output for CL8 (CL value of 8 clock cycles) consists of a logic low output 0. In other words, the two outputs are from the CL register part 106b , in the 9B are logical outputs represented as [1-logical high and 0-logical low].

According to 9B For example, in the first mode, the inverse size of the input A from the Col_Block_Addr becomes the NAND gate along with P1 with the logical output high (1) from the CL register part 106b for CL7 fed. If the nearby memory block 100b is selected (input A is 0), the NAND gate generates an output according to logic low (0) from the inverted input A and logic high (1) from the CL register part 106b , A first inverter stage connected to the output of the NAND gate inverts the output of the NAND gate in such a manner that the CL7 output is logic high (1). On the other hand, if the remote memory block 100b is selected (input A is 1), the NAND gate generates a logical high output (1) from the inverted input A (which is logic low (0) if the remote memory block 100a is selected) and from the logical high value (1) of the CL register part 106b in such a way that the CL7 output becomes logic low (0) by the first inverter stage. The NOR gate receives the input A and the logic low output (0) from the CL register 106b for CL8. If the nearby memory block 100b is selected (input A is 0), the NOR gate outputs logic high (1) to a second inverter stage connected to the output of the NOR gate, which in turn outputs logic low (0) as CL8. If on the other side of the remote memory block 100a is selected (input A is 1), the NOR gate outputs logic low (0) to the second inverter stage in such a manner that the CL8 output is logic high (1). A similar analysis can be made 9B are applied when the memory device is placed in the second mode in which [1 0] is applied to the MRS_Addr signal via A5 and A4 bits of the address bus. As a result, a CAS latency (CL) of CL7 is applied when the data in the near-side block 100b from 8th is accessed when the MRS_Addr bits A5 and A4 are set to [0 1] to set the CL mode to the first mode. This exemplary output from CL Mux 106a ' [1 0] then becomes the Dout enable circuit 106a '' (please refer 9A and 9B ) is provided as the CL value (CL7 in this exemplary embodiment) to provide a CAS latency required to provide an output enable signal (OUTEN) to the output circuits and pad unit 105 for the data coming from the near-side block_0 (ie the nearby memory block) 100b be read out. In other words, the REN signal, which is the Dout enable circuit 106a '' is fed to the CL value delayed by the CAS latency control part 106 is delivered before the output of the data of the near-side block_0 100b is released. This example represents the first mode (mode 1) described above. It should be noted that a CL8 is connected to the Daut enable circuit 106a '' would be applied to REN for accessing the far side block_1 100a to delay. Thus, the output of data of the near-side memory block_0 100b be determined individually, regardless of the data to be read from the memory blocks, the far distance from the output circuits and the pad unit 105 are removed. How out 9B can be seen, the output of each mode register MR1 and MR2 from the CL Mux and the output enable part 106a logically high if the corresponding bits (A5 and A4) of MRS_Addr are logically low, and vice versa.

Table 4, below, illustrates the CL values obtained by the CL Mux 106a ' for each of the blocks according to the near-side block_0 100b and the far-side block_1 100a in the first mode and in the second mode, respectively. TABLE 4 CLOSE REMOTE 1st mode 7 8th 2nd mode 8th 8th

According to the above-mentioned Table 4, in the first mode, a CL7 of "1" and a CL8 of "0" become the Dout enable circuit 106a '' as a result of the output of the CL register part 106b and from CL Mux 106a ' ( 9B ) for the near-side block_0 100b while CL8 of "1" and CL7 of "0" are applied to the Dout enable circuit 106a '' as a result of the output of the CL register part 106b and from CL Mux 106a ( 9B ) for the far-side block_1. In contrast, in the second mode, a CL8 of "1" and a CL7 of "0" become the Dout enable circuit 106a '' as a result of the output of the CL register part 106b and from CL Mux 106a ' ( 9B ) for both blocks according to the near-side block_0 100b and for the far side block_1 100a created. Thus, according to this embodiment of the present general inventive concept, each block of the memory device may have a separate reserved programmable latency register, and the CAS latency may be changed at any time, depending on the blocks to be read at a given time. Specifically, the CL value is put into the Dout enable circuit 106a '' fed when the read command with Col_Block_Addr is fed.

10 illustrates a circuit diagram of the Dout enable circuit 106a '' from 9B according to an embodiment of the general inventive concept. The REN signal, which is input to a main delay device, is activated in response to a read command. The main delay delays the REN signal by a number of clocks that have been preselected to delay REN, which is set by CL (i) in the present example. A delay (1tck) delays the already delayed REN (delayed by the main delay means) by an additional clock cycle, so that a delay of CL (i + 1) is achieved). If CL (i) is CL Mux 106a ' (please refer 9A and 9B ) is selected, the OUTEN signal is activated after the number of clocks set by CL (i) has passed. For example, when the storage device is set to the first mode described above, the thumb release circuit delays 106a ' from 10 the OUTEN signal using only the main delay means to access the nearby memory block 100b and the main delay plus a delay (1tck) to access the remote memory block 100a , It should be noted that the Dout enable circuit 106a '' from 10 may contain multiple delays, depending on the number of CL registers to be used, which in turn depends on the number of memory blocks in the memory device in which data is stored.

Similar to the previous description in connection with the mode registers (ie 9B ) to select CL7 as the CL value that corresponds to the output enable circuit 106a '' should be created to the near memory block_0 100b Another set of mode registers may be used to access and release a different CL value for accessing the remote memory block_1 100a and to share it. When a CL for accessing and releasing the remote memory block_1 100a CL8 can be selected to provide the appropriate CAS latency (CL value) to the output enable circuit 106a '' to access shared data stored in the remote memory block_1 100a are stored. Thus, the CAS latency control part 106 from 8th Contain separate sets of mode registers to determine a CL value that is applied to access and release data from the respective memory block. Alternatively, a separate MRS instruction may be applied to each set of mode registers to set a CL mode for each respective memory block to be accessed, separate CL values may also be applied for each memory block. Thus, according to one embodiment of the present generic inventive concept, separate sets of mode registers are within the CAS latency control portion 106 from 8th (and the 9A - 9B ) is provided for each respective memory block to be accessed, thereby providing a block-reserved programmable latency register.

11 illustrates a timing diagram of operating signals of the CAS latency control part 106 from 8th according to an embodiment of the present general inventive concept. The timing chart illustrates the operation of the memory device in a case where either: (1) the first mode or the second mode (described above) is set, and the remote memory block 100a is selected by Col_Block_Addr or (2) the second mode is set and the nearby memory block 100b is selected by the Col_Block_Addr signal. As in 11 is illustrated, a clock CK is supplied by a memory controller. The CL values of register 1 and register 2 (see 9A and 9B ) are set by the MRS command and the MRS ADDR signal at timing tMRS of the timing chart (this is the timing at which the tMRS signal is activated). It should be noted that the CL values of the register 1 and the register 2 may alternatively be set by a fuse cut-through instead of the MRS instruction. The REN signal is activated in response to a read command. The column block address (ie, the Col_Block_Addr signal) has a logical high value (ie, it is the remote column block 100a selected), and the CL mode is set to one of the modes according to the first and second modes described above, CL8 is activated as a logical high value, and CL7 remains at a logic low value (see Table 4), through the operation of CL Mux 106a ' (see the 9A and 9B ). Alternatively, if the column block address is logic low or at a low logic level (ie, the nearby column block 100b is selected) and the CL mode is set to the second mode, CL8 is asserted high and CL7 remains at a low logic level in accordance with the operation of CL Mux 106a ' , It thus becomes the REN signal in the Dout enable circuit 106a '' in such a way that an OUTEN signal is activated after 7 clock cycles have elapsed. The output of the read data (D0) begins after 8 clock cycles or lapses thereof (see DATA OUTPUT, which subsequently begins to read (read) the OUTEN signal, which signal is delayed until the 8tCLK). If on the other hand, though not in 11 is shown, the column block address consists of a logic low value, such that the nearby column block 100b is selected, and the CL mode is set to the first mode described above, CL7 is set to the logic high value and CL8 is set to a low logic value instead. Thus, the REN signal then becomes at the Dout enable circuit 106a '' delayed in such a way that the OUTEN signal is activated after the elapse of 6 clock cycles. The output of the read data (D0) starts after the elapse of 7 clock cycles (see DATA OUTPUT which begins to access (read) the OUTEN signal, which signal is delayed, up to 7tCLK). As a result, valid data can be obtained from the output circuits and the pad unit 105 (please refer 8th ) to be read.

12 illustrates a memory device according to another embodiment of the present general inventive concept. In the memory device according to the embodiment of FIG 12 is a memory bank 200 divided into four memory blocks containing the block_0 200a , Block) 200b , Block 2 200c and Block_3 200d , wherein each memory block can be labeled with a different CL value. More specifically, Block_0 may be labeled CL (i), Block_1 may be labeled CL (i + 1), Block 2 may be CL (i + 2), and Block 3 may be CL (i + 3). Similar to the memory device of the embodiment of FIG 8th contains the memory device of 12 a column decoder 201 and a row decoder 204 for decoding specific portions (e.g., addresses) of memory blocks_0-3 within the memory bank 200 , An address buffer stage 202 receives a signal indicating an address of a block to be accessed, and supplies the received signal to each of the decoders according to the column decoder 201 , the row decoder 204 and also to a CAS latency control part 206 , For example, if the nearby memory block_0 200a is requested for access provides the address buffer stage 202 the address of the block to be accessed (to be read) to the column decoder 201 , The address buffer level 202 and an instruction decoder 203 provide the MRS_Addr signal or the pMRS signal to the CAS latency control part 206 to set a CL mode for the CL (s) to be applied based on the block or blocks to be accessed. The CAS latency component 206 contains a CL Mux and an output enable part 206a and a CL register part 206b , However, the CAS latency control part contains 206 in contrast to the CAS latency control part 106 from 8th four sets of mode registers (including CL registers), where each set of mode registers is designated for one of the memory blocks_0-3. The CAS latency component 206 returns an OUTEN signal to a Dout circuit and the pad unit 205 based on the CL values generated by CL Mux 206a ' be selected to enable or allow access to data from each of the blocks at a respective CL value. It goes out 12 show that the distances from each of the blocks (block 0, block 1, block_2 and block_3) from the Dout circuits and the pad unit 205 are different (d1 <d2 <d3 <d4). As a result of the respective distances of the memory blocks from the Dout circuits and the pad unit 205 is a difference in an inner data access time (Δdt) greater than an operation clock cycle time t _ck (Δdt> t _ck ). Thus, according to the present embodiment, each memory block is designated with a corresponding CL value in order to increase the performance and the operating speed of the memory device. For purposes of illustration only, CLs of 7, 8, 9, and 10 will be used in the following discussion in conjunction with the blocks corresponding to block_0 200a , Block_1 200b , Block 2 200c and Block_3 200d where CL (i) = 7, CL (i + 1) = 8, CL (i + 2) = 9, and CL (i + 3) = 10 in clock cycles, respectively. In a manner similar to that described above, when the MRS instruction is received from a memory controller (not shown) via the instruction decoder 203 is input, the pMRS signal is activated, and the MRS_Addr signal becomes the CAS latency control part 206 supplied in such a manner that the CL mode is set or set at this time. Thus, if a read command with the block address (ie Col_Block_Addr) from the memory controller via the command decoder 203 and the address buffer stage 202 is fed, the CL value of each block is determined by the block address.

13A illustrates a block diagram of the CAS latency control part 206 from 12 according to an embodiment of the general inventive concept. In 13A contains the CL register part 206b four CL registers, each CL register having a different CL value as a result of the MRS instruction. It should be noted that the CL values of the CL registers can also be adjusted by cutting a fuse instead of using the MRS instruction. The CL Mux 206a ' receives a first CL value (either CL (i), CL (i + 1), CL (i + 2) or CL (i + 3)) from one of the CL registers 1-4, a second CL value ( either CL (i + 1), CL (i + 2) or CL (i + 3)) of one of the CL registers 2-4, a third CL value (either CL (i + 2) or CL (i + 3)) from one of the CL registers 34 , and a fourth CL value CL (i + 3) from the CL register 4. The CL Mux 206a ' outputs a selected CL value to an output enable circuit in response to the Col_Block_Addr values fed thereto (see 12 and 13A ). As in 13B For example, any one of eight modes may be selected as the CL mode by the MRS_Addr values received together on the address bus and the pMRS signal. The CL mode can be changed by the MRS command. Thus, each of the memory blocks 0-3 may have a different (or the same) CL value reserved therefor, such that the different CL modes have a variety of different combinations of the CL values for each of the memory blocks Show. The CL mode, which displays the CL values for each memory block, can be selected based on application speeds. For example, in a low-speed application, it may be desirable to use CL values that are the same for all memory blocks (eg, mode 4). Similarly, in a high-speed application, it may be desirable to use different CL values for different memory blocks, such that data from the memory blocks closer to the output circuit and pad (pad) (e.g. Block_0), at the Dout circuits and the pad unit 205 can be read (accessed) earlier than the memory blocks that are further away and take more time to access the data. The CL mode can be selected by a user. In addition, as shown in FIG 13A the CL registers of the CL register part 206b corresponding to the respective memory blocks, respectively their respective CL values to the CL Mux 206a It should be noted that the switches SW1 and SW2 in 13A and only for the purpose of understanding the operations, and that the switches SW1 and SW2 are not actually interposed between the CL registers of the CL register portion 206b and the CL Mux 206a ' are inserted. Conversely, the CL mode is selected according to the MRS_Addr value, and the CL value can be switched according to the Col_Block_Addr value (in flight), so that no actual switches in the embodiment of FIG 13A required are. Furthermore, CL registers 1-4 may actually contain respective sets of mode registers (as discussed below with reference to FIG 14 will be described).

14 illustrates an embodiment of a current circuit arrangement with details of the CAS latency control part 206 from 12 , As according to the embodiment of 14 is illustrated contains the CL register part 206b four sets of mode registers, including a mode register 1, a mode register 2, a mode register 3, and a mode register 4, each of which provides a CL value for the MRS_Addr value. Thus, the MRS_Addr size fed to the mode register sets may contain multiple values. The first set of mode registers (CL (i + 3), CL (i + 2), CL (i + 1) and CL (i)) is associated with memory block_0, the second set of mode registers (CL (i + 3), CL (i + 2) and CL (i + 1)) is assigned to memory block_1, the third set of mode registers (CL (i + 3) and CL (i + 2)) is the memory block_ 2, and the fourth mode register CL (i + 3) is assigned to the memory block 3. The CL Mux 206a ' , in the 12 is illustrated, is also in 14 shown as a circuit diagram with a plurality of NAND gates and an inverter stage. Since the outputs from each of the mode registers of the sets of mode registers are output and supplied to the inputs of the NAND gates, as in FIG 14 is illustrated, an associated block address for a respective memory block is fed to the corresponding NAND gates. More specifically, a block address signal for memory block_0 is fed to the NAND gates, which receive the outputs of the set of mode registers for block_0, a block address signal for memory block_1 is fed to the NAND gates, which are the outputs of the set of Mode registers for block_1 are received, a block address signal for memory block 2 is fed to the NAND gates, which receive the outputs of the set of mode registers for block 2, and a block address signal is generated for memory block 3 in the NAND Input, which receives the outputs of the set of mode registers for block_3. The block address signals for the memory blocks may be logic high whenever corresponding memory blocks are selected in the read command. For example, when the read command requests data from block 0, a logic high signal (1) is put into a NAND gate together with each of the outputs of the first set of mode registers (CL (i + 3), CL (i + 2), CL ( i + 1) and CL (i)) individually. The logic high signal corresponding to the selected memory block is provided by a CL address decoder 271 (will be described later). As a result of the NAND gates and the inverter stage, which process the mode register output values and the block address signals, a signal CL (i + 3), CL (i + 2), CL (i + 1) and CL (i ), corresponding to the MRS_Addr value supplied to the sets of mode registers, and the block address signal (ie, the current block address set by the CL address decoder 271 is delivered). The current block address acts as a select signal which selects the logic that follows the set of mode registers of the corresponding memory block being accessed.

It becomes mm the mode of operation of the CAS latency control part 206 referring to the circuit diagram of 14 described. For purposes of description, assume that the memory device is programmed to operate in mode 1 (ie, in the first mode) as a CL mode (see FIG 13B ) in such a way that the block_0 operates with the CL value of CL7 (CL (i)) (7 clock cycles), the block_1 operates with the CL value of CL8 (CL (i + 1)) (8 clock cycles), block 2 operates with the CL value of CL9 (CL (i + 2)) (9 clock cycles), and block 3 operates with the CL value of CL10 (CL (i + 3)) (10 clock cycles). The sets of mode registers (Mode Register 1, Mode Register 2, Mode Register 3 and Mode Register 4) corresponding to each of the memory blocks (Block_0, Block_1, etc.) may be individually programmed using the pMRS signals from each set of mode registers (ie pMRS- Signals pMRS [1], pMRS [2], pMRS [3] and pMRS [4]), as described above with reference to the embodiment according to FIGS 8th . 9A and 9B has been described. Preferably, a one-time MRS command can enable all pMRS signals. That is, the CL register of mode register 1 for block 0 may be programmed to set the CL mode to the first mode, by logic low (0) from MRS_Addr to the CL register CL (i) and logic high (1) is applied by MRS_Addr to the CL registers CL (i + 3), CL (i + 2) and CL (i + 1), where CL (i) corresponds to CL7, CL (i + 1) corresponds to CL8, CL (i + 2) corresponds to CL9 and CL (i + 3) corresponds to CL10.

In this case, the CL value of CL7 becomes CL mux 206a ' is applied to the output enable circuit whenever the block address signal for block_0 indicates that block_0 is being accessed. Similarly, the CL registers of the mode register 2 of the block_1 may be programmed to set the CL mode to the first mode (mode 1) by applying a logic low signal (0) to the CL register CL (FIG. i + 1) corresponding to CL8 and applying a logic high signal (1) to the CL registers CL (i + 3) and CL (i + 2) corresponding to CL9 and CL10, respectively the address bus is made while a logical high value is given to the pMRS [2] signal. As a result, the CL value of CL8 becomes CL mux 206a ' is applied to the output enable circuit whenever the block address signal for block_1 indicates that block_1 is to be accessed. Further, the CL registers of the mode register 3 of the block_2 may be programmed to set the CL mode to the first mode (mode 1) by applying a logic low value (0) to the CL register CL (i + 2) corresponding to CL9 and applying a logic high value (1) to the CL register CL (i + 1) corresponding to CL10 through the address bus, while a logic high value is applied to the pMRS [3 ] Signal is issued. Thus, the CL value of CL9 becomes CLux 206a ' is applied to the output enable circuit whenever the block address signal of block_2 indicates that block 2 is to be accessed. Finally, the CL register of the mode register 4 of the block_3 may be programmed to set the CL mode to the first mode (mode 1) by applying a logic low (0) to the CL register CL (i + 3). which corresponds to CL10, which is done via the address bus, while a logical high value is given to the pMRS [4] signal. As a result, the CL value of CL10 becomes CL mux 206a ' is applied to the output enable circuit whenever the block address signal for block_3 indicates that block 3 is to be accessed. In other words, when programming each of the sets of mode registers corresponding to each block, a logical low value (0) is applied to the CL register corresponding to the CL value to be set such that an output of CL mux 206a ' that is the set CL value is at logical high (1) when the corresponding block is selected according to the column block address. For example, in the first mode (described above), a logic low value (0) is applied to the CL register CL (i) in the mode register 1 for the block_0. Accordingly, when Block_0 is selected by the corresponding column block address, the CL (i) output is a logical high value (1).

According to 14 For example, the pMRS signals (pMRS [1], pMRS [2], pMRS [3] and pMRS [4]) can be activated by the MRS command at a time. This means that all the pMRS signals can consist of the same signal. In this case, the signal MRS_addr (the bits A9, A8, A7, A6) is provided to the mode register 1 MR1, the signal MRS_addr (the bits A6, A5, A4) is supplied to the mode register 2 MR2, which Signal MRS_addr (the bits A3, A2) become the mode register 3 MR3, and the signal MRS_addr (bit A1) is supplied to the mode register 4 MR4, while the pMRS signals pMRS [1], pMRS [2], pMRS [3 ] and pMRS [4] are logically high.

The programming of the sets of mode registers (ie mode register 1 to mode register 4) of 14 can also be done sequentially. The other CL modes that are in 14 may be programmed for the sets of mode registers in a manner similar to that described above. It should be noted, however, that because the CL register CL (i) of the mode register 4 of the block_3 maintains the CL value of CL10 due to a data access time of the block_3, it typically is not required to have the CL register of the mode register 4 again. Further, in cases where the CL mode is changed so that the CL value or CL values of only one or two sets of the mode registers are changed, it is not necessary to reprogram all sets of the mode registers. An MRS instruction can therefore be applied to reprogram only the sets of mode registers which have a CL value which must be changed when the next data is read. Thus, each of the sets of mode registers may have only one CL register which stores a logic low value to indicate the CL value corresponding to the respective or respective memory block. If the block of memory in question is selected via the corresponding block address signal, the corresponding CL value will be CL Mux 206a ' is outputted through a series of NAND gates and an inverter stage to supply the corresponding CL value to the output enable circuit. As an example of the operation of the memory device of 14 when the memory device is operating in the first mode (ie, mode 1) and block_0 is to be accessed (ie, the block address signal for block_0, which is fed to the NAND gates of mode register 1, has a logic high value (FIG. 1)), the CL register CL (i) in the mode register 1 outputs a logic high value which is fed to a NAND gate, along with the other logical high value supplied from the block address signal As a result, a logic low value is output through this NAND gate and then inverted by the inverter stage so that the CL (i) output has a logic high value. Thus, the CL value is CL (i), which is CL7 in the present embodiment.

In another example, if the memory device is operating in the first mode and block 2 is to be accessed (ie the block address signal for block 2 is fed to the NAND gates of mode register 3 and is at a logic high value (1)), In the mode register 3, the CL register CL (i + 2) outputs a logic high value which is input to a NAND gate together with the other logical high value supplied from the block address signal for Accordingly, a logic low value is output by this NAND gate and then inverted by another NAND gate, so that the CL (i + 2) output has a logic high value.

When the CL mode is set as the first mode (mode 1), the output of CL (i) of the mode register 1, the output of CL (i + 1) of the mode register 2, the output of CL (i + 2) of the Mode register 3 and the output of CL (i + 3) of the mode register 4 are all at a high logical value "1". Thus, when the read command contained in the column block addresses enters the CL address decoder 271 is fed (see 14 ), one of the outputs of the mode registers 1 ~ 4 becomes logically high through the CL mux 206a ' is selected and output to the output enable circuit.

15A illustrates the CL address decoder 271 of the CAS latency control part 206 which is to access the respective memory blocks of 12 is used, and 15B illustrates a corresponding truth table. In particular, the CL address decoder 271 from 15A to be used to provide a block address signal consisting of a logic high signal to the NAND gates (NEVER-GATE) corresponding to the appropriate set of mode registers, in the CAS latency control part 206 , what in 14 is illustrated. 15B contains the truth table for the CL address decoder 271 , The column block addresses can be represented as two bits BA1 (block address bit 1) and BA0 (block address bit 2). As in 15B is illustrated, "00" corresponds to block_0, "01" corresponds to block 1, etc. BA1B and BA0B represent the inverse of block address bits BA1 and BA0, respectively. As with the CL address decoder 271 and also based on the corresponding truth table, whenever a memory block is selected, using the appropriate combination of column block address bits, the CL address decoder generates 271 a logic high signal as a block address signal for the relevant or respective memory block being selected. The CL address decoder 271 returns the block address signal for the respective memory block to the CL mux 206a ' (please refer 14 ,

16 FIG. 12 illustrates a detailed circuit diagram of an output enable circuit of the memory device of FIG 12 according to an embodiment of the present general inventive concept. A read enable signal (REN) responds to a read command. According to the present embodiment, the output enable circuit includes a main delay circuit and three sub-delay circuits. The main delay circuit delays the REN signal by 7 clock cycles in such a manner that the CL value is equal to CL7, the first sub-delay circuit delays the REN signal by an additional clock cycle in such a manner that the CL value is equal CL8, the second sub-delay circuit delays the REN signal for another or additional clock cycle so that the CL value is equal to CL9, and the third sub-delay circuit delays the REN signal for another additional clock cycle, such that the CL Value is equal to CL10. Based on the input from the CL mux 206a ' the output enable circuit delays the REN signal by an appropriate delay value to produce a proper OUTEN signal for each respective memory block in accordance with the CL value. The output enable circuit may operate using a delay locked loop (DLL) or using a phase locked loop or phase locked loop (PLL). It should again be noted that these CL values (CL7, CL8, etc.) are examples and the scope of the present general inventive concept is not limited thereby.

17 illustrates a memory device with four memory banks A, B, C and D according to an embodiment of the present general inventive concept. The present embodiment may operate and operate in a manner similar to the prior embodiments described in connection with memory block access. Here, the memory banks A and B are shown as remote banks, with respect to output circuits and pad, while the memory banks C and D are represented as nearby banks, with respect to the output circuits and the pad ). Here Bank A and Bank B (the remote banks) each have a longer data line than that of Bank C and Bank D (nearby banks). According to an embodiment of the present general inventive concept, when there is a difference in the data line lengths between the memory banks in the illustrated manner, each memory bank may be formed to have a different CL value according to the length of the data line thereof. Thus, the nearby banks C and D have a shorter CL value than the CL value for the remote banks A and B. To compensate for this difference in data line lengths, a CL Mux (not shown) provides a suitable one CL value to a data output circuit (not shown) in response to a bank address signal received with a read command. Thus, unlike the previous embodiment in which the CL value can be determined based on a memory block address, here the CL value is determined based on the bank address. It should be understood, however, that the embodiments of the present generic inventive concept may be practiced with any particular bank, or may be applied to any particular bank.

The storage device of 17 may provide a CAS latency control portion (not shown) similar to the CAS latency control 106 and 206 of the previous embodiments. This CAS latency control portion selects the CL value to be applied to the output circuits and also to the pad for the memory bank being accessed, with the read command corresponding to a CL mode being triggered by a Pre-programming of the CAS latency control part and the bank address of the read command is set.

18A illustrates a memory device 400 According to yet another embodiment of the present general inventive concept, the CL values may be assigned to sections of memory banks A, B, C and D if memory arrays thereof are not split in a simple manner. For example, each of the blocks 1, 2, 3 and 4 of the memory device 400 be divided based on a predetermined data access time, which may be dependent on a distance between the output or output circuits and the pad unit and each block 1, 2, 3 and 4. Thus, a CL value for block 1 may be set to CL (i), while a CL value of block 2 having a greater distance from the output circuits and the pad unit may be set to CL (i + 1) - Value, and a CL value of the block 3 farther from the output circuits and the pad unit than any one of the blocks 1 and 2 can be given CL (i + 2), and a CL value of the block 4 positioned furthest away from the output circuits and the pad unit with respect to the blocks 1, 2 and 3, as shown, may be occupied by CL (i + 3). As a result, the bank addresses, column addresses, and row addresses can be used to determine which block in which bank should be accessed, and also which CL value to associate with a respective block. The individual benches of 18A are shown as being divided into rows and columns, depending on their position with respect to the output circuits and the pad unit.

A row decoder (R / D) may be located horizontally at the bottom of Bank A and Bank C and above Bank B and Bank D in such a manner that the rows extend in a vertical direction and a row address the bank A and the bank B in blocks 3 and 4 divides. A column decoder (C / D) may be located vertically on a left side of the bank C and / or the bank D and on a right side of the bank A and / or the bank B such that columns extend in a horizontal direction, and a column address may divide bank C and bank D into blocks 1 and 2. Each of the banks A, B, C and D may have their own row decoder and column decoder.

18B FIG. 12 illustrates a table of logical values indicating the location or location of addresses for blocks of banks of 18A identify. The term "block" refers to numbered zones in the storage device 400 , As in 18A is illustrated, each of the blocks extends between two memory banks. According to 18B For example, the addresses of the blocks may be represented using a series of bits including BA0, BA1, RA _MSB and CA _MSB . In particular, since four memory banks A, B, C and D are provided, two bits (ie, BA0 and BA1) are required to indicate which of the memory banks is to be accessed by the read command. CA _MSB (column address) splits memory banks C and D into columns 1 and 2 by columns. More specifically, CA _{MSB represents} the most significant bit of a column address for encoding the memory block. Similarly, RA _MSB (row address) splits memory banks A and B. a row or row in blocks 3 and 4. More specifically, RA _MSB may be the most significant bit of a row address for encoding the memory block.

18B Figure 13 illustrates a truth table indicating how each of the blocks can be selected when the storage device 400 does not have a simple structure. The X's in 18B indicates "do not care" bits indicating that an address selection selects a bank or block based on the combination of other bits, regardless of a value of the do not care bit. For example, to select block 3 in bank A, the bank address bits BA1 and BA0 are "00", and RA _MSB is "0", and since block 3 or block 4 in bank A is accessed using row addresses, the column address bit (CA _MSB ) consists of a do not care-bit "X".

19 Figure 12 illustrates a CL address decoder of a CAS latency control portion (not shown) used to access the memory device 400 from 18A access. Since the operation of the CL address decoder should be known to those skilled in the art, a truth table is not provided here. The CL address decoder of 19 can work in a similar way as the CL address decoder 271 from 15A , As in 19 12, the CL address decoder receives bank address bits (BA0 and BA1), row address bits (RA _MSB ), and column address bits (CA _MSB ) and their corresponding inverse values. The CL address decoder processes the received bits to produce a logic high signal at the particular memory block that is selected and to provide a logic high signal to a CL Mux (not shown) such that the CL Mux receives a select appropriate CL value corresponding to the selected block.

The 20A and 20B illustrate a storage device 500 (Chip) with a non-ODIC (external DQ internal clock) architecture and a memory device 500 ' (Chip) with an ODIC architecture according to still further embodiments of the general inventive concept. In the storage device 500 is an I / O pad (pad or pad) 502 located on a right side of the chip between a memory bank C and a memory bank D. In the storage device 500 ' are I / O pads 502 ' located on each side of the chip. As a result, a number of horizontal rows of data or lines pass between the memory banks in the non-ODIC architecture, and these may reside in the ODIC architecture memory device 500 ' be reduced in such a way that most, if not all, of the data lines are vertical. As in 20B As illustrated, the present general inventive concept may be embodied in the memory device 500 ' with the ODIC architecture with left I / O pad 502 ' and right I / O pad 502 ' and a control unit 504 ' will be realized. In particular, each memory bank includes left and right sections indicated by letters A / C and B / D. Each bank in the ODIC architecture is divided into two sections, for example a bank A located on the left and right sides of the storage device 500 ' is located. Read data for each bank can be output from both the left and the right position at the same time. When a read operation for bank A occurs, half of the data is read from the left portion of bank A and can go to the left I / O pad 502 ' and the other half of the read data may be output at the same time from the right portion of the bank A to the right I / O pad 502 ' , Also, each memory bank may be in a zone 1 and a zone 2 according to the distance from the left I / O pad 502 ' and the right I / O pad 502 ' be split. The zone 1 is closer than the zone 2 on each I / O pad, so that the zone 1 has a shorter CL value than the zone 2. The zones 1 and 2 can be divided by the column block address or the row block address, namely based on whether the row decoders or column decoders in the memory chip 500 ' are located. As in 20B 1 and 2, the zones 1 and 2 may be divided by the column block address because a column decoder (Cm) is located on the side of each bank. In a similar manner to the embodiments described above, the CL value for zone 1 (near) and 2 (remote) may be differentiated by a column block address.

Claims (36)

Semiconductor memory device, comprising: at least one memory bank ( 100 ; 200 ) with a plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) in order to store data, whereas those in the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) can be read in response to a read command; a control unit ( 106 ; 206 ) for generating a plurality of CAS latency values and predetermined blocks of the memory blocks (CAS) around the CAS latency values ( 100a . 100b ; 200a . 200b . 200c . 200d ) to be read; and an output circuit ( 105 ; 205 ) for outputting the data in response to a read signal activated by a read command, the output circuit ( 105 ; 205 ) the data from each of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) based on the assigned CL values, the control unit ( 106 ; 206 ) Comprises: a CAS latency register ( 106b ; 206b ) containing a plurality of sets of mode registers, each of the sets of mode registers being adapted to generate a plurality of the CAS latency values; and a CAS latency mux unit ( 106a ; 206a ) for selecting one of the plurality of CAS latency values from each set of mode registers corresponding to a column address included in the read command and the selected CAS latency values of predetermined blocks of the memory blocks (FIG. 100a . 100b ; 200a . 200b . 200c . 200d ), based on predetermined conditions of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), and wherein the predetermined conditions of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) a location of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) with respect to the output circuit ( 105 ; 205 ) in which the data is output. A latency controller that is usable in conjunction with a memory device having a plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) for storing data, comprising: a CAS latency register ( 106b ; 206b ) containing at least one set of mode registers, each set of mode registers adapted to generate a plurality of CAS latency values associated with one of the memory blocks, the plurality of CAS latency values being different from each other based on a location of the respective memory blocks, from which data is read; a CAS latency mux unit ( 106a ; 206a ) for receiving the generated CAS latency values from the at least one set of mode registers and for selecting one of the received CAS latency values based on a signal containing information regarding the memory blocks to be read; and an output enable circuit ( 106a ''; 206a '' ) receiving the selected CAS latency value and also receiving a read enable signal activated by a read command and outputting an output enable signal to an output circuit. The latency control unit of claim 2, wherein the output circuit outputs the data stored in the accessed memory blocks according to the read command based on the selected CAS latency value and the output enable signal. Latency control unit usable with a memory device having a plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) to store data and a data output circuit ( 105 ; 205 ) to output the stored data from the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) in accordance with a read enable signal, the latency control unit ( 106 ; 206 ) Contains: a latency determination unit ( 106a '; 206a ' ) for determining a plurality of latency values, and for selecting predetermined values of the latency values based on an address signal indicative of locations of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) to be read indicates; and an output enable unit ( 106a ''; 206a '' ) for receiving the latency values determined by the latency determination unit ( 106a '; 206a ' ) and the latency values to the data output circuit ( 105 ; 205 ) to output the data from the plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), wherein the data is output according to predetermined values of the plurality of latency values, based on the location of the memory block (Fig. 100a . 100b ; 200a . 200b . 200c . 200d ) from which the data is output. A semiconductor memory device according to claim 1, further comprising: an address buffer stage ( 102 ; 202 ) for receiving an address signal to output MRS addresses for setting a CAS latency mode when an MRS command is input and to output addresses of the address signal when a read command is input; an address decoder ( 101 . 104 ; 201 . 204 ) for decoding the addresses and for selecting one of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) having block addresses; an instruction decoder ( 103 ; 203 ) for receiving the MRS command and outputting a pMRS signal and for receiving the read command and outputting a read enable signal; and wherein the control unit is configured to receive the MRS addresses and the pMRS signal when the MRS command is input so that the CAS latency mode is set in accordance with a plurality of CAS latency values to receive block addresses to activate one of the plurality of CAS latency values and to receive the read enable signal and to supply an output enable signal to the output circuit ( 105 ; 205 ) according to the activated CAS latency value, the output circuit outputting the read data from the selected memory block in response to the output enable signal. The memory device of claim 5, wherein: each of the plurality of mode registers generates predetermined CAS latency values based on the MRS addresses when the pMRS signal is activated, and the control circuit (14). 106 ; 206 ) further comprises an output enable circuit for receiving the read enable signal and for activating the CAS latency value to delay the read enable signal by a number of clocks indicating or corresponding to the activated CAS latency value, and to output the delayed read enable signal as the output enable signal. A memory device, comprising: an output circuit ( 105 ; 206 ); a large number of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) spaced a different distance from the output circuit ( 105 ; 205 ) exhibit; and a CAS latency control part ( 106 ; 206 ) for operating or actuating the output circuit ( 105 ; 205 ) in a plurality of modes including at least a first mode in which the output circuit ( 105 ; 205 ) is operated with a CAS latency value that is the same for accessing the plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), and in a second mode in which the output circuit ( 105 ; 205 ) are operated with CAS latency values that are different in order to access the plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), wherein the different CAS latency values are different latency values based on the location of the particular memory block from which the data is read. A memory device according to claim 7, wherein said plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) comprises a plurality of memory banks. A memory device according to claim 8, wherein said plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) further comprises a plurality of zones, within the plurality of memory banks. A memory device according to claim 7, wherein said CAS latency control part ( 106 ; 206 ) is programmable between the plurality of modes using two or more bits of a mode register set (MRS) command. A memory device according to claim 7, wherein said CAS latency control part ( 106 ; 206 ) a memory address of one of the plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) to be accessed, from a read command, and making a selection according to the received memory address among the different CAS latency values when the output circuit ( 105 ; 205 ) works in the second mode. A memory device according to claim 7, wherein said CAS latency control part ( 106 ; 206 ) Comprises: a plurality of registers corresponding to the plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) to store the respective CAS latency values; and a multiplexer ( 106a '; 206a ' ) for selecting from the plurality of respective CAS latency values depending on whether the CAS latency control part ( 106 ; 206 ) operates in the first mode or in the second mode. Memory device according to Claim 12, in which the multiplexer ( 106a '; 206a ' ) an address of a current memory block ( 100a . 100b ; 200a . 200b . 200c . 200d ), which is accessed, and selects a CAS latency value corresponding to the received address. A memory device according to claim 13, wherein the CAS latency control part (16) 106 ; 206 ) further comprises: an output enable circuit ( 106a ''; 206a '' ) for receiving the selected CAS latency value and a read enable signal associated with a read command and for delaying the read enable signal by a number of clock cycles corresponding to the selected CAS latency value and an output enable signal the delayed read enable signal, to the output circuit ( 105 ; 205 ). The memory device of claim 13, wherein the received address includes at least one of a bank address, a column address, and a row address. A memory device according to claim 13, wherein said plurality of memory blocks ( 200a . 200b . 200c . 200d ) Comprises: four memory banks arranged in each corner of a memory chip on which the memory device ( 200 ; 400 ; 500 ) is implemented such that the output circuit ( 205 ) is disposed on one side of the memory chip between two memory banks; and four memory zones arranged under the four memory banks, such that each of the four memory zones is at a different distance from the output circuit (FIG. 205 ) having. The memory device of claim 16, wherein each of the memory zones extends over more than one of the memory banks. The memory device of claim 17, wherein the first of the memory zones extend along a row direction of the memory banks, and second zones of the memory zones extend along a column direction of the memory banks. The memory device of claim 12, wherein: said plurality of registers comprise a plurality of mode registers programmable by following bits of an MRS instruction received over an address bus; and the multiplexer ( 106 ''; 206 '' ) has a plurality of logical units to output a logic high value at an output corresponding to the selected CAS latency value. A memory device according to claim 12, wherein said plurality of registers stores said plurality of CAS latency values corresponding to said plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) corresponds. A memory device according to claim 7, wherein said plurality of different CAS latency values satisfy the different data access times of said plurality of memory blocks (Fig. 100a . 100b ; 200a . 200b . 200c . 200d ) corresponds. Storage device with a plurality of storage units ( 100a . 100b ; 200a . 200b . 200c . 200d ); and a control part ( 106 ; 206 ) for receiving a current address associated with a read command to select a CAS latency value during an operation of the memory device among a plurality of CAS latency values corresponding to the plurality of memory units (Fig. 100a . 100b ; 200a . 200b . 200c . 200d ), according to the current address, and the selected CAS latency value to an output circuit ( 105 ; 205 ) of the storage device ( 100 ; 200 ). A memory device according to claim 22, wherein said plurality of memory units ( 100a . 100b ; 200a . 200b . 200c . 200d ) Comprises: a remote storage device having a long data access time and a corresponding CAS latency value; and one or more nearby memory units having shorter access times and having CAS latency values that are programmable to be less than or equal to the CAS latency value of the remote storage device. Method for accessing data in a semiconductor memory device having a multiplicity of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), which method comprises the steps of: setting a CAS latency mode comprising a plurality of CAS latency values corresponding to a plurality of said memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) when an MRS command is input; Receive an address to indicate which memory block ( 100a . 100b ; 200a . 200b . 200c . 200d ) is read when a read command is input; Selecting one of the plurality of CAS latency values indicated by the selected address; Delaying a read enable signal associated with the read command to a number of clocks determined by the selected CAS latency value and outputting an output enable signal to an output circuit ( 105 ; 205 ) according to the delayed read enable signal; and outputting data from the memory block ( 100a . 100b ; 200a . 200b . 200c . 200d ) designated by the address based on the output enable signal. Method for accessing data in a semiconductor memory device, comprising a multiplicity of memory banks, each of which has a plurality of memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), in which data is stored, which method comprises the following steps: assigning a plurality of CAS latency values, which are output by an output circuit ( 105 ; 205 ), which releases the output of data stored in the plurality of memory blocks according to the plurality of CAS latency values, to the addresses indicating the locations of the memory blocks to be read; Receive an address of a selected memory block ( 100a . 100b ; 200a . 200b . 200c . 200d ) to be read associated with a read command; and providing a signal which is delayed according to the CAS latency value of the addressed memory block to the output circuit ( 105 ; 205 ); and outputting the data from the addressed memory block ( 100a . 100b ; 200a . 200b . 200c . 200d ) in accordance with when the delayed enable signal is received. The method of claim 25, wherein the allocation of the plurality of CAS latency values provided by the output circuit ( 105 ; 205 ), assigning different CAS latency values to the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), which different distances from the output circuit ( 105 ; 205 ) exhibit. The method of claim 25, wherein the CAS latency values are predetermined addresses of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) in such a way that smaller CAS latency values in memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) closer to the output circuit ( 105 ; 205 ) and increasingly larger CAS latency values to the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), which are progressively farther from the output circuit ( 105 ; 205 ) are positioned so that there is a delay in the output of the data stored in the memory blocks are increased proportionally, with the increase in the distance of the memory block ( 100a . 100b ; 200a . 200b . 200c . 200d ) from the output circuit ( 105 ; 205 ). Method for reading data from a memory device having at least two memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), whereafter: an address signal containing information pointing to at least two addresses of the memory device to be read is provided; at least two CAS latency values are selected which delay the output of the data to be read from the memory device based on address signal information for predetermined time periods; and releasing the output of the data to be read from the at least two addresses of the memory device at different delay time periods based on the CAS latency value selected for the corresponding address after receiving a read enable signal conveying the command, To read data from the at least two addresses of the memory device. The method of claim 28, wherein the address signal information includes information about the location of the addresses of the memory blocks to be read. A method of reading data from a memory device having an I / O pad and a plurality of memory blocks having different distances from the I / O pad, the method comprising the steps of: Applying different CAS latency values to the plurality of memory blocks by changing the CAS latency value during operation of the memory device depending on the location of the memory block to be read when a read command is input. Method for managing data read commands in a memory device ( 100 ; 200 ), which method comprises the steps of: selecting different column address strobe (CAS) latency values so that these memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) having different data access times; and delaying a read enable signal associated with each of the memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ), according to the different CAS latency values, if the different memory blocks ( 100a . 100b ; 200a . 200b . 200c . 200d ) is accessed. The method of claim 31, wherein selecting the different CAS latency values comprises enabling or enabling a CAS latency mode corresponding to different CAS latency values for each memory block. 100a . 100b ; 200a . 200b . 200c . 200d ) to be set by an MRS command. The method of claim 31, wherein delaying the read enable signal comprises: receiving a read command having an address to obtain a specified memory block (16); 100a . 100b ; 200a . 200b . 200c . 200d ) to read; and selecting the CAS latency value associated with the specified memory block ( 100a . 100b ; 200a . 200b . 200c . 200d ) corresponds to the received address. The method of claim 31, wherein delaying the read enable signal comprises: Delaying the read enable signal until associated with a specified memory block by a number of clock cycles of the corresponding CAS latency value; and Providing an output enable signal for enabling an output circuit that comprises or receives read data from the specified memory block in accordance with the delayed read enable signal associated therewith. The method of claim 31, wherein selecting the different CAS latency values comprises selecting a first CAS latency value for a nearby memory block and selecting a second CAS latency value for a remote memory block via an MRS command, the remote memory block is the memory block farthest from an output circuit, and the nearby memory block is closer to the output circuit (FIG. 105 ; 205 ) is located as the remote storage block. The method of claim 35, wherein selecting the first CAS latency value comprises: Setting the first CAS latency value to be less than the second CAS latency value in a first mode of operation; and adjusting the first CAS latency value to be equal to the second latency value in a second mode of operation.

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