DE102006027826A1 - circuitry - Google Patents

Abstract

A circuit arrangement comprises a power inverter (INV), a potential shifter (LSHIFT) and a power driver (DRIV). On the output side, the power inverter (INV) provides a blocking signal (LSIG) with low resistance and inverse to a pulse-width-modulated drive signal (PWM). The potential shifter (LSHIFT) can be activated and deactivated depending on the blocking signal (LSIG). The potential shifter (LSHIFT) provides a switching signal (SSIG) on the output side only if the potential shifter (LSHIFT) is activated by the inhibit signal. The output driver (DRIV) can be coupled with an upper switch (X2) on the output side to activate the upper switch (X2). The power driver (DRIV) turns on the upper switch (X2) depending on the switching signal (SSIG). The power driver (DRIV) also turns off the upper switch (X2) when the potential shifter (LSHIFT) is disabled by the inhibit signal (LSIG).

Description

The The invention relates to a circuit arrangement, in particular a Half-bridge driver forms for driving an upper switch and optionally one lower switch of a half-bridge arrangement.

Such Half-bridge arrangements For example, in DC-DC switching regulators in step-down converter or boost converter arrangements or in motor control systems used to convert electrical energy with high efficiency or to drive electric motors with high efficiency. These half-bridge arrangements can for services be designed from a few watts to several thousand watts. For driving the upper switch and possibly provided lower Switches of the half-bridge arrangement are Each driver required a quick turn on and off enable the switch. It must also be ensured that the upper switch and the bottom switch of the half-bridge arrangement are not turned on simultaneously to a short circuit and a damage to avoid the switch.

The The object of the invention is to provide a circuit arrangement the easy and reliable is.

The Task is solved by the characteristics of the independent Claims. Advantageous developments of the invention are characterized in the subclaims.

The Invention is characterized by a circuit arrangement, the a power inverter, a potential shifter and a power driver. The power inverter has a pulse width modulated input side Drive signal supplied. Of the The power inverter provides a blocking signal with low impedance on the output side and inversely to the pulse width modulated drive signal ready. the Potential slider is the input side, the pulse width modulated drive signal or a differential pulse signal can be supplied. The differential pulse signal is derived from the pulse width modulated drive signal. Of the Potential slide is dependent can be activated and deactivated by the blocking signal. The potential slider On the output side, it provides a switching signal which indicates an increased auxiliary potential is related. The potential slider provides the switching signal dependent supplied from the input side pulse width modulated drive signal or differential pulse signal, when the potential shifter is activated by the blocking signal. The power driver is the output side with an upper switch can be coupled to control the upper switch. The power driver switches the upper switch on a dependent from the switching signal. The power driver switches the upper switch furthermore, when the potential shifter is deactivated by the blocking signal becomes.

Of the The advantage is that such a circuit arrangement is very simple is and requires only a small number of components. Further is a low-impedance structure of the circuit arrangement possible. Thereby the circuit is very reliable and insensitive in particular across from Pollution or opposite Moisture that is too unwanted, parasitic capacities can lead between the components of the circuit. Thereby the circuit arrangement can be operated particularly safely. Furthermore, the circuit arrangement is also for high clock frequencies of the pulse width modulated Drive signal suitable, for example, for clock frequencies of more than a megahertz.

The Circuitry can by the small required number be built on components very simple and inexpensive discreet. The reliability and reliability of the circuit does not significantly impaired. This has the advantage that, by suitable choice of the components, in particular of the semiconductor components, a dielectric strength the circuit arrangement is very easy to specify. Even with discreet Structure of the circuit arrangement requires the circuit arrangement only a small area. However, the circuit arrangement can also be integrated Circuit can be formed.

The Circuit arrangement is suitable for different power topologies, especially for Step-down converter, step-up converter or step-up / step down converter. Further the circuit arrangement is particularly suitable for class D amplifier. By the high reliability and reliability, the circuit arrangement is also particularly good suitable for a use in a motor vehicle.

In an advantageous embodiment, the circuit arrangement comprises a one-way deadtime, the input side with the power inverter is coupled and thereby the input side, the blocking signal can be fed. The one-way deadtime element is the output side with a lower switch coupled to drive the lower switch. The one-way deadtime element switches the lower switch on depending on a first parameter value of the inhibit signal and switches the lower one Switch off dependent from a second parameter value of the inhibit signal.

The first and / or the second parameter value of the blocking signal relate in particular to a rising or falling edge of the blocking signal or, for example, to an exceeding or Falling below a predetermined threshold by the inhibit signal. A dead time of the one-way dead time member is constituted by a period between a time of a change of the inhibit signal for turning on the lower switch and a time of actually turning on the lower switch. By suitable dimensioning of the dead time can be ensured that the upper switch is already turned off before the lower switch is turned on. As a result, a short circuit is reliably prevented, which otherwise caused by the simultaneously switched upper and lower switches and can lead to destruction of the upper and / or lower switch. The circuit arrangement thus forms a very reliable and reliable half-bridge driver, which is insensitive to dirt and moisture. Furthermore, it is ensured that the dead time is at least maintained. In particular, this is true regardless of a direction of current flow out of or into a half-bridge center node electrically formed between the upper and lower switches. As a result, the circuit arrangement is particularly suitable for use in a class D amplifier. Another advantage is that the blocking signal activates the activation of the upper and lower switches in such a way that they can not be switched on simultaneously. This locking is done selbstregelnd, that is, in the presence of unwanted parasitic capacitances between the components of the circuit, for example by pollution or moisture, possibly increases the dead time, but the overlapping switching on the upper and lower switch is thereby particularly reliably prevented.

In In this context, it is advantageous if the one-way deadtime member a delay transistor and a variable resistor. The adjustment resistance is connected to a control terminal of the delay transistor. An input terminal of the delay transistor forms an input of the one-way deadtime element. An output connection of the delay transistor forms an output of the one-way deadtime element. The dead time of the one-way dead time element is dependent on a Millerkapazität of the delay transistor and a resistance value of the adjustment resistor.

Of the Control terminal of the delay transistor is in particular by a gate terminal or a base terminal educated. The input terminal is in particular by a drain connection or a collector terminal is formed. The output terminal is in particular by a source connection or an emitter terminal is formed. The advantage of the circuit arrangement is that such a reliable one delay a change of Disable signal to turn on the lower switch and the actual Switching on the lower switch is possible. Furthermore, the desired delay or Dead time very easy by choosing the resistance value of the adjustment resistor predetermined. Another advantage is that through the one-way deadtime link only switching on the lower switch is delayed, switching off but essentially instantaneous he follows. This ensures that the bottom switch is off, before the upper switch is turned on. Furthermore, only one low number of components for the one-way deadtime required and the circuit arrangement is thereby very simple and inexpensive.

In In this context, it is also advantageous if the control terminal of the delay transistor a control signal via the adjustment resistor fed is for activating or deactivating the one-way deadtime element dependent on the control signal. This has the advantage that the one-way deadtime is easily switchable by the control signal. In a deactivated State, the bottom switch remains off regardless of one Course of the blocking signal. In an activated state forms the lower switch a synchronous rectifier, which depends on delayed the lock signal can be switched on and essentially switched off without delay. By the control signal is for different loads a different mode of operation of the circuit specifiable, each one favorable Efficiency of the circuit allows.

In In another advantageous embodiment, the potential shifter comprises a Potentialschieberwiderstand, with its first end with the heightened Auxiliary potential is coupled and with its second end with a Potential shift switch is coupled. The potential slide switch is also coupled to the output of the power inverter. Of the Potential shift switch is dependent on the pulse width modulated Drive signal or the differential pulse signal and switched on switched off. The switching signal is at a tap between the potential slide resistor and the potential slide switch available depending on the inhibit signal when the potential shifter is activated. The potential slider is activated when the potential slide switch is switched on is. The advantage is that the circuit arrangement thereby a has a simple structure and only a few components are required. Furthermore, the switching signal can only be generated if the potential shifter is activated by the inhibit signal. This allows the upper switch only be switched on when the lower switch is switched off is. The control of the upper and the lower switch are so reliable locked against each other.

In a further advantageous embodiment of the circuit arrangement For example, an output of the potential shifter is coupled to an upper pre-drive switch. The upper pre-driver switch is thereby the switching signal supplied to the Switching on or off the upper pre-driver switch depending on the switching signal. The upper pre-driver switch is electrically in between the increased auxiliary potential and an input of the power driver. A lower one The pre-driver switch is electrically connected between the input of the power driver and a reference potential arranged. The lower pre-driver switch is coupled to the output of the power inverter. The lower one Predriver switch is characterized the blocking signal can be supplied to turn or turning off the lower pre-driver switch depending on the blocking signal. The advantage is that the circuitry has a has a simple structure and only a few components are required. The upper switch is fast and reliable through the upper pre-driver switch and the power driver switched on by the switching signal. Further, the upper switch fast and reliable can be switched off by the lower pre-driver switch depending on the blocking signal. This ensures that the top switch safely turned off when the bottom switch is turned on becomes.

In a further advantageous embodiment of the circuit arrangement is between a control port and a tax reference port each of the upper switch and / or the lower switch Compensating capacitor provided. High-frequency vibrations, in particular by the switching operations of the upper and / or lower Switch can arise, can optionally via a miller capacity of the upper and / or lower switch on the control terminal of the respective switch turned off and to an undesirable, parasitic Turn on this switch. By providing the compensation capacitor, the high-frequency Vibrations are compensated or reduced so much that the unwanted, parasitic Turn on reliably is prevented. As a result, the circuit arrangement is particularly reliable and reliable. The control terminal is in particular a gate terminal or a basic connection of the respective switch. The tax reference terminal is in particular a source terminal or an emitter terminal of the respective switch.

embodiments The invention are explained below with reference to the schematic drawings. It demonstrate:

1 a block diagram of a circuit arrangement,

2 a first embodiment of the circuit arrangement as a half-bridge driver in a buck converter arrangement,

3A a time characteristic of an output voltage and an output current in a first direction of the output current,

3B a time characteristic of the output voltage and the output current in a second direction of the output current,

4 a second embodiment of the circuit arrangement as a half-bridge driver in the buck converter arrangement,

5 a third embodiment of the circuit arrangement as a half-bridge driver in the buck converter arrangement,

6 a first variant of a fourth embodiment of the circuit arrangement as a half-bridge driver in the buck converter arrangement,

7 an application example of the first variant of the fourth embodiment,

8th a second variant of the fourth embodiment of the circuit arrangement as a half-bridge driver in the buck converter assembly and

9 A fifth embodiment of the circuit arrangement as a half-bridge driver in the buck converter.

elements same construction or function are cross-figurative with the same Provided with reference numerals.

A circuit arrangement, which is designed in particular as a half-bridge driver for driving a half-bridge with an upper switch X2 and a lower switch X3, has a power inverter INV (FIG. 1 ). The upper switch X2 and the lower switch X3 are in a half-bridge center node acting as a node 10 is referred to, coupled together and are arranged electrically in series with each other between a supply potential VCC and a reference potential GND. The reference potential GND is preferably a ground potential. A voltage between the supply potential VCC and the reference potential GND is for example about twelve volts, but may also be larger or smaller.

The upper switch X2 and the lower switch X3 are preferably field-effect transistors, in particular MOS field-effect transistors. Preferably, the upper and lower switches X2, X3 already have a low gate-source voltage ei NEN low on resistance, for example, about 26 milliohms at a gate-source voltage of about 4.5 volts. However, the upper switch X2 and the lower switch X3 can also be designed differently.

The power inverter INV input side, a pulse width modulated drive signal PWM can be fed. The pulse width modulated drive signal PWM is clocked, for example, with a clock frequency of 300 kilohertz, but may also be clocked at a higher or lower clock frequency. In particular, the clock frequency may be more than one megahertz. The power inverter INV inverts the pulse-width-modulated drive signal PWM and sets this output low-impedance at a node 18 ready as a blocking signal LSIG. Preferably, an output resistance of the power inverter INV is less than 100 ohms. It is particularly advantageous if the output resistance is less than ten ohms. For example, the output resistance is about 1 to 10 ohms. However, the output resistance may be lower or higher. The pulse width modulated drive signal PWM is related to the reference potential GND and has, for example, an amplitude of about five volts. However, the amplitude of the pulse width modulated drive signal PWM may also be greater or less than five volts.

Of the Power inverter INV is electrically connected between an auxiliary potential VDD and the reference potential and switches its output to an H level when the pulse width modulated drive signal PWM has an L level, and switches its output to one L level when the pulse width modulated drive signal PWM a H level has. For example, the auxiliary potential VDD is approximately five volts. The H level is then, for example, about five Volt and the L level is about zero volts. However, the auxiliary potential VDD and the high level can also bigger or less than five Be volts.

Of the Output of the power inverter INV is connected to a control terminal the lower switch X3 coupled. Is the lower switch X3 as Field effect transistor formed, then is a threshold voltage of the lower switch X3 so to choose that is smaller than the H level of the inhibit signal LSIG to a safe switching on of the lower switch X3 in the presence to ensure the H-level of the lock signal LSIG. Electric between the output of the power inverter INV and the control terminal of the lower switch X3 is preferably a one-way deadtime TDEAD1 provided having a deadtime TDEAD2, which in a direction of the output of the power inverter INV to the control terminal of the lower switch X3 acts. Furthermore, the one-way deadtime TDEAD1 includes a bypass diode X13, the deadtime TDEAD2 in one direction from the control terminal of the lower switch X3 to the output of the power inverter INV bridged. Thereby is the lower switch X3 at a change of the lock signal LSIG delayed from the L level to the H level by the deadtime TDEAD2 switchable and in case of a change of the inhibit signal LSIG from the H level to the L level substantially instantaneously switched off. However, the one-way deadtime TDEAD1 can also be designed differently be.

The Circuit arrangement further comprises a potential shifter LSHIFT, the dependent from the pulse width modulated drive signal PWM on to an increased auxiliary potential VEE related switching signal SSIG generates to turn on the upper switch X2. The potential shifter LSHIFT is the pulse width modulated Activation signal PWM or a differential pulse signal DSIG can be supplied. The Differential pulse signal DSIG is at one clock of the pulse width modulated Actuator signal PWM and is dependent, for example the pulse width modulated drive signal PWM or a clock signal of the pulse width modulated drive signal PWM generated. The potential slider LSHIFT is further connected to the output of the power inverter INV coupled, that the potential shifter LSHIFT depending on the lock signal LSIG can be activated and deactivated. For example, the potential slider LSHIFT activated when the inhibit signal LSIG has the L level and deactivated when the inhibit signal LSIG has the H level. The switching signal SSIG is generated depending on the pulse width modulated Drive signal PWM or the differential pulse signal DSIG when the Potential slide LSHIFT is activated by the blocking signal LSIG. The switching signal SSIG is not generated when the potential shifter LSHIFT is disabled.

The circuitry further includes a power driver DRIV that electrically connects between the boosted auxiliary potential VEE and the node 10 is arranged. The output driver DRIV is output coupled to a control terminal of the upper switch X2 for low-impedance driving of the upper switch X2. On the input side, the power driver DRIV is coupled to an upper and a lower pre-drive switch X1, X9, which are arranged in series with one another electrically between the increased auxiliary potential VEE and the reference potential GND. A control terminal of the upper pre-driver switch X1 is coupled to the output of the potential shifter LSHIFT. The control connection of the upper predriver switch X1 can thus be supplied with the switching signal SSIG.

Depending on the switching signal SSIG, the upper pre-driver switch X1 turns on and rises through the input of the power driver DRIV to a high potential to the increased auxiliary potential VEE. The power driver DRIV is designed to switch on the upper switch X2 by raising a potential above the turn-on threshold of the upper switch X2 on the output side of the power driver DRIV. The upper pre-driver switch X1 is turned off by deactivating the potential shifter LSHIFT. However, the upper pre-driver switch X1 can be switched off, for example, even when the potential shifter LSHIFT is activated, if no differential pulse is supplied to the potential shifter LSHIFT.

One Control terminal of the lower pre-driver switch X9 is connected to the output coupled to the power inverter INV. The control terminal of the lower Predriver switch X9 is therefore the blocking signal LSIG fed. has the inhibit signal LSIG is at the H level, then the lower pre-driver switch is turned on X9 and leads the input of the power driver DRIV thereby a low potential to, which corresponds approximately to the reference potential GND. The power driver DRIV is configured to turn off the upper switch X2 thereby that the output side of the power driver DRIV the potential below the switch-on threshold of the upper switch X2 is lowered. Of the Lower pre-driver switch X9 is off when the inhibit signal LSIG has the L level.

By a boosting diode X10 and a boosting capacitor C2, a boosting circuit is formed, which may also be referred to as a boosting circuit. The boosting capacitor C2 is between a node 4 to which the increased auxiliary potential VEE is assigned, and the node 10 arranged. The boosting diode X10 is electrically arranged between the auxiliary potential VDD and the boosted auxiliary potential VEE. The boosting capacitor C2 is charged via the boosting diode X10 to a boosting voltage approximately equal to the auxiliary potential VDD minus a forward voltage of the boosting diode X10 when the upper switch X2 is turned off and the lower switch X3 is turned on. The knot 10 then has approximately the reference potential GND. The increased auxiliary potential VEE is formed from a current potential of the node 10 plus the boost voltage of the boost capacitor C2. If the upper switch X2 is turned on and the lower switch X3 is off, then the node points 10 about the supply potential VCC on. Accordingly, the increased auxiliary potential VEE is then approximately the supply potential VCC plus the boosting voltage of the boosting capacitor C2. By suitable dimensioning of the boosting capacitor C2, it can be ensured that the control terminal of the upper switch X2 has a sufficiently high voltage with respect to the node 10 can be supplied to keep the upper switch X2 turned on, as long as the switching signal SSIG is generated. Instead of the booster circuit, however, for example, a voltage source can be provided which provides the required increased auxiliary potential VEE with respect to the reference potential GND.

2 shows a first embodiment of the circuit arrangement as a half-bridge driver in a buck converter arrangement. The pulse width modulated drive signal PWM is generated by a signal source V2, which has a first source internal resistance R5. The signal source V2 is formed for example by a gate output. The source internal resistance R5 is, for example, about 400 ohms. The pulse width modulated drive signal PWM is decoupled via the power inverter INV, which is formed by a first and a second inverter transistor X11, X12. The power inverter INV has the task to provide the required high current pulses for driving the lower switch X3 and to logically invert the pulse width modulated drive signal PWM. The lower switch X3 forms a synchronous rectifier. The required current pulses for driving the lower switch X3, for example, about one ampere, but may also be larger or smaller. It is provided that the half-bridge center node, that is, the node 10 , which has low potential at about the reference potential GND when the pulse width modulated drive signal PWM has the L level, and the node 10 has the high potential at approximately the supply potential VCC when the pulse width modulated drive signal PWM has the H level. However, the circuit arrangement can also be designed so that there is a reverse assignment of the levels and potentials.

The Auxiliary voltage VDD is provided by an auxiliary voltage source V4, which has a second source internal resistance R8. A supply line the auxiliary voltage source V4 to the circuit arrangement further comprises a first line inductance L2 on. To avoid electrical vibrations is a first Block capacitor C5 provided, which has a parasitic resistance R10 has. The first blocking capacitor C5 is electrically connected between the auxiliary potential VDD and the reference potential GND arranged. the Power inverter INV, the auxiliary voltage VDD by another Auxiliary voltage source V10 can be provided, however, the Power inverter INV, the auxiliary voltage VDD also by the auxiliary voltage source V4 be provided.

The supply potential VCC is provided by a supply voltage source V5. A supply line of the supply voltage source V5 to the upper switch X2 has a second line inductance L3 and a line resistance R9. In order to avoid electrical oscillations, a second blocking capacitor C6 is furthermore provided electrically between the supply potential VCC and the reference potential GND.

For operation as a buck converter, an inductance L1 is provided, which is electrically connected between the half-bridge center node, that is, the node 10 , and a load is arranged. The load is constituted by a load current source I1 and a load resistor R11 electrically connected in parallel with the load current source I1. The load is electrically arranged between the inductance L1 and the reference potential GND. Furthermore, a capacitor C3 is arranged electrically parallel to the load for operation as a step-down converter.

The potential shifter LSHIFT is formed by a voltage divider and by a potential slide switch X8. The voltage divider is electrically connected between the node 4 and the potential slide switch X8, and is formed by first and second voltage dividing resistors R1, R2. For example, a resistance value of the first voltage dividing resistor R1 is about 200 ohms, and a resistance value of the second voltage dividing resistor R2 is about 470 ohms, for example. However, the voltage divider can also be designed as a capacitive voltage divider. Furthermore, it is also possible to dispense with the first voltage divider resistor R1, in particular if it is ensured that a maximum between the control terminal of the predriver switch X1 and the node 4 prevailing voltage is so low that it can not lead to damage to the Vortreiberschalters X1. In particular, the first voltage divider resistor R1 can be dispensed with if the predriver switch is designed as a bipolar transistor. The second voltage divider resistor R2 may also be referred to as a potential shifter resistor.

Of the Potential shift switch X8 is preferably by a field effect transistor whose source terminal is connected to the output of the power inverter INV is coupled. The control connection of the potential slide switch X8 is coupled to the input of the power inverter INV. Of the Control connection of the potential slide switch X8 is by a Gate terminal of the potential slide switch X8 formed. A midpoint tap of the Voltage divider is connected to the control terminal of the upper pre-driver switch X1 coupled for feeding of the switching signal SSIG. The switching signal SSIG falls as a switching voltage across the second voltage divider resistor R2 from when the potential slide switch X8 is turned on and the inhibit signal is at the L level. The Switching signal SSIG is thereby related to the increased auxiliary potential VEE.

Of the Predriver switch X1 is preferably a p-channel field effect transistor is formed and the control terminal of Vortreiberschalters X1 through a gate terminal of the p-channel field effect transistor educated. The upper pre-driver switch X1 therefore turns on when the switching voltage over the second voltage divider resistor R2 drops, that is, the switching signal SSIG is generated. Accordingly, the upper pre-driver switch X1 is turned off when the switching signal SSIG is not generated.

The Switch signal SSIG, however, can only be generated when the Potential slide switch X8 is turned on, that is, the potential shifter LSHIFT is activated by the lock signal LSIG at the L level. Thereby is a current flow through the voltage divider possible, the switching voltage to Consequence, which is to turn on the upper Vortreiberschalters X1 leads.

Between the upper and lower pre-driver switches X1, X9 is a limiting resistor R3 provided, for example, a resistance value of about 22 Ohm has. For the case of a temporary overlapping Turning on the upper and lower pre-driver switches X1, X9 a possible short-circuit current through them by the limiting resistor R3 on a harmless Value limited. The limiting resistor R3 is not mandatory, elevated however the reliability and the reliability of the circuit.

The power driver DRIV is formed by a first driver transistor Q1 and a second driver transistor Q2, which are formed as bipolar transistors. A respective base terminal of the first and second driver transistors Q1, Q2 is connected to a node 7 coupled, which is formed by a drain terminal of the lower Vortreibertransistors X9, which is coupled to the limiting resistor R3. A respective emitter terminal of the first and second driver transistors Q1, Q2 is coupled to the control terminal of the upper switch X2. A collector terminal of the first driver transistor Q1 is connected to the node 4 and a collector terminal of the second driver transistor Q2 is connected across a block diode X5 to the node 10 coupled. Block diode X5 prevents current flow from the node 10 towards the DRIV power driver.

The one-way dead-band TDEAD1 is constituted by a delay transistor X7 and a variable resistor R7. The delay transistor X7 is formed by another p-channel field effect transistor whose drain terminal forms an input terminal of the one-way dead time TDEAD1 and whose source terminal constitutes an output terminal of the one-way dead time TDEAD1. An unillustrated substrate diode of the delay transistor X7 forms the bypass diode X13. The adjustment resistor R7 is electrically arranged between a control terminal of the delay transistor X7 and the reference potential GND. The control terminal of the delay transistor X7 is formed by a gate terminal of the further p-channel field effect transistor.

By an unillustrated, so-called Miller capacity further p-channel field effect transistor connected between the drain terminal and the gate terminal of the further p-channel field-effect transistor is formed, a negative feedback is effected, the output side to a tilting an input side, rising edge of the blocking signal LSIG leads.

Thereby increases a gate-source voltage of the lower switch X3 slowed down so that the threshold voltage of the lower switch X3 against the rising edge of the blocking signal LSIG delay is exceeded and the lower switch X3 thus delayed turns. With respect to the rising edge of the inhibit signal LSIG, the lower switch X3 is switched on only after expiry a dead time, which is represented by a value of Miller capacity and a Resistance value of the adjustment resistor R7 is predetermined. By Selection of the resistance value of the adjustment resistor R7 is the dead time very easy to specify. The resistance of the adjustment resistor R7 is for example, about 1.24 kilo ohms, and the dead time is, for example about 100 nanoseconds. A charge on the gate terminal of the bottom However, switch X3 can over the substrate diode of the delay transistor X7 are discharged quickly when the lock signal LSIG the L level having. The switching off of the lower switch X3 thus takes place essentially instantaneous. The dead time until the lower switch X3 is switched on must be be sized so that it is larger as a period of time for switching off the upper switch X2 is required. The lower Switch X3 only switches on when the upper switch is switched off.

Does the potential at the node increase? 10 quickly, for example, by turning on the upper switch X2, a current can flow to the gate terminal of the lower switch X3 via a Millerkapazität not shown of the lower switch X3. This current is derived in principle by the power inverter INV to the reference potential GND. However, due to the distance between the power inverter INV to the gate terminal of the lower switch X3 and the associated line inductance of the current can, if appropriate, not fast enough to the reference potential GND are derived. As a result, the gate-source voltage of the lower switch X3 may rise and possibly lead to parasitic switching on of the lower switch X3. However, this may cause the upper and lower switches X2, X3 to be turned on simultaneously. By providing a compensation capacitor C4 directly between the gate terminal and the source terminal of the lower switch X3, the voltage increase of the gate-source voltage of the lower switch X3 can be reduced so as to avoid the undesired switching-on of the lower switch X3.

Accordingly, in the presence of a negative output current IOUT in the node 10 Turn on the lower switch X3 also lead to an unwanted, parasitic turning on the upper switch X2. By providing a further, not shown compensation capacitor C4 between the gate terminal and the source terminal of the upper switch X2 can be avoided according to the unwanted switching on of the upper switch X2.

In the following, four different operating situations are explained. In a first operating situation, the switch-off operation of the lower switch X3 and the switch-on operation of the upper switch X2 are considered in the case of a positive output current IOUT, that is to say for a current from the node 10 out through the inductor L1 and a non-latching buck converter operation.

Of the lower pre-driver switch X9 stops the upper switch X2 is turned off until the gate-source voltage of the lower switch X3 corresponding to the blocking signal LSIG the threshold voltage of the lower pre-driver switch X9 has fallen below. This threshold voltage is for example, about a volt. The lower switch X3 then leaves already no longer high current flow. By the L level of the blocking signal On the one hand, LSIG thus becomes the gate-source voltage of the lower switch X3 decreases, so that the lower switch X3 turns off, and on the other hand the activation of the upper switch X2 for switching on the upper one Switch X2 enabled. The blocking signal LSIG thus locks the control of the upper and lower switches X2, X3 against each other.

For the upper switch X2 and the lower switch X3 different transistor types with different parasitic capacitances can be used. In addition, compensation capacitors C4 can also be used as external gate sour ce capacitors are provided. These parasitic or additional capacitances and other parasitic capacitances, which are formed for example by contamination of the circuit arrangement or by moisture on the circuit arrangement, have only a small influence on the function of the circuit arrangement. This is achieved essentially by the low-resistance structure of the circuit arrangement and in particular by the low-resistance provision of the blocking signal LSIG at the output of the power inverter INV. As a result, a switch-off time of the lower switch X3 is largely independent of the capacitances of the circuit arrangement on the blocking signal LSIG recognizable, in particular independent of capacitances in a range of the lower Vortreiberschalters X9 and the potential slide switch X8. The detection of the switch-off of the lower switch X3 for the release of the upper switch X2 is therefore extremely reliable.

Shortly before the lower pre-driver switch X9 turns off, the potential slide switch X8 turns on. As a result, a current predetermined by the voltage divider flows through the first and second voltage divider resistors R1, R2. This current causes the voltage drop across the second voltage divider resistor R2. The signal related to the reference potential GND in the node 18 This way it will be on the node 4 converted switching signal SSIG implemented.

One Voltage rise over the second voltage divider resistor R2 is optionally through parallel capacities delayed for example, by parasitic capacities of the upper pre-driver switch X1 are formed. By this delay is the lower pre-driver switch X9 already turned off when the upper pre-driver switch X1 turns on, so that through the upper and the lower Vortreiberschalter X1, X9 no cross-flow flows. however may possibly due to the influence of component tolerances Such transient occur for a short time, but then by the limiting resistor R3 is limited.

The source impedance in the node 7 is further reduced via the downstream, non-inverting complement driver, which forms the DRIV power driver. The gate terminal of the upper switch X2 is quickly charged via the power driver DRIV, but delayed by the potential shifter LSHIFT with respect to the pulse width modulated drive signal PWM. However, the protection against the overlapping switching on of the upper and lower switches X2, X3 by the locking by the blocking signal LSIG also acts independently of a signal passage time of the potential shifter LSHIFT.

If, before switching on the upper switch X2, a positive output current IOUT flows through the inductance L1 in the direction of the capacitor C3, the lower switch X3 first switches off. The output current IOUT substantially continues to flow through a substrate diode of the lower switch X3, which forms a lower freewheeling diode D3. An output voltage UOUT between the potential at the node 10 and the reference potential GND thereby jumps to a forward voltage of the lower freewheeling diode D3, which is for example about one volt. The upper switch X2 then turns on hard, that is, the potential at the node 10 quickly rises to about the supply potential VCC.

In a second operating situation, the turn-off operation of the lower switch X3 and the turn-on operation of the upper switch X2 at a negative output current IOUT from the inductance L1 into the node 10 looked into it. This operating situation occurs, for example, in a lulling buck converter operation or in a Class D amplifier. In this operating situation, too, the protection explained above acts against the overlapping switching on of the upper and lower switches X2, X3.

However, the output voltage UOUT does not increase until the upper switch X2 is switched on, but already during the switch-off of the lower switch X3. The reason for this is that the negative output current IOUT causes charging of parasitic and elementary capacitances that are connected to the node 10 are connected. The output voltage UOUT therefore increases linearly. After charging the capacitances, the negative output current IOUT substantially flows through a substrate diode of the upper switch X2, which forms an upper freewheeling diode D2 when the upper switch X2 is still off. Due to the voltage drop across the upper freewheeling diode D2 corresponds to the potential at the node 10 about the supply potential VCC plus the forward voltage of the upper freewheeling diode D2, which is about one volt.

The signal delay of the potential shifter LSHIFT is preferably dimensioned by suitably selecting the resistance values of the first and second voltage divider resistors R1, R2 such that the upper switch X2 does not switch on until the negative output current IOUT has flowed through the upper freewheeling diode D2 for a period of time sufficient, the capacity at the node 10 through the negative output current IOUT so far that the potential at the node 10 close to the supply potential VCC, for example, down to about one to two volts. The upper switch X2 can then turned on particularly low loss who the. This is also referred to as soft-switching or soft-switching.

Parasitic capacities, to Example by pollution or moisture, cause an additional signal delay in the potential slide LSHIFT and thus a longer conduction phase the upper freewheeling diode D2. Although this has a reduction of Overall efficiency of Tiefsetzstellers result. However, located The circuit arrangement so in a safe operating point. The overlapping Turning on the upper and lower switches X2, X3 will do so especially reliable prevented.

Even if the delay of the potential shifter LSHIFT would be very small, the overlapping switching on of the upper and lower switches X2, X3 by the inhibit signal LSIG reliable prevented. With very little delay of the potential slide LSHIFT canceled optionally the soft switching on of the upper switch X2.

In a third operating situation is the switch off the upper Switch X2 and the switch-on of the lower switch X3 at the positive output current IOUT in the non-latching buck converter operation considered. Also in this operating situation is by the blocking signal LSIG ensures that the upper and lower switches X2, X3 are not simultaneously are turned on.

The Rising edge of the blocking signal LSIG causes rapid switching on of the lower predriver switch X9 when its threshold voltage is exceeded is. The gate connection the lower switch X2 is over the power driver DRIV as well as over discharge the block diode X5 very fast. Because of the positive Output current IOUT decreases the output voltage UOUT by switching off the upper switch X2 quickly. The output current IOUT then flows essentially about the lower freewheeling diode D3 on. The lower switch X3 is still turned off because of the increase in the gate-source voltage of the lower Switch X3 through the delay transistor X7 and the adjustment resistor R7 is slowed down. The compensation capacitor C4 and the gate-source capacity of the lower Switch X3 will therefore be charged slowly and the lower switch X2 thereby delayed switched on. Due to the voltage drop across the lower freewheeling diode D3 is the output voltage UOUT is about -1 Volt. Due to the low output voltage UOUT the lower switch switches X3 soft, causing the output voltage UOUT to about zero volts is raised. The switching on of the lower switch X3 takes place therefore low loss.

For one reliable Operation of the circuit arrangement must be through the circuit appropriate choice of the respective threshold voltage to be designed so the lower pre-driver switch X9 is already on, before the gate-source voltage of the lower switch X3 reaches its threshold voltage. To the threshold voltage of the pre-driver switch X9 is lower choose as the threshold voltage of the lower switch X3.

In a fourth operating situation, the turn-off operation of the upper switch X2 and the turn-on operation of the lower switch X3 are considered at the negative output current IOUT. During the turn-off operation of the upper switch X2, the negative output current IOUT flows into the node 10 into it, the potential remains at the node 10 during turn-off of the upper switch X2 approximately at the supply potential VCC plus the forward voltage of the upper freewheeling diode D2. The upper switch X2 therefore turns off soft and low loss. The switching on of the lower switch X3 is delayed by the delay transistor X7 and the adjusting resistor R7. The lower switch X3 therefore turns on only hard after the upper switch X2 is turned off. The hard turning on of the lower switch X3 drops the potential at the node 10 approximately to the reference potential GND.

One Advantage of the circuit arrangement is that in all four operating situations, this means independently from the direction of the output current IOUT, the locking of the drive of the upper and lower switches X2, X3 by the inhibit signal LSIG is effective.

3A shows a time course of the output voltage UOUT at the negative output current IOUT. At a first time tA, the lower switch X3 turns off, thereby the output voltage UOUT rises rapidly from about zero volts to about the supply potential VCC plus about one volt, the upper freewheeling diode D3 conducts. At the second time tB, the upper switch X2 switches on softly, the output voltage UOUT thereby drops by about one volt to approximately the supply potential VCC. At a third time tC, the upper switch X2 switches off, the upper freewheeling diode D2 conducts and the output voltage UOUT rises again to approximately the supply potential VCC plus approximately one volt. After the dead time expires, the lower switch X3 turns on hard at a fourth time tD. The output voltage UOUT falls quickly to about zero volts.

3B shows correspondingly a time course of the output voltage UOUT at the positive output current IOUT. At a fifth time point tE, the upper switch X2 turns off and the output voltage UOUT falls quickly to about -1 volts, the lower freewheeling diode D3 conducts. After the dead time has elapsed, the lower switch X3 switches on softly at a sixth instant tF and the output voltage UOUT rises to approximately zero volts. At a seventh point in time tG, the lower switch X3 switches off, the lower freewheeling diode D3 conducts and the output voltage drops to about -1 volt. At an eighth time tH, the upper switch X2 turns on hard. As a result, the output voltage UOUT rises rapidly to approximately the supply potential VCC.

4 shows a second embodiment of the circuit arrangement, which differs from the first embodiment in that the delay transistor X7 and the adjusting resistor R7 are replaced by a charging resistor R12 and the separately formed bypass diode X13. The charging resistor R12 causes slower charging of the gate-source capacitance of the lower switch X3 and the compensation capacitor C4 when the rising edge of the latch signal LSIG occurs. As a result, the lower switch X3 is switched on with a corresponding delay. By suitable choice of the resistance value, for example about ten ohms, the desired dead time can be specified. The circuit arrangement is so very simple and inexpensive to produce.

5 shows a third embodiment of the circuit arrangement, which differs from the first embodiment in that the one-way deadtime TDEAD1 and the compensation capacitor C4 are not required. The lower switch X3 is replaced by a freewheeling diode D1, that is, the synchronous rectifier function of the lower switch X3 is eliminated. This circuit is particularly simple and inexpensive to produce.

6 shows a first variant of a fourth embodiment of the circuit arrangement, which differs from the first embodiment in that the control terminal of the potential shifter switch X8 is not coupled to the input of the power inverter INV, the control terminal of the potential shifter switch X8 so the pulse width modulated drive signal PWM is not supplied, but the control terminal of the potential shifter switch X8 is coupled to a differential pulse source V11 through which the differential pulse signal DSIG is supplied to the control terminal of the potential shifter switch X8. With each differential pulse, the gate-source capacitance of the upper switch X2 is charged when the inhibit signal LSIG simultaneously has the L level. Due to the pulsed activation of the potential slide switch X8, a current flows through the voltage divider of the potential shifter LSHIFT only for a very short period of time of the differential pulse. As a result, only small losses occur in the potential shifter LSHIFT and an energy requirement of the circuit arrangement is thereby reduced. Furthermore, the circuit arrangement thereby has a higher efficiency. This allows in particular a low-loss operation at high supply potential VCC.

7 shows an application example of the first variant of the fourth embodiment of the circuit arrangement. Two or even more than two of the circuit arrangements, for example in each case in a step-down converter arrangement for respectively different voltages, are operated synchronously with one another. The buck converter assemblies are each supplied to the common differential pulse signal DSIG. Furthermore, the respective step-down converter arrangement is supplied with the respective pulse width modulated drive signal PWM, for example a first pulse width modulated drive signal PWM1 for generating a voltage of five volts or a second pulse width modulated drive signal PWM2 for generating a voltage of 3.3 volts. By synchronously operating the buck converter assemblies, unwanted interference between them can be avoided.

8th shows a second variant of the fourth embodiment of the circuit arrangement in which the differential pulse signal DSIG is generated by a differentiating circuit of the pulse width modulated drive signal PWM. The differentiating circuit comprises a differentiating capacitor C7 and a differentiating resistor R13. The differentiating capacitor C7 is supplied with the pulse-width-modulated drive signal PWM at a first terminal. The second terminal of the differentiating capacitor C7 is coupled to the reference potential GND via the differentiating resistor R13. Furthermore, a first inverter X14 and a second inverter X15 are provided electrically in series one behind the other, via which the second terminal of the differentiating capacitor C7 is coupled to the control terminal of the potential shifter switch X8. The first and second inverters X14, X15 ensure that the differential pulse signal DSIG is supplied to the control terminal of the potential shifter switch X8 in a low-resistance manner in order to avoid signal distortions.

9 shows a fifth embodiment of the circuit arrangement, which differs from the first embodiment in that the control terminal of the delay transistor X7 via the adjustment resistor R7, a control signal CSIG is supplied. The control signal CSIG is generated, for example, by a control signal source V12, which depends on a desired switching state of the delay transistor X7 provides either an L level or an H level. In the presence of the L level, the delay transistor X7 is turned on and thereby activated. The circuit arrangement then corresponds in its function to the first embodiment of the circuit arrangement. However, if the H level is present, then the delay transistor X7 is turned off and thereby deactivated. The lower switch X3 then remains off regardless of a course of the blocking signal LSIG. The circuit arrangement then corresponds in its function to the third embodiment, that is, only the substrate diode of the lower switch X3 or the lower free-wheeling diode D3 is used. The synchronous rectifier function of the lower switch X3 is eliminated. Depending on the control signal CSIG, the synchronous rectifier function of the lower switch X3 can thus be activated or deactivated simply and dynamically during the operation of the circuit arrangement.

The Use of the synchronous rectifier function of the lower switch X3 is particularly advantageous when the output current IOUT is large in magnitude, for Example larger than about one amp. In amount small Output current IOUT, for example less than about one ampere however, the operation without the synchronous rectifier function of the lower one Switch X3 advantageous. By appropriate activation or deactivation of the synchronous rectifier function of the lower switch X3 the control signal CSIG, the circuit arrangement each with a Great Efficiency can be operated.

The Insensitivity of the circuit to parasitic influences such as moisture and other creeping distances was experimentally in a water bath with proven distilled water. The circuit showed even with the occurring high parasitic capacitances no loss of function. In particular, an overlapping occurred Turning on the upper and lower switches X2, X3 does not turn on. It showed only a high load of Leistungsinverters INV, however, by suitable dimensioning of the power inverter INV can be countered. Due to this special reliability and reliability is the circuit arrangement in particular for the Use in motor vehicles particularly suitable. The circuit arrangement can for example consist of discrete components on an area of only about a square centimeter can be built. The circuit arrangement However, it can also be designed as an integrated circuit.

The Circuitry is exemplary as a half-bridge driver described in a buck converter arrangement. However, the circuitry is also usable in a boost converter or boost converter arrangement or in a Class D amplifier. Furthermore, the circuit arrangement as a half-bridge driver for others Applications usable.

Claims (7)

Circuitry that includes - one Power inverter (INV), the input side of a pulse width modulated Activation signal (PWM) can be fed is and the output a blocking signal (LSIG) low impedance and inverse to the pulse width modulated drive signal (PWM), - a potential slide (LSHIFT), the input side, the pulse width modulated drive signal (PWM) or a differential pulse signal (DSIG) can be fed, which from the pulse width modulated Trigger signal (PWM) is derived, and depending on the lock signal (LSIG) can be activated and deactivated and the output side, a switching signal (SSIG), which refers to an increased auxiliary potential (VEE) depends on supplied from the input side pulse width modulated drive signal (PWM) or differential pulse signal (DSIG), if the potential shifter (LSHIFT) is blocked by the blocking signal (LSIG) is activated, - one Power Driver (DRIV), the output side with an upper switch (X2) can be coupled to control the upper switch (X2) and the depending on the switch signal (SSIG) turns on the upper switch (X2) and which turns off the upper switch (X2) when the potential shifter (LSHIFT) is deactivated by the inhibit signal (LSIG). Circuit arrangement according to Claim 1, which has a one-way deadtime element (TDEAD1) comprising the input coupled to the power inverter (INV) is and the input side, the blocking signal (LSIG) can be fed and the output side with a lower switch (X3) coupled is for driving the lower switch (X3) and depending on a first parameter value of the inhibit signal (LSIG) the lower switch (X3) delayed turns on and depends from a second parameter value of the inhibit signal (LSIG) the lower Switch (X3) off. Circuit arrangement according to Claim 2, in which - the one-way dead-time element (TDEAD1) comprises a delay transistor (X7) and an adjustment resistor (R7), - the adjustment resistor (R7) is connected to a control terminal of the delay transistor (X7), - an input terminal of the delay transistor (X7) forms an input of the one-way dead-time member (TDEAD1), - an output terminal of the delay transistor gate (X7) forms an output of the one-way dead time element (TDEAD1) and - a dead time of the one-way dead time element (TDEAD1) is predetermined depending on a Miller capacitance of the delay transistor (X7) and the adjustment resistor (R7). Circuit arrangement according to claim 3, wherein a Control signal (CSIG) via the adjustment resistor (R7) to the control terminal of the delay transistor (X7) can be fed is to enable or disable the one-way deadtime (TDEAD1) dependent from the control signal (CSIG). Circuit arrangement according to one of the preceding claims, in of the - of the Potential shifter (LSHIFT) comprises a potential shifter resistor, which coupled with its first end with the increased auxiliary potential (VEE) is and with its second end with a potential slide switch (X8) is coupled, - of the Potential shift switch (X8) with the output of the power inverter (INV) is coupled, - of the Potential slide switch (X8) depending on the pulse width modulated Activation signal (PWM) or the differential pulse signal (DSIG) can be switched on and can be switched off and - the Switching signal (SSIG) at a tap between the potential slide resistor and the potential slide switch (X8) can be provided depending on the Blocking signal (LSIG) when the potential shifter (LSHIFT) is activated is, with the potential shifter (LSHIFT) is activated when the Potential slide switch (X8) is switched on. Circuit arrangement according to one of the preceding claims, in the - one Output of the potential shifter (LSHIFT) with an upper pre-driver switch (X1) is coupled, - the upper pre-driver switch (X1) thereby the switching signal (SSIG) can be fed to turn on or turn off the upper pre-driver switch (X1) dependent from the switching signal (SSIG), - the upper pre-driver switch (X1) electrically between the raised Auxiliary potential (VEE) and one input of the power driver (DRIV) is arranged - one lower pre-driver switch (X9) electrically between the input of the power driver (DRIV) and a reference potential (GND) arranged is and - of the Lower pre-driver switch (X9) to the output of the power inverter (INV) and the lower pre-driver switch (X9) thereby the blocking signal (LSIG) can be fed is for switching on or off the lower pre-driver switch (X9) from the inhibit signal (LSIG). Circuit arrangement according to one of the preceding claims, in between a control port and a tax reference port the upper switch (X2) and / or the lower switch (X3) respectively a compensation capacitor (C4) is provided.