DE102006027383A1 - A method for damping an acoustic noise and arrangement for carrying out the method - Google Patents

Abstract

The invention relates to a method and an arrangement for damping an acoustic noise. The method is characterized in that the noise is acoustically detected by a microphone device with a conversion into an interference signal, then a synchronization of a phase-locked loop takes place on the interference signal, due to the interference signal generated by the phase-locked loop an anti-noise signal and acoustically in the environment destructive interference with the acoustic noise is emitted. The arrangement for attenuating an acoustic noise is characterized by a noise microphone (Mic1) for acoustic recording of noise and conversion into an input signal (x (n)), connected to the Störsignalmikrophone programmable control and processing unit (10), an audio amplifier unit (NF -PA) with a connected, an acoustic anti-noise signal (7) radiating anti-noise speaker (Sp2) and a Errorsignalmikrofon (Mic2) for detecting a residual error signal (e (n)) in connection with the control and processing unit.

Description

The The invention relates to a method for damping an acoustic noise according to the preamble of claim 1 and an arrangement for carrying out the Method according to the preamble of claim 13.

to damping of acoustic noise, for noise reduction and for reasons of hearing protection passive sound insulation, for example, insulated headphone type Earmuffs, Verdämmungen and the like means. Such sound insulation However, often enough, they are not enough or not enough in one for that install or install the intended area, dampen the Often enough, sound only in an insufficient degree or bring other disadvantages with them, such as an undesirable thermal insulation, a disadvantageous increase in mass or - im Trap the earmuffs - one on Duration uncomfortable wearing.

One Example for this is the sound insulation in an airplane cockpit. For reasons Mass savings in ultra-low and single engine aircraft has to be an elaborate one soundproofing be dispensed with in the cockpit area. The ear protection against the engine and propeller generated sound is in this case exclusively by appropriate headphones with insulation realized. These headphones serve both the hearing protection, as well as understanding between pilot and ground station as well as the conversation between Pilot and copilot. Wearing such quite heavy and sweeping, headphone is highest in the long run uncomfortable and still does not quite eliminate the perceptible engine noise.

It The task, a procedure, now results from the above and an arrangement for damping an acoustic background noise specify, with targeted, space-saving and largely without passive insulation devices and materials acoustic noise and noise effectively steamed and even can be eliminated. The method or the arrangement should little effort can be applied to the place where the noise to eliminate or dampen is. It should as possible be universally applicable, i. the method or the arrangement should make it possible preferably all frequencies of the noise effectively below a convenient intensity threshold to press and yourself on the existing in background noise Set and adjust frequencies.

The Task is with a method for damping acoustic noise with the features of claim 1 and an arrangement for damping acoustic interference noise solved with the features of claim 13. The subclaims include appropriate or advantageous embodiments of the method or the arrangement.

The Process according to the invention is characterized characterized in that the background noise acoustically over a microphone device with a conversion into an interference signal is detected. Subsequently there is a synchronization of a phase-locked loop on the interference signal. This then generates an anti-noise signal that is acoustically in the environment for destructive interference with the acoustic noise is delivered.

basic idea the method according to the invention So it is, the background noise in an active manner with an anti-noise signal for destructive interference to bring and thus extinguish or at least to dampen sustainably. For this purpose, the noise is first recorded by means of the microphone device and in an electronic interference signal reshaped. This time-periodic signal is then at a phase-locked loop. This generates an anti-siren signal, whose course of time is such that it coincides with the course of the interference signal destructively superimposed. The anti-noise signal is emitted acoustically into the environment and superimposed there with the acoustic noise, so in the field of noise and the anti-noise a mutual extinction of the sound in conjunction with a sustainable damping the sound intensity takes place. This overlay can in principle in all sound conducting media, ie in air, solids and Liquids, occur.

Of the Advantage of such a method lies in its flexibility and high-grade Adaptability. Due to the phase-locked loop exactly the frequencies filtered out of the acoustic interference signal, the muted Need to become. The anti-noise signal forms exactly the acoustic interference signal off and steams it by destructive interference under a certain intensity and volume. at a change the frequency response of the noise The phase-locked loop regulates itself to the present one new frequency of the noise one. Such an adaptation is in principle with passive sound insulation impossible.

The Method has the following expedient method steps on. The acoustic noise will over a jamming microphone detected acoustically and in a sinusoidal input signal for the phase-locked Implemented control loop. The phase-locked loop now generates over one Direct Digital Synthesis (DDS) a DDS signal. This DDS signal is converted into the anti-noise signal. The anti-noise signal is acoustically over an anti-noise speaker radiated. There is an acoustic overlay of the noise and the anti-noise. The overlay sound resulting from this overlay will over a Errorsignalmicrophone detected and converted into a Errorsignal. The error signal and the DDS signal then become a load mean Square Algorithm (LMS) coupled. The LMS algorithm generates then an anti-sound control signal. The anti-sound control signal leads one controlling feedback to converting the DDS signal into the anti-noise signal.

at this embodiment the antisound signal becomes dependent from the actual at the place of soundproofing have been continuously regulated. This applies in particular its phase position and frequency. This will be the rule for the regulation the Digital Direct Synthesis Dsa signal obtained from the phase-locked Control circuit and detected by the Errorsignalmikrofons error signal of overlay sound at the place of soundproofing used to stop the generation of the anti-noise signal from the DDS signal affect until the error signal falls below a defined level falls.

Of the phase-locked loop leads Frequency generation in the form of direct digital synthesis in Connection with a phase detector off. It will be through the direct digital synthesis an in-phase signal and a quadrature signal generated. Their phase error with respect to the input signal via the Phase detector determines. To minimize the phase error the frequencies of the in-phase signal and the quadrature signal by means of tuned to a control element. This procedure allows a independent Re-tuning of the phase-locked loop to that from the detection the Störschalls originating Input signal.

Conveniently, leads the Phase detector from a narrowband demodulation to the influence of interfering frequencies as comprehensive as possible to minimize. At an outside the capture range of the phase-locked loop lying input frequency of the input signal is a sweeping of the direct digital Synthesis performed until the presence of a signal on the phase detector.

Of the Phase detector is expediently is designed as a digitally averaging phase detector. It will the in-phase signal and the quadrature signal in each case a multiplier multiplied by the input signal. Subsequently, each takes place in one Filter member hiding additive mixing products with the generating each of a differential output signal and a division of the differential output signals in a divisional term. In an adjoining Arctan link an Actan calculation is performed with an output of the phase error.

The one filter element each is called a cascading low-pass decimation filter operated with at least two filter stages. Such filter members can be in a particularly simple way by programming to implement.

The Control element regulates the phase difference between the input signal and the DDS signal to zero. The control process is in Form of a D and P control process with a downstream I-control process, ie executed in the form of a PI control process.

For the mentioned switching between sweep and control mode, an amplitude detector is provided. Here are the amounts the output signals added after filtering and compared with a threshold value. At a value below the threshold, the sweep mode started. Otherwise the rule mode is called.

the LMS algorithm is expediently a second-way delay unit assigned. This generates one of the delay time between anti-noise speakers and error signal microphone corresponding delay for generating a phase difference between the phase-locked loop and the error signal. The delay unit considered the finite duration of the acoustic signal between the anti-noise loudspeaker and the error signal microphone and synchronizes the control operations of the LMS algorithm in their time with the propagation speed of the acoustic Signals in the silenced Room area.

In a first embodiment, the delay is achieved by regularly emitting a Di Rac pulse via the anti-noise loudspeaker picked up by the error signal microphone. The time between the generation of the Diracimpulses and the recording of the signal is measured as a delay time. In this embodiment, the actual transit time of a reference signal between the anti-noise loudspeaker and the error signal microphone is thus determined directly under the physical conditions of the spatial region.

at a second embodiment will the delay be over that Determining a phase difference between the phase-locked Run control circuit and the error signal using a phase detector. there is the error signal instead of the input signal at the corresponding Input of the phase detector on.

at a third embodiment will be the delay corrected out of a control tendency of the LMS algorithm. there will be at a wrong control tendency by a phase angle shifted by 90 ° Ausgangssig signals from the phase-locked loop on as long pass the LMS algorithm, until the control tendency shows the correct direction.

A Arrangement for damping an acoustic noise is characterized by a noise microphone for the acoustic recording of the noise and conversion into an input signal, one with the interfering signal microphone connected programmable control and processing unit, a Audio amplifier unit with a connected, emitting an acoustic anti-noise signal Anti-noise loudspeakers as well as an error signal microphone for recording a remaining error signal in conjunction with the control and Processing unit.

The programmable control and processing unit has a phase-locked Control circuit consisting of a phase detector, a controller and a direct Digital synthesis unit on. The phase-locked loop has an input lying at the phase detector for the from Noise signal microphone detected Input signal and one output each for one of the direct digital Synthesis unit generated in-phase signal and a quadrature signal for generating an anti-noise signal.

Farther the programmable control and processing unit has one Last Mean Square algorithm with the in-phase signal, the quadrature signal and the error signal as input quantities in feedback to actuators for the Generation of the anti-noise signal.

Farther the programmable control and processing unit has a delay element for delayed delivery of the in-phase and quadrature signals to the load-mean-square algorithm on.

The programmable control and processing unit can in particular as an evaluation board ADSP-BF533 EZ-KIT LITE with one out of one C / C ++ - compiler, a runtime library, an assembler, a linker and a Loader existing development software and a flash memory be educated. Such an evaluation board is suitable because of the available standing audio outs and inputs and the programmability-based device configuration is particularly good for the Implementation of the mentioned process steps and process components.

The method and the arrangement will be explained in more detail below with reference to exemplary embodiments. To clarify serve the 1 to 23 , The same reference numbers are used for identical or equivalent parts and method steps.

It shows:

1 a greatly simplified schematic representation of an arrangement for carrying out the method,

2 an exemplary system architecture of a BF533 EZ-KIT LITE,

3a an illustration of the structure of a Blackfin processor,

3b a representation of the structure of a Blackfin processor core,

4 an exemplary block diagram of an arrangement for carrying out the method,

5 an exemplary block diagram of a phase-locked loop for carrying out the method,

6a an exemplary plot of the DDS signals,

6b an exemplary plot of a DDS multiplied by the input signal,

7 an exemplary block diagram of a phase detector,

8th an exemplary block diagram of a filter cascade,

9 a representation of a selection of an output signal of the filter cascade,

10a a representation of an amplitude response of the filter cascade at the output 1,

10b a representation of an amplitude response of the filter cascade at the output 2,

11a a representation of an amplitude response of the filter cascade at the output 3,

11b a representation of the amplitude response of the filter cascade at the output 4,

12 a representation of an arrangement for bandpass measurement,

13 a representation of the amplitude response at the output 7,

14 a representation of the amplitude response at the output 7 with a center frequency of 1 kHz,

15a an exemplary plot of a low-pass filtered signal after multiplication of signals at frequencies of 1 kHz and 900 Hz,

15b an exemplary plot of low-pass filtered signals and resulting phase differences,

16 an exemplary signal flow diagram of a controller,

17a an exemplary plot of the frequency and phase control after a third filter stage,

17b an exemplary plot of the frequency and phase control after a seventh filter stage,

18 an exemplary embodiment of a modified microphone port,

19 an exemplary measuring arrangement for functional testing of the method according to the invention,

20 an exemplary spectrum with and without anti-noise at 60 Hz,

21a an exemplary spectrum with and without anti-sound at 750 Hz,

21b an exemplary spectrum with and without anti-sound at 1000 Hz,

22a an exemplary spectrum with and without anti-noise at 250 Hz,

22b an exemplary spectrum with and without anti-sound at 500 Hz,

23 an exemplary spectrum with and without anti-noise at 1500 Hz.

1 shows a greatly simplified schematic representation of an arrangement for carrying out the method, or a representation of the inventive concept. This consists in that of an interfering sound source 5 Outgoing and propagating in a medium Störschallwelle 6 with a sound wave emitted coherently in the medium and also propagating 7 to destructively interfere and thus wipe out. The coherent sound wave 7 is called an antisound. To generate the As an alternative, the background noise is acoustically detected by a microfleed microphone Mic1, converted into an electronic signal and a programmable control and processing unit 10 fed. This generates an anti-noise signal with the substantially same frequency and amplitude of the noise, the phase position but is shifted from that of the noise by 180 °, and outputs this signal via an anti-noise speaker Sp1. It is in the space between the noise source 5 and the anti-noise speaker Sp1 achieves an extinction or at least a considerable attenuation of the sound intensity and volume. An external programming unit 20 serves to influence the function of the control and processing unit 10 , in particular a programming, a parameter setting or the implementation of measurement routines for functional testing.

The programmable control and processing unit 10 can for example be designed by an evaluation board ADSP-BF533 EZ-KIT LITE. Such a board provides a development environment that can detect the noise signal and generate the anti-noise signal in a very simple manner. A basic system architecture of the development board is in 2 exemplified.

The development board has a Blackfin BF533 processor 21 as a CPU. This forms the core of the board. According to the technical specification, the processor is operated with a maximum core clock frequency of 600 MHz. The clock in the CPU is powered by an on-board oscillator 22 supplied with a clock signal of 27 MHz. The real-time clock 22a the CPU is equipped with a 32.768 kHz oscillator 23 clocked.

The board has 4 RCA sockets 24 which are used as audio input. There are also 6 more RCA jacks 25 provided that can be used as audio outputs. The input signals supplied to the board are separated by capacitor circuits of DC components. In each case, an operational amplifier circuit converts the input signals into a symmetrical signal form. The balanced signals are then converted into an audio codec 26 fed.

The Output signals of the board are in a corresponding manner transferred from a symmetric to an unbalanced waveform and finally lie about one DC blocking capacitor at the corresponding output sockets.

As an audio codec 26 For example, an AD1836 from Analog Devices can be used. This can be operated with sampling frequencies of 96 kHz, 48 kHz and 16 kHz. Its word width is selectable in three stages, between 16 bit, 20 bit and 24 bit. The signal-to-noise ratio and the dynamic range of the audio codecs are 105 dB in this case. The digital-to-analog converters have a dynamic range and a signal-to-noise ratio of 108 dB. The codec's registers are over an SPI port 27 The blackfin processor described and read out the digitized audio data in Packed AUX mode via a SPORT0 28 transferred to the BF533 processor. When using the Packed AUX mode, two external stereo analog-to-digital converters and one external stereo digital-to-analog converter can also be connected to the codec via I ² S. In this case, the codec then time multiplexed the data from all transducers to the Blackfin processor via SPORT0. Since a very large amount of data has to be transferred in this transmission, the maximum sampling frequency under these conditions is limited to 48 kHz.

The evaluation board has an optionally usable option for analog video input and output. There are 3 RCA jacks for each 29 available. The video inputs lead after a DC blocker directly to the inputs of a video decoder ADV7183 30 from Analog Devices. After the outputs of a video encoder ADV7171 31 follow low-pass filters and a noninverting amplifier with a gain of two. To match the impedance, a resistor of 75 ohms is provided and routed to the RCA jacks. The video encoder and the video decoder have a PPI interface 32 connected to the Blackfin processor.

The SPORT0 also connected to the audio codec 28 is accessible via a connector to the developer. The Blackfin processor has a number of UART ports 33 on. These are routed via an RS232 driver module ADM3202 for adaptation of the control. Via a 9-pin SUB-D socket 34 The level-converted UART signals are led to the outside.

The evaluation board also has a 32 MB SDRAM memory chip 35 and two flash memory chips 36 with a size of 1 MB each. The memory modules are equipped with an External Bus Interface Unit (EBIU) 37 of the processor 21 connected.

The evaluation board is expandable via 3 expansion ports with 90 pins each. These include an address bus, a data bus, the PPI 32 , the EBIU 37 as well as the SPORT0 28 and a SPORT1 38 led out. For example, an expansion board with a network interface can be connected to the expansion ports.

The Blackfin processor also has a JTAG (Joint Test Action Group) port 39 on. This is led out to a connector. An emulator can be connected to this port. To access development and control software, such as Visual-DSP ++, a USB bus with a USB interface on the board is available. This converts the USB data into JTAG signals TDI, TMS, TCK, TDO or TRST. The processor is thus programmable via the USB interface. Debugging is also carried out via the USB interface.

to Programming and implementation of the method steps or for external control of the board are a set of software tools used. these can also to a development software package, for example Visual-DSP ++, be summarized. For example, the package contains a compiler for one higher Programming language, especially C / C ++, a runtime library with a supply of mathematical, DSP and C runtime and library functions, an assembler, a linker and a loader. Furthermore, a Be provided simulator, an emulator and a debugger. The development and control software may conveniently generate a user interface, on the programming and control of the board, or the programmable Control and processing unit through a set of convenient tools and features, such as a mixed-programming with a concurrent one Display of a C / C ++ and an assembler code, is simplified. After a faultless The code is then written into the RAM of the evaluation board or the control and processing unit loaded and executed there.

To the Debugging has a plot function that uses an array as a Plot can be considered. For example, a signal given at a frequency of 300 Hz to an audio input and sampled at a sampling frequency of 16 kHz. The case obtained data are written continuously in an array, the designed as a ring buffer. A plot of the array will be after created by stopping the CPU. Other representations, for example an X / Y diagram, a waterfall diagram or an eye diagram, are also buildable.

A another possibility Debugging becomes expediently provided by a Background Telemetry Channel (BTC). On the BTC can between a host computer hosting the named development and control software is running, and the Blackfin processor on the board, or equivalent Processor in the control and processing unit, during the ongoing data exchange. A real-time debugging, so a Tracking of operation and parameter development in real time, are possible. A user can thus be in the ongoing operation of the board or the control and processing unit, intervene and process data or change process variables. The data read by the processor can then also be displayed in a diagram above the Course time are applied.

Subroutine functions and their performance can over a statistical profiling will be displayed. This will be statistical while the execution of the program routines a program counter or program counter read. This determines how long the processor has been in which subroutine is stopped. So can Program parts are found that are poorly written and slow down the speed of the program.

Finally, can a flash programmer may be provided. This one finished written and optimized program in the flash memory of the Boards or the control and processing unit. The program is up then permanently in the flash memory and will turn on after a power up the board or the control and processing unit immediately started.

The 3a and 3b show schematically a structure of the Blackfin processor or the processor core.

The core of the processor consists essentially of a Data Atithmetic Unit 40 , an address arithmetic unit 41 and a control unit.

The Data Arithmetic Unit has two so-called MACs (multipliers / accumulators). These be consist of two 16-bit fixed-point multipliers 42 and two 40-bit accumulators 43 , The result of the multipliers is output as a 32-bit value. Also provided are two 32-bit ALUs for arithmetic and logic operations, four 8-bit video ALUs, a barrel shifter for performing shift operations, and a 32-bit register.

The Address Arithmetic Unit consists of an 8 pointer register 44 , a 16-index register 45 used by data address generators and two data address generators 46 for controlling a circular buffer.

The Control Unit contains a sequencer 47 , This controls the program execution, evaluates jump instructions and controls loops.

Of the Contains processor Up to 80 KB of program memory and up to 68 KB of data memory. Both memories can optionally used as SRAM or cache. A DMA controller is also integrated in the Blackfin processor.

The processor is assigned a system periphery. Their assemblies serve to supply the processor. It is a loop 48 for generating a core clock based on the input clock. The core clock can be up to 750 MHz. From this clock signal all other system clocks are derived. A voltage regulator is used to supply power to the processor. It expediently has a dynamic power management and adapts the core clock and the supply voltage to the power consumption of the currently running application. Finally, a Real Time Clock 49 , a watchdog timer 50 and a JTAG interface 51 available.

As mentioned has the processor continues to over an EBIU interface for controlling an external memory. Also is a controller for Asynchronous access to the Blackfin processor. This can be used to control an SRAM or a flash memory.

When User peripherals are serial interfaces, a parallel interface, Timer and an I / O interface available. There are three types of serial Interfaces available. As a peripheral is a Universal Asynchronous Receiver / Transmitter (UART), for example, the connection between Telephone modem to the computer is known. This interface can in full duplex mode. Another use can be half duplex IrDA.

A Another interface is the already mentioned SPORT interface. Of the includes exemplary processor 2 synchronous serial interfaces, including a time-duplex mode with 128 time slots support. This interface is very well suited to processors in one Multiprocessor system to support each other directly. she can with a very high transfer rate operate.

Of Further, a Serial Peripheral Interface (SPI) interface be provided. This interface is typically used for communication with codec, especially the one mentioned Audio codecs, D / A and A / D converters, LCDs or other microcontrollers used. This is a 4-wire interface. Two lines are used as data lines, one as a clock line and the fourth is used as a device select line. By the Device select line can also several slave devices are connected to a master device.

When parallel interface is the mentioned Parallel Peripheral Interface (PPI) available. This is a bidirectional one Bus with a variable bus width between 8 and 16 bits. He is half-duplex capable and can be operated with a variable clock frequency of 66 MHz become. This interface is mainly used for data exchange Video codecs used.

To the Generation of pulse width modulation (PWM) is possessed by the Blackfin processor three timers. Furthermore there are 16 freely programmable I / O pins. these can For example, to select an SPI slave or to control LEDs are used.

Finally, the processor contains an interrupt controller.

4 shows an exemplary block diagram of an arrangement for carrying out the method. The method described below suppresses a noise with a variable frequency in the range of 50 Hz to 1.5 kHz. The basis is a single-tone ANC system with adaptive notch filter. From a sinusoidal input signal x (n) is an in-phase signal x ₀ (n) and a quadrature signal x ₁ (n) is formed. The signal d (n) represents the noise, in this case the noise, propagating from a source of interference via a transmission medium having the transfer function P (z). The antisound signal y (n) is generated from the in-phase signal x ₀ (n) and the quadrature signal x ₁ (n). It is emitted by the anti-noise loudspeaker Sp1 after a preceding audio amplification NF-PA and arrives with a transfer function H (z) to the place or the spatial area at which the background noise is to be extinguished. The transfer functions P (z) and H (z) describe the sound propagation in the relevant medium, for example in air, but also in a liquid or a solid. They contain information on the distance between source of noise and extinction location, or anti-sounding loudspeaker and extinguishing location and information on possibly existing sound transitions in different media and the like parameters and functional dependencies that are necessary for a correct execution of the method, in particular an optimal extinction of the noise, and must be taken into account.

When superimposing sound and anti-sound, the anti-noise signal and the noise signal add together and generate a detected signal e (n). The error signal is detected with a microphone signal Mic2 and fed back to a Least Mean Square algorithm LMS. This then sets gain factors w ₀ (n) and w ₁ (n) for the in-phase signal x ₀ (n) and the quadrature signal x ₁ (n). The antisound signal y (n) is composed of a linear combination of the in-phase signal and the quadrature signal. The gain factors form the linear coefficients in the linear combination. The antisound signal y (n) thus consists of y (n) = w 0 (N) x 0 (n) + w 1 (N) x 1 (N).

With an amplitude of the two signals x ₀ (n) and x ₁ (n), y (n) can assume any possible amplitude up to magnitude 1 and every phase angle, provided w ₀ (n) and w ₁ (n) in arbitrarily small steps are adjustable.

The task of the LMS algorithm is thus to set the amplitude and phase of the anti-noise signal y (n) so that the interference signal d (n) and the anti-sound signal y (n) cancel out as completely as possible after the passage of H (z). The LMS algorithm thus receives the error signal e (n) and additionally a delayed in-phase and quadrature signal x ₀ '(n) or x ₁ ' (n). These are generated from a delay DELAY and take into account the finite duration of the anti-noise under the influence of the transfer function H (z).

Two microphones Mic1 and Mic2 are used to detect the background noise and the error sound signal. The noise-isolating microphone Mic1 is positioned in the immediate vicinity of the noise source and picks up the background noise there. A phase-locked loop PLL generates the in-phase signal x ₀ (n) and the quadrature signal x ₁ (n) and synchronizes to the detected by the noise microphone Mic input signal x (n). The error signal microphone Mic2 receives the error signal e (n) and introduces this into the LMS algorithm. This embodiment with two microphones has the advantage that there is always an input signal for the phase-locked loop. In a synchronization of the phase-locked loop PLL to a signal supplied only by the microphone Mic2 signal would the phase-locked loop in the event of complete cancellation of noise and anti-sound no longer suitable for synchronization signal received.

5 shows an exemplary implementation of the phase-locked loop PLL. The PLL forms the heart of the method according to the invention and is also referred to as a phase-locked loop. It serves to convert the input signal x (n) obtained from the background noise into a signal pair x ₀ (n) and x ₁ (n), from which the anti-noise signal y (n) can be generated.

The PLL is divided into different blocks in this example. The frequency generating part of the PLL forms a block for a Direct Digital Synthesis DDS. The DDS generates the in-phase signal x ₀ (n) and the quadrature signal x ₁ (n). A phase detector PD detects a phase error Φ between the DDS and the input signal x (n). To minimize the phase error, the DDS is readjusted. This control loop causes the mentioned synchronization of the PLL to the input signal x (n).

To avoid disturbances due to neighboring frequencies, the narrowest possible demodulation in the phase detector PD is advantageous. Under this condition, it may happen that the input signal x (n) is outside the bandwidth of the demodulator in the phase detector. The phase detector in this case no longer provides a signal. The input signal x (n) is in this case outside the capture range of the PLL. In this case, an amplitude detector AMP is provided, which opens the control loop in the event of a missing signal from the phase detector PD and activates a SWEEP module which tunes the DDS as long as possible. until the phase detector receives a signal. The PLL is thereby tuned to a new frequency range.

In the direct digital synthesis DDS, the sinusoidal input signal x (n) is reproduced by a step-shaped signal with discrete-time and discrete values. This means that a new value is output at regular intervals after a sampling period T _A. The length of the sampling period is determined by the sampling frequency. The sampling frequency is a suitably set device constant.

For the example shown here, programmable library functions are used to execute the DDS. The DDS generates a cosine signal as an in-phase signal x ₀ (n) and a sine signal as a quadrature signal x ₁ (n). To calculate the cosine and the sine, use is made of assembler functions in order to carry out the calculation as close to the hardware as possible. In principle, it is possible to have both functions both in the interval [0; π] over a half period, as well as in the interval [0; 2π] over a full period. The digital synthesis starts again from the beginning after passing through the intervals, with an alternation of sign changes having to be performed within one half-period of a simulation of the functions.

From Of particular importance in the DDS is the sampling frequency. At a extinction from background noise to At a frequency of 1.5 kHz, experience shows that a sampling frequency of 16 kHz sufficient. This will save time for the others Calculations available stands.

In the DDS, the frequency of the generated in-phase and quadrature signals can be changed by changing a phase angle Δφ per sampling interval. The frequency generated at the DDS is calculated by the relationship f DDS = Δφ f A / X.

there X represents a device-specific Constant. A typical value for X is in hexadecimal notation X = 0xFFFF + 1. This corresponds to a value of 65536 in decimal Notation.

Conveniently, a program is used for the realization of the DDS, which is the input signal to the audio input of the programmable control and processing unit 10 reads in and then outputs the DDS signals to their audio outputs. The processor located within the control and processing unit receives a regular interrupt from the audio codec after the sampling period T _A. The processor then executes an interrupt service routine (ISR). The ISR allows reading the data from the audio codec, calling a program to manipulate the data of the input signal, and writing the output values to the codec.

Conveniently, the DDS can be implemented as an array to allow later implementation of additional features and functions. 6a shows by way of example the output signals of the DDS with a frequency of 250 Hz. As can be seen from the plot, both signals have a phase difference of 90 °.

7 shows an exemplary block diagram of a phase detector PD. As already mentioned, the phase detector within the phase-locked loop PLL serves to determine the phase error Φ between the input signal x (n) and the signals generated by the DDS. The in 7 The phase detector shown acts as a digital averaging phase detector, ie a digital-averaging phase detector.

The signals x ₀ (n) and x ₁ (n) generated by the DDS are respectively multiplied by the input signal x (n) in a multiplier M1 or M2. Such a multiplication corresponds in each case to an amplitude modulation with a suppressed carrier. It is assumed that an input frequency f _inputs present at the input of the phase detector with a phase shift φ _inputs and the DDS frequency f _DDS generated. For the signals in_cos (t) and in_sin (t) present after the multipliers, it follows, using the addition theorems for trigonometric functions: in_cos (t) = ½ [cos (2π (f Input - f DDS ) t + φ Input ) + cos (2π (f Input + f DDS ) t + φ Input )] in_sin (t) = ½ [sin (2π (f Input - f DDS ) t + φ Input ) + sin (2π (f Input + f DDS ) t + φ Input )].

Both expressions contain an additive mixing Term, wherein the adding up the frequencies f _inputs and f _DDS and must be eliminated. The in the block diagram in 7 shown filters F1 and F2 filter out the associated signals. After the filters F1 and F2, only the following signals are available: out_cos (t) = ½ [cos (2π (f Input - f DDS ) t + φ Input )] out_sin (t) = ½ [sin (2π (f Input - f DDS ) t + φ Input )]

An adjoining division in a div div div leads to the formation of a tangent of the two terms, so that finally in a Arctan term tan ^-1 a time-dependent phase φ e (t) = 2π (f Input - f DDS ) t + φ Input can be determined. If both frequencies f _inputs and f _DDS same, takes φ _e (t) has a time constant value φ on _inputs. The DDS must be readjusted by this amount. In differing amounts of f _inputs and f _DDS is obtained for φ _e (t) is a sawtooth signal.

For example, the multipliers M1 and M2 are implemented as a 32-bit multiplication function, which may be programmed in C / C ++, for example. To control the output signal of the in-phase path x ₀ (n), the signal can optionally be output via a D / A converter. 6b shows by way of example the result of a multiplication of a DDS frequency of 250 Hz with an input frequency of 4 kHz. The signal shows a 4 kHz carrier frequency with an envelope fluctuation of 250 Hz, as expected in suppressed carrier amplitude modulation.

The filters F1 and F2 off 7 essentially have two tasks. The first task is to filter out the additive mixed product after the multipliers M1 and M2 from the signal. For this purpose, the filter bandwidth should correspond to the amounts of _DDS f or f _inputs depending on which of the two frequencies the larger amount. At an unknown frequency f _inputs is assumed to be maximum bandwidth f _DDS, wherein the side to be scavenging frequency below the DDS frequency. Under these circumstances, an octave-wise switchable filter is advantageous over a variable bandwidth filter and is preferred in the embodiment shown here.

The second task of the filters F1 and F2 is the phase-locked Control loop PLL against neighboring interference frequencies shield. Therefore their bandwidth must be relatively narrow. Is for example the PLL tuned to a frequency of 1 kHz and is the Nebenstörfrequenz 1050 Hz, results after the multipliers an undesirable frequency of 50 Hz. This frequency must be suppressed by the filters. As in the spectrum of background noise mainly With harmonics of the fundamental frequency is expected, these can at the lowest fundamental frequency of 50 Hz, a distance of 50 Hz. Accordingly, the filter should have a bandwidth of less than 50 Hz can be realized. Particularly advantageous for this is a realization of the filter in the form of a cascading decimation filter with several outputs.

8th shows an exemplary block diagram of a filter cascade. As a minimum requirement, the decimation filter should have an input sampling frequency of the audio codec, for example 16 kHz, and a corresponding output sampling frequency, for example 8 kHz. The sampling frequency and the bandwidth are further reduced by cascading the filter. It is advantageous for switching to smaller bandwidths, if the ripple of the signal in the passband is as low as possible. The respective stages of the filter cascade can be realized in assembler or in C. It is advantageous if an array for inputting the output values as well as the number of input values and a pointer to a filter status structure are transferred to the function. The filter state is assigned a filter coefficient, delay line and read / write pointer location via the filter status structure. In addition, the struct contains the number of filter coefficients and a decimation index. To simplify the initialization of the struct as much as possible, there should be a definition statement that executes the initialization of the program in one line as far as possible.

The single filter stage forms the basis of the filter cascade. For the phase-locked Control loop PLL will be for the in-phase signal path and the quadrature signal path each a filter cascade needed. Conveniently, Only one filter cascade function is used to which the data of the filter and separate the output of the filter for each signal path calculated. Conveniently, should be a possibility be provided to specify the number of cascade element after which the output value of the filter is output.

The for the Necessary filter cascade Functions and parameters are summarized in a struct. This will set the number of submissions Parameters sustainably limited. The stack to be managed by the processor remains so clear and small as possible and can be written and read with minimal time loss become.

Of the Struct contains Pointers pointing to the first entry of an array. The initial values for the Filter stages form a two-dimensional array. The first level of the array indicates the respective filter level, the second level is used for storing the two input values for each filter stage.

It is also a pointer to delay lines intended. Also, statusstructs pointing to a pointer is present in the struct used by the filter function.

The functioning of an exemplary C function of the filter cascade is shown in FIG 8th shown by way of example. The function receives an input value inval. Then, a cascade function writes an input value into an input buffer of the filter stage in [0]. Whether a value [0] or [1] is written to [0] is controlled by a decimation counter counter [0]. The decimation counter counter [0] changes its value in the input buffer either from 0 to 1 or from 1 to 0 after each saving. The value of the decimation counter determines the position in which the next time the filter cascade is written into it. If both memory locations are filled, the decimation counter is reset to 0 and a function fir_decima is called. This calculates the output value of the filter stage and stores it in the input buffer of the 2nd filter stage in [1]. Now the value in the decimation counter [1] of the second filter stage is changed. In exactly the same way, the process continues until the last filter stage.

As described, the filter cascade should transfer the output value of a specific filter level. 9 shows a related representation. To output the output value, the filter cascade function is given a parameter n_out. The parameter n_out acts as a switch that selects between two filter stages, in the example shown here between the stages in [2] and in [1], and retrieves a value out val from one of the two stages. The decision as to whether the value is recalled from memory location 0 or 1 takes place via the respective decimation counter counter [2] or counter [1].

to Initialization of the filter cascade becomes an initialization routine used. This reserves the required memory and initializes in a loop the filter cascade structs and the status structs the filter stages.

The 10a to 14 show some amplitude responses of the filter cascade at different outputs. Frequency ranges are linear on the abscissa, and the associated amplitudes are plotted logarithmically on the ordinate.

10a shows an amplitude response at the output 1 of the filter cascade. It can be seen that at output 1 all frequencies above 2.0 kHz are filtered out. 10b shows an amplitude response at the output 2 of the filter cascade. In this example, all frequencies above 1.0 kHz are filtered out.

11a shows an amplitude response at the output 3 of the filter cascade. At this output frequencies above 500 Hz are filtered out. 11b shows an amplitude response at the output 4 of the filter cascade. Frequencies above 250 Hz are filtered out here.

12 shows the arrangement used for bandpass measurement at the individual filter outputs. At a filter F, or at its nth output a DDS is applied, which provides a frequency of 1kHz. This is applied in each case to multipliers M, which are arranged before and after the filter stage F. A spectrum analyzer and tracking generator S reads in the signals at the multiplier connected downstream of the filter stage F and outputs a tracking pulse to the multiplier preceding the filter stage.

13 shows an amplitude response at the output 7 of the filter cascade. At this output frequencies above 30 Hz are hidden. 14 shows an amplitude response at the output 7 with a center frequency of 1 kHz with a left and right side 3dB bandwidth of about 15 Hz.

The respective sampling frequencies and 3dB bandwidths at the outputs of the filter stages are shown by way of example in the following table:

15a shows an exemplary time domain measurement. In this case, the DDS supplies a signal with a frequency of 1 kHz. To this signal, an input signal of 900 Hz was multiplied. The measured signal is in 15a shown above. The signal shows as a resulting signal a sine wave with a frequency of 100 Hz, which is superimposed on a frequency of 1.9 kHz. The waveform shown below shows a low pass filtered signal through the filter cascade. In the example shown here, the signal was output at output 1 of the cascade. The 3 dB bandwidth is 1.15 kHz in this case. As can be seen from the figure results after filtering a signal with a frequency of 100 Hz, the difference frequency between 1 kHz and 900 Hz, which is read out with a sampling frequency of 4 kHz. With this signal and the signal of the quadrature path, the phase difference between the DDS frequency and the input signal can be determined.

After the low-pass filtered signals out_cos and out_sin are present, as described with these signals, the phase difference between the DDS signals and the input signal can be calculated. 15b shows a related example. In this case, the DDS generates a signal at a frequency of 1 kHz while an input signal at a frequency of 900 Hz is applied. The low-pass filtered signals as well as the calculated phase angle were output. As previously described, in this case, the phase angle over time has a sawtooth shape. The frequency of the sawtooth corresponds to the frequency difference between the DDS frequency and the input frequency. In this example, the frequency difference is -100 Hz. The slopes of the sawtooth are therefore sloping.

task of the regulator REG, it is now the phase difference as possible to bring to a value of zero and keep. At a disappearing Phase difference is the input frequency equal to the DDS frequency. To extinguish of the noise have to the frequencies of the input signal and the DDS signal are the same Have frequencies.

From the phase detector, the regulator REG receives a signal φ e (t) = 2π (f Input - f DDS ) t + φ Input ,

The signal indicates the actual phase difference between the DDS and the input signal. By differentiating φ _e (t), the frequency difference can also be determined. The controller can now be divided into the regulation of the frequency and the phase.

To determine the frequency difference, the difference of the phase difference must be calculated at two consecutive sampling times. The controller now has to add up the frequency difference to the DDS frequency. Because the low-pass filters cause run-time, care must be taken that the system does not vibrate. It is therefore expediently only a part of the frequency difference added. This part of the control can now respond quickly to changes in the frequency of the input signal. If the frequency difference is zero, then φ _e (t) is constant and contains the fixed angular deviation between the DDS and the input signal. If φ _e (t) is positive, the input signal of the DDS leads ahead. To compensate for the phase difference in this case, the DDS frequency must be increased. If the phase difference is negative, the DDS frequency must be lowered accordingly. In order to regulate the phase, therefore, a part of φ _e (t) of the DDS frequency can be added up. Here too, care must be taken that the system does not oscillate.

An exemplary signal flow diagram of the controller is shown in FIG 16 shown. The terms labeled T represent time delays, K _P and K _D are multipliers.

Of the Regulator can also be in a higher Programming language, especially in C, be realized. The differentiator The controller should determine the difference between two phase angles. Since the phase is shown only in the range from -π to π, takes place at a linear phase progression after π a jump to -π. A normal Subtraction function would doing a change from 2π, which is wrong. The subtraction function used must be this Consider jump exception.

The coefficients in the multipliers K _P and K _D must be less than 1. To implement them, right shift operations can be used. Tests have shown that the scheme works best with a K _P that has 11 right shifts and a K _D that equals 5 shifts. It has been found to be useful for K _P to have a value of approximately 0.0004 and K _D approximately 0.03.

Because the filter bandwidth and thus also the sampling frequency of the filters is adjustable, the regulator should be at the output sampling frequency of the filter are operated because the controller only in this temporal Distance gets a new value from the filter. The regulator is preferred implemented as a D and P controller with downstream I controller. This corresponds to a PI controller. Because the controlled system in this case an I-member is because the phase is over the frequency is regulated, this type of regulator is particularly suitable, to generate a control deviation of 0.

The 17a and 17b show exemplary plots of the control behavior. The control of the frequency and the phase were recorded in this example with a filter bandwidth of 280 Hz at the output of the third filter stage. At the input of the phase-locked loop PLL in this example is a frequency jump from 700 Hz to 900 Hz. The corresponding plot is in 12a shown. It can be seen from the plot that the PLL is adjusted after about 200 ms in this jump. The control behavior after the 7th filter stage with a frequency hopping from 700 Hz to 715 Hz is in the plot in 17b to see.

The already in 5 As shown, amplitude detector AMP serves to switch between the search mode and the control mode. The search mode is used to find a frequency within the filter bandwidth. The switching criterion here is whether after the filter, a signal with a sufficient amplitude is applied and thus a signal within the filter bandwidth is present or not. For this purpose, the amounts of the output signals are added by the filters and then compared with a threshold value. If the sum is below the threshold value, the search mode is started. If the sum is above the threshold, the controller is called as previously described.

If the noise signal extinguished It is important to maintain the stable frequency response of the PLL detect. This is called lock detection. Only, if the frequency of the noise and the DDS frequency is the same, the generated anti-noise to an extinction of the noise. The PLL is then stably locked to a frequency when the Phase error is zero.

For this is checked before the evaluation of the phase detector, if after the filter on Signal with enough greater Amplitude is present. This is then proof that the input signal lies in the filter bandwidth.

switches the amplitude detector in the search mode, the lock status thus becomes spent as not curled. When switching to the control mode the lock detection is called after the rules. At the lock detection will be the amount of the current and the previous one Value of the phase detector added and compared with a threshold value. A finite threshold is used because of a Comparison with size zero already a deviation of less than 0.007 ° already a non-curled State of the PLL would show. Sufficiently accurate, according to experience, a threshold of about 2 °.

in the Seek mode can be the jamming signal either over a Fast Fourier Transform (FFT) or a sweep of the DDS frequency respectively. In the example shown here, the method of sweeping was applied. This brings a lower programming effort itself as the realization of an FFT.

The search mode can take place with a fixed filter bandwidth and thus equal frequency steps or with increasing frequency with a larger bandwidth and thus larger frequency steps to go through. An acceleration of the search results in a variable, adapted to the frequencies searched step size. It takes about one second to search the frequency range between 50 Hz and 1.5 kHz.

To the acoustic detection of the interference signal serves as mentioned a microphone. Because of the relatively high sensitivity, the small Design and a low supply voltage while an electret microphone prefers. This is a power supply for the microphone and a gain of the Microphone signal necessary.

Electret microphones require a supply voltage of 1.5 to 10 V for the impedance converter integrated in the microphone. A microphone consumes a maximum current of 0.5 mA. To limit the current, a resistor can be inserted. The size of the resistor is relatively uncritical, a resistance on the order of between 1 kΩ and 10 kΩ can be used. In the wiring diagram 18 is an exemplary audio input can be seen.

There Electret microphones only a very low output voltage of approx. 5 mV / Pa is a gain of the signal necessary to control the audio codec. It must an override be avoided to harmonics and synchronization of the PLL to rule out wrong frequencies.

How out 18 can be seen, is provided at the audio input an OPV amplifier stage with switched after inverter to generate a balanced signal. The gain of the 1st amplifier stage acts as an impedance converter. To increase the gain, the resistor R87 in 18 be changed appropriately. Because the sound level in the real operation of the anti-noise device is not yet known, the resistor R87 can be replaced with a 120 kΩ resistor. When resistor R105 is 5.76 kΩ, a gain of -20.83 is achieved. These designs should be made for two audio inputs. The first audio input is used to record the noise directly to the source of interference and to synchronize the PLL. The second audio input is for a microphone that picks up the noise at the point where you want to cancel the noise. The generated signal is fed to a Least Mean Square (LMS) algorithm.

The LMS algorithm is a gradient-based search method. It was developed by B. Widrow and ME Hoff in 1960. The algorithm is used in the method shown here to set the coefficients w ₀ (n) and w ₁ (n) of the anti-noise signal. The LMS algorithm receives as inputs the error signal e (n) as well as the signals x ₀ (n) and x ₁ (n) from the PLL.

The error signal is the addition of background noise and anti-sound. The goal of the LMS algorithm is to adjust the coefficients w ₀ (n) and w ₁ (n) so that the portion of the noise frequency to be canceled disappears into e (n). The LMS algorithm follows the recombination formula w (n + 1) = n (n) + μ e (n) × (n).

μ represents the increment represents the speed of the algorithm and whose accuracy can be adjusted. If μ is too large, converges the algorithm is not. Another convergence condition is that the error signal and the PLL have a maximum phase difference of 90 °. This condition is realized by the already mentioned delay unit DELAY. Here, a so-called secondary delay unit can be used. The delay essentially corresponds to the duration of the sound between the anti-noise loudspeaker and Morph microphone contained in the runtime function H (z). It can be assumed that the distance between anti-noise speakers and Morale microphone stays the same. This can be a solid and constant Length of delay be accepted.

Such LMS algorithm with calculated delay is also called Filtered-X LMS algorithm or FXLMS. The recursion formula for an FXLMS is then w (n + 1) = w (n) + μ e (n) × (n - Δ k ).

Here, Δ _k represents the number of delays and is calculated from Δ t _k = _{f s} f. t _f is the time required by the sound from the anti-noise loudspeaker to the microphone, f _s is the sampling frequency.

It can different approaches to realize the secondary path delay unit DELAY in a variable Distance between the anti-noise speaker and the microphone become.

When first option can a dirac push, i.e. a very short-term, peak-like signal with high amplitude over the Anti-noise loudspeakers are emitted from the microphone is recorded. The Dirac push can to the correlation between the time of emission and the time be used to record the signal, with the delay time can be measured directly. The Secondary Path Delay Unit must be at exactly this time interval delay. Such a calibration is in regularly recurring temporal Spacing performed.

When second option becomes a phase difference between the PLL and the error signal with the aid of a phase detector in the preceding description determined. Instead of the input signal x (n), the error signal e (n) applied to the phase detector. The signals passed to the LMS algorithm Need to become then recalculated. This is done by changing the phase angle of the PLL and the phase difference between the PLL and is added to the error signal. Then the sine and cosine values will be calculated calculated to the appropriate angle and passed to the LMS algorithm.

When third possibility the direction is monitored, in which the LMS algorithm governs. Regulates the LMS in the wrong Direction, are shifted from the PLL by 90 ° shifted signals to the Pass LMS. If the control direction is again wrong, the signal for the LMS becomes again rotated by 90 °.

The third option is the easiest to implement and operate with a minimum of computational effort. If the LMS does not converge, either w ₀ or w _{1 is} controlled to 1 or -1. This can be taken as an indication of a too large phase shift, provided that the anti-noise signal can in any case become louder than the noise signal. A disadvantage of this variant is that if the phase difference is too large, the anti-siren signal can briefly become loud until the phase difference has been readjusted. The LMS algorithm and the secondary path delay unit can be programmed and implemented in C.

19 shows an exemplary measuring arrangement for functional testing of the method and the arrangement according to the invention. As a measuring device is used in this embodiment, a computer PC with an audio test program, such as the program developed by U. Müller program audio tester. The PC is used in this embodiment both as a function generator, as well as oscillograph and spectrum analyzer in the audio field.

to Measurement is performed by the function generator of the program running in the PC pure tones generated over output a line-out output from a sound card. The audio signal is reinforced with an active box AB and aired. This signal represents the background noise. For synchronization the PLL of the anti-noise device is at a distance a from the active speaker AB the microphone Mic1 attached. The point where the background noise extinguished is to be located at a distance b from the active speaker AB. It is true that the distance b is large compared to the Distance should be a. For example, a = 14cm and b = 180cm. At the distance b is the Morre Microphone Mic2.

The anti-noise speaker is off in the arrangement 19 formed as another active box AB2. This is located at a distance c from the microphone MIC2. For the sizes of a and b c = 70cm. To measure the level at the location of the microphone MIC2 the error signal is first to the control and processing unit, in this case a board for digital signal processing DSP, passed and forwarded by this to a line-in input of the sound card on the PC. The incoming data at the line-in input are evaluated with the spectrum analyzer function of the audio test program in the PC. For the audio test program, an appropriate sampling frequency having a sufficient data width and a sufficiently fine dot count is selected for the FFT. A sampling frequency of 8 kHz with a data width of 16 bits and an FFT point number of 32768 is expedient. The resulting frequency resolution is 0.24 Hz. The window function for the FFT can be the Hamming window function.

The with the test arrangement 19 measured results show that at a noise level of -18 dBFS an anti-noise radiation can reduce the level to less than -80 dBFS. This reduces the level of the interference signal below the noise limit. The interference signal is suppressed to the lower limit of the dynamic range of the microphone MIC2. A level difference of 60 dB is roughly the ratio between the noise of a heavy truck and soft whisper.

Some spectra exemplified are in the 20 to 23 shown. 20 shows an exemplary spectrum with a noise at 60 Hz with and without anti-sound. The noise signal is attenuated by more than 50 dB in this example by the anti-sound. 21a shows a spectrum with and without anti-sound at a frequency of the noise of 750 Hz. One recognizes a maximum in the audio spectrum, which is attenuated after irradiation of the anti-sound by about 60 dB. 21b shows a spectrum with a noise signal of 1000 Hz with and without anti-sound. The Störschallpeak at 1000 Hz is attenuated here by 72 dB.

22a shows a spectrum with a noise signal of 250 Hz. After irradiation of the anti-noise, the level of the maximum is attenuated by about 67 dB. 22b shows a Störschallspektrum with a maximum at 500 Hz. After irradiation of the anti-noise results in an attenuation of about 70 dB.

23 finally shows a noise spectrum at 1500 kHz. After irradiation of the anti-noise, the corresponding maximum is attenuated by 59 dB.

Several Tones, i. several frequencies of background noise can be achieved by a parallelized embodiment of the anti-sounding method dampen. There are several PLL used, each on the respective Maxima of the individual frequencies of Störschalls are lured. A Mutual influence of the anti-noise signals can then in each Be excluded if the respective frequencies of the interference noise in no integer ratio stand. In this case, the antisound signal always only interferes with the noise the respective frequency.

at Idle times may cause the CPU of the device to enter an idle mode purposes of energy saving.

As already mentioned, the finding of frequencies in background noise can be realized via an FFT. This increases the speed of finding the disturbing sounds. The Secondary Path Delay Unit can also be realized according to other variants be where the big one Phase difference is avoided, as mentioned, to a temporary loud anti-noise signal leads.

All Software implementations can also take the form of a specialized, Data processing hardware can be realized and stored on a circuit board be integrated. It is also possible to arrange the anti-noise speaker in a headphone. The anti-noise speaker in this case does not have a large acoustic Give up performance while the area in which the background noise extinguished becomes, by the design of the headphone directly on the environment of the protected Ear limited remains. In this case, the amplifier output stage can be omitted and the background noise is steamed immediately at the user's ear.

in the Frame expert Acting can more changes on the embodiments shown respectively. Further embodiments emerge from the dependent claims.

5

noise source

6

Störschallwelle

7

Anti sound wave

10

Tax- and processing unit

20

programming unit

21

processor

22

oscillator

22a

real Time clock

23

oscillator

24

RCA jacks, Audio input

25

RCA jacks, Audio output

26

Audio codec

27

SPI port

28

SPORT0, Serial Port 0

29

RCA jacks, Video input and output

30

video decoder

31

video encoder

32

PPI interface, Parallel Peripheral Interface

33

UART connectors, universal Asynchronous receiver / transmitter

34

SUB-D connector, 9 pin

35

SDRAM memory module, Synchronous Dynamic RAM

36

Flash memory

37

EBIU, External bus interface unit

38

SPORT1

39

JTAG port, Joint Test Action Group Port

40

Data Arithmetic Unit

41

address Arithmetic Unit

42

Fixed Point multiplier

43

accumulators 40 bits

44

8th Pointer register

45

16 index register

46

Data address generator

47

sequencer

48

Core clock control circuit

49

real Time clock

50

Watchdog Timer

51

JTAG interface

FROM

Powered speakers

STARTING AT 2

second Powered speakers

AMP

amplitude detector

counter [N]

Decimation counter Nth filter stage

DELAY

delay means

DDS

direct Digital synthesis

div

division element

DSP board

digital signal processing

fir_decima

filter function

in [N]

input buffer Nth filter stage

inval

input value for filter cascade

K _P , K _D

multipliers

LMS

least Mean Square Algorithm

M1

first multiplier

M2

second multiplier

Mic1

Störschallmikrofon

Mic 2

Error signal microphone

PD

phase detector

PLL

phase-coupled loop

REG

regulator

Sp1

Anti-sound speaker

SWEEP

Sweep module

T

Time delay element

tan ^-1

Arctan link

d (n)

noise

H (z)

transfer function anti sound

P (z)

transfer function background noise

e (n)

error signal

T _A

sampling

w ₀ (n)

gain phase signal

w ₁ (n)

gain quadrature signal

x (n)

input

x ₀ (n)

phase signal

x ₀ '(n)

delayed in-phase signal

x ₁ (n)

 quadrature signal

x ₁ '(n)

delayed quadrature signal

y (n)

Anti-noise signal

Φ

phase error

y (n)

Anti-noise signal

φ _e (t)

time-dependent phase

Claims (17)

A method for damping an acoustic noise, characterized in that the noise acoustically detected by a microphone device with a conversion into an interference signal, then a synchronization of a phase-locked loop on the interference occurs, due to the interference signal generated by the phase-locked loop an anti-noise signal and is emitted acoustically into the environment for destructive interference with the acoustic noise. A method according to claim 1, characterized by the following method steps: - Acoustic detection of the acoustic noise on a Störsignalmikrofon (Mic1) and converting into a sinusoidal input signal (x (n)) for the phase-locked loop (PLL), - generating a DDS signal (x ₀ (n), x ₁ (n)) by the phase-locked loop with a conversion into the anti-noise signal (y (n)), - acoustic radiation of the anti-noise signal via an anti-noise speaker (Sp1), - acoustic interference of the noise and the anti-sound, acoustic Detecting a Überla fringing noise resulting from this overlay on a Errorsignalmikrofon (Mic2) and converting into a Errorsignal (e (n)), - coupling the DDS signal (x ₀ (n), x ₁ (n)) and the Errorsignals (e (n)) into a load mean square algorithm (LMS) and generating an antisound control signal, - controlling feedback of the antisound control signal to the conversion of the DDS signal into the A ntischallsignal. Method according to Claims 1 and 2, characterized in that the phase-locked loop (PLL) carries out a frequency generation in the form of a direct digital synthesis (DDS) in conjunction with a phase detector (PD), wherein an in-phase signal x ₀ (n ) and a quadrature signal x ₁ (n) whose phase error (Φ) to the input signal (x (n)) determined by the phase detector and their frequencies to minimize the phase error by means of a control element (REG) are tuned. Method according to claim 3, characterized in that the phase detector (PD) performs a narrowband demodulation, wherein at an outside the capture range of the phase-locked loop lying input frequency of the input signal (x (n)) a sweep of the direct digital Synthesis is performed until the presence of a signal at the phase detector. A method according to claim 3 and 4, characterized in that the phase detector (PD) is designed as a digitally averaging phase detector, wherein the in-phase signal (x ₀ (n)) and the quadrature signal (x ₁ (n)) in each case a multiplier (M1 , M2) are multiplied by the input signal (x (n)), then in each case a filter element (F1, F2) hiding additive mixing products with generating a differential output signal (out_sin, out_cos) with a division of the differential output signals in a divisional element, a subsequent Arcan computation is performed in an arctan and an output of the phase error (Φ). Method according to claim 5, characterized in that that each one filter member (F1, F2) as a cascading Low-pass decimation filter operated with at least two filter stages becomes. Method according to claim 3, characterized that the control element (REG) the phase difference between the input signal (x (n)) and the DDS signal to zero, the control process in the form of a D and P control operation with a downstream I control process is carried out in the form of a PI control process. Method according to claim 4, characterized in that that for switching between sweep and control modes is an amplitude detector (AD) is provided, the amounts of the output signals after the filters are added and compared with a threshold and at a value below the threshold value, the sweep mode is started and otherwise the rule mode is called. Method according to claim 2, characterized in that that the LMS algorithm, a convergence securing second-way delay unit (DELAY), which is one of the delay time between anti-noise speakers (Sp1) and Errorsignalmikrofon (Mic2) appropriate delay for Generating a phase difference between the phase-locked loop (PLL) and the error signal (e (n)) generated. A method according to claim 9, characterized in that in a first embodiment Ver Delay is determined by a regular emission of a Dirac pulse through the anti-noise speaker (Sp1), which is recorded on the Errorsignalmikrofon, wherein the time between the generation of the Dirac pulse and the recording of the signal is measured as a delay time. Method according to claim 9, characterized in that that in a second embodiment the delay over that Determining a phase difference between the phase-locked Control loop (PLL) and the error signal by means of a phase detector accomplished is, with the error signal e (n)) present in place of the input signal. Method according to claim 9, characterized in that that in a third embodiment the delay is corrected out of a control tendency of the LMS algorithm, where at a wrong regulation tendency by a phase angle shifted by 90 ° Output signals from the phase-locked loop (PLL) as long passed to the LMS algorithm until the regulation trend is in the right direction. Arrangement for damping acoustic noise, characterized by a noise microphone (Mic1) for acoustically recording the noise and converting it into an input signal (x (n)), a programmable control and processing unit connected to the noise microphone ( 10 ), an audio amplifier unit (NF-PA) with a connected, an acoustic anti-noise signal ( 7 ) and an error signal microphone (Mic2) for detecting a residual error signal (e (n)) in connection with the control and processing unit. Arrangement according to claim 13, characterized in that the programmable control and processing unit ( 10 ) a phase-locked loop (PLL) comprising a phase detector (PD), a regulator (REG) and a direct digital synthesis unit (DDS) with an input to the phase detector for the input signal (x (n) detected by the noise microphone (Mic1)) and each having an output for an in-phase signal (x ₀ (n)) generated by the direct digital synthesis unit and a quadrature signal (x ₁ (n)) for generating an antisound signal (y (n)). Arrangement according to claim 13 and 14, characterized in that the programmable control and processing unit ( 10 ) a load mean square algorithm (LMS) with the in-phase signal (x ₀ (n)), the quadrature signal (x ₁ (n)) and the error signal (e (n)) as input quantities in feedback to actuators (w ₀ (n ) w ₁ (n)) for the generation of the antisound signal (y (n)). Arrangement according to claim 15, characterized in that the programmable control and processing unit ( 10 ) has a delay (DELAY) for the delayed transfer of the in-phase and quadrature signal to the load Mean Square algorithm (LMS). Arrangement according to claim 13 to 16, characterized in that the programmable control and processing unit ( 10 ) as an evaluation board ADSP-BF533 EZ-KIT LITE with a development of at least one C / C ++ compiler, a runtime library, an assembler, a linker and a loader development software and a flash memory is formed.