DE102006011462B4 - Memory circuit and method for operating a memory circuit - Google Patents

Abstract

Memory circuit (1) with
a resistance memory element (3),
a bit line (4),
a select transistor (2) disposed between the resistive memory element (3) and the bit line (4), non-conductive in an idle state to disconnect the resistive memory element (3) from the bit line and conducting to address the resistive memory element, to connect the resistive memory element (3) to the bit line, and another transistor (7),
characterized in that
the further transistor (7) is connected to a node (N) between the resistance memory element (3) and the selection transistor (2), and
the selection transistor (2) and the further transistor are designed such that in the idle state, in order to apply a predetermined potential via the further transistor (7) to the resistance memory element (3), the selection transistor (2) is nonconductive and the further transistor (7) is conductive, and that for addressing the resistance memory element of the selection transistor (2) is conductive and the further transistor (7) is non-conductive.

Description

The The invention relates to a memory circuit having a resistance memory element and a method for. Operating such a memory circuit.

memory devices can Resistive memory elements for storing information. The resistance memory element can assume different resistance states for this purpose, each of which can be assigned to a logical state. Resistive memory elements are often called CBRAM memory elements (CBRAM: Conductive bridging RAM), PMC memory elements (PMC: Programmable Metallization Cell). A resistive memory element comprises after understanding the present invention, a solid state electrolyte, between a Anode of a conductive migrating material and an inert cathode is arranged. By Applying an electric field to the solid electrolyte migrates the migrating material of the anode in the solid state electrolyte, causing the Resistive memory element conductive becomes (it takes a low resistance) and by mooring an inverted electric field becomes the migrating material back pushed to the anode, causing the resistance of the resistive memory element increases (it decreases a high resistance).

Usually has such a memory device on memory cells having a Comprise selection transistor and the resistance memory element, the in series between a panel element that has a set potential and are connected to a bit line. By activating (conductive make) of the selection transistor, the resistance memory cell be addressed and cherelement on the Widerstandsspei can z. B. by applying a voltage between the bit line and the Plate element to be accessed.

In a case where the selection transistor is nonconductive and the resistive memory element is in a high resistance state (High resistance state), a node floats between the selection transistor and the resistive memory element, d. H. he has no fixed potential. This is this sensitive to induced disturbances, which is a result of level transitions of a Can be signals which is guided at a short distance to the node, such as an activation signal on a word line through which the corresponding one Selection transistor is controlled. Such disorders can become an undesirable Voltage drop across the Lead resistance memory element, which can reduce the resistance of the resistive memory element. A change the resistance of the resistance memory element can continue cause that the logical state associated with the resistance state is, can not be detected correctly. Even if the voltage drop across the Resistor memory element is not sufficient to the resistive memory element to a low resistance state (low resistance state) To program, the repeated occurrence of voltage drops above the Resistor storage element lead to a change in resistance, so that after several accesses to the appropriate memory cell the stored information can no longer be detected correctly. Consequently, depends the data retention time from the number of accesses. Even if the stored information correctly after a change in the resistance of the Resistor memory element can be detected, such Reduction of resistance continues to be an extension the access time to the memory cell lead.

A generic memory circuit and a generic device for operating such a memory circuit is in the US 2005/0195673 A1 shown. From the US 2005/0185444 A1 a memory device is described with a layered structure in which a solid state electrolytic cell is used.

It It is an object of the present invention to provide a memory device with a resistive memory cell and a method of operation a memory device to provide, wherein the Degradation of the resistance state to which the resistive memory element is set, due to disturbances, which are induced by adjacent signal lines avoided can be.

These Tasks are performed by the memory circuit and the method for Operating the memory circuit according to the independent claims solved.

Further advantageous embodiments of the invention are in the dependent claims specified.

According to the present Invention is provided a memory circuit comprising a resistive memory element, a bit line and a selection transistor to the resistive memory element to address, wherein the resistance memory element via the Selection transistor is connectable to the bit line. Further is another transistor provided with the resistive memory element is connected to a predetermined potential at a node between the selection transistor and the resistance memory element to create.

Of the allows more transistor it, the node between the selection transistor and the resistive memory element with a fixed potential to connect, to prevent the node "floatet".

Preferably The resistance memory element comprises a programmable metallization cell.

Of the Selection transistor may be formed so that this conductive when a first potential is applied and does not become conductive, when a second potential is applied, the further transistor is formed so that this becomes conductive when the second potential is created and does not become conductive when a third potential is created.

Of the Selection transistor may further via a first word line controlled and the further transistor via a second word line be controlled.

The third potential can be chosen that way be that the selection transistor is not conductive.

Preferably the select transistor is of an enhancement type and the others Transistor of a depletion type, with the first potential in a range between the second and the third potential provided is.

Farther a control circuit may be provided to the first, second and third potential at the first and second word lines and at least one Write and read potential on the bit line create.

The Control circuitry may be configured to apply the second potential the first and second word lines in an idle state of the memory circuit so that the selection transistor is nonconductive and the other Transistor is conductive to the predetermined potential at the resistance storage element to apply; and for addressing the resistive memory element to apply the first potential to the first word line so that the selection transistor becomes conductive, a bit line potential to apply the resistive memory element and the third potential to be applied to the second word line, so that the further transistor does not become conductive.

The Control circuitry may be configured to apply the third potential to apply the second word line, either simultaneously or after the first potential has been applied to the first word line.

Preferably is a first terminal of the resistor memory element with a first terminal of the selection transistor and a plate element with connected to a second terminal of the resistance memory element, to create a plate potential, wherein a second terminal of the Selection transistor is connected to the bit line, wherein the other Transistor has a first terminal connected to the first terminal the resistance memory element is connected and a second Terminal, on which a predetermined potential is applied has.

Of the second terminal of the further transistor may be connected to the plate element be connected.

One Gate terminal of the further transistor may be connected to the second word line and a gate terminal of the selection transistor with the first word line be connected.

According to one another embodiment According to the invention, the memory circuit comprises the first and a second Resistive memory element, the first and a second bit line, the first selection transistor, around the first resistive memory element to address, wherein the first resistance memory element with the first bit line connectable, and a second selection transistor, to address the second resistive memory element, wherein the second resistive memory element connectable to the second bit line is. Furthermore, the memory circuit comprises the first further transistor, which is connected to the first resistive memory element to a predetermined potential at a first node between the first selection transistor and the first resistance storage element and a second further transistor connected to the second Resistor storage element is connected to a predetermined potential at a second node between the second selection transistor and to apply the second resistance memory element. In this embodiment can adjacent word lines are used to connect the further transistor to control.

The first word line may be provided to the first selection transistor and control the second further transistor, and wherein a second Word line is provided to the second selection transistor and to control the first further transistor.

According to the present invention, there is provided a method of operating a memory circuit comprising a resistive memory element, a bitline, and a selection transistor for addressing the resistive memory element, the resistive memory element being connectable to the bitline via the selection transistor is. Furthermore, a further transistor is provided which is connected to the resistive memory element to apply a predetermined potential. The method includes the steps of opening the selection transistor and closing the further transistor in an idle state to apply the predetermined potential across the further transistor to the resistive memory element, and closing the selection transistor and opening the further transistor when addressing the resistive memory element to the bit line potential to apply to the resistive memory element.

Preferably the selection transistor becomes conductive, if a first potential is applied and not conducting, if a second potential is applied, with the further transistor becomes conductive when the second potential is applied and not becomes conductive when a third potential is applied, the third potential chosen is that the selection transistor is not conducting.

Of the Selection transistor can over a first word line and the further transistor via a second Word line to be controlled.

According to one embodiment According to the present invention, a storage device is provided, a semiconductor substrate having a first memory cell, the one Comprising select transistor structure and another transistor structure, a signaling layer disposed on the semiconductor substrate is and a first bit line and a first and second word line comprises a memory layer. On the signaling layer is arranged and a solid electrolyte material comprises, and a plate member structure, which on the storage layer is arranged.

Preferably have the selection transistor structure and the further transistor structure each a first source / drain region on, wherein a connecting element in the signaling layer is provided, which is an electrical contact between the first Source / drain region and the memory layer provides.

The another transistor structure may have a second source / drain region, wherein a further connecting element is provided, which is the second Source / drain region and the plate element structure with each other combines.

The first word lines are preferably connected to a gate region of the selection transistor structure and the second word line with a gate region of the further transistor structure connected.

The first select transistor structure may include a third source / drain region which is connected to the bit line, wherein a second Memory cell is provided, wherein a third source / drain region a second selection transistor structure as a common third Source / drain region in common with the third source / drain region of the first selection transistor structure is provided.

A second memory cell may be provided, wherein a second source / drain region a second further transistor structure as a common second Source / drain region together with the second source / drain region the first further transistor structure is provided.

According to one another embodiment According to the invention, the selection transistor structure is a transistor structure of the enhancement type and the second depletion type transistor structure provided, wherein the first and second further transistor structures disposed in a doping well within the semiconductor substrate are, wherein the doping well a different to the semiconductor substrate Having doping concentration.

The first and second memory cells may be along the first bit line be arranged, wherein the second bit line is provided, the is substantially parallel to the first bit line, wherein along the second bit line, a third and fourth memory cell are arranged, wherein in a direction substantially at right angles for the course of the bit line, the selection transistor structures and the further transistor structures are arranged alternately.

According to one embodiment the present. The invention is a method for producing a Storage device provided, which includes the steps of providing a Halbleitersub strats with a first memory cell having a selection transistor structure and another transistor structure, the provision of a Signaling layer on the semiconductor substrate, wherein the signaling layer comprises a first bit line and a first and second word line, the provision of a storage layer on the signaling layer, which is a solid electrolyte material comprising and providing a plate structure on the storage layer includes.

The Selection transistor structure and the further transistor structure can each provided with a first source / drain region, wherein a connector is provided in the signaling layer that will make an electrical contact between the corresponding ones first source / drain regions and the storage layer available provides.

The further transistor structure can be provided with a second source / drain region, wherein a further connecting element ( 20 ) which interconnects the second source / drain region and the plate structure.

The Connecting element and the other connecting element can in one or more identical process steps are provided, wherein after providing the storage layer in at least the region, the is arranged above the further connecting element, the storage layer is removed and arranged according to a plate structure, that the further connecting element in electrical contact with the plate structure passes.

To the removal of the storage layer over the further connecting element can be a side wall of the storage layer with an insulating Layer are provided before the plate structure is applied.

The first select transistor structure may be connected to a third source / drain region be provided, which is connected to the bit line, wherein a second memory cell is provided, wherein a third source / drain region a third selection transistor structure as a common third Source / drain region together with the third source / drain region of first further transistor structure is provided.

Preferably a second memory cell is provided, wherein a second source / drain region a second further transistor structure as a common second Source / drain region together with the second source / drain region of the first further Transistor structure is provided.

The first and second memory cell may be along the first bit line be arranged, wherein a second bit line is provided, which is substantially parallel to the first bit line, wherein along the second bit line, a third and fourth memory cell be arranged, wherein in a direction substantially at right angles for the course of the bit lines, the selection transistor structures and the further transistor structures are arranged alternately.

preferred embodiments The invention will be described in detail below with reference to the accompanying drawings explained in more detail. It demonstrate:

1 a schematic representation of a resistance memory cell for use in a memory circuit;

2 FIG. 3 is a timing diagram illustrating the coupling of disturbances at a node between the selection transistor and the resistive memory element of the resistive memory cell; FIG.

3A a conventional memory circuit having a number of memory cells;

3B a layout of an integrated structure of the conventional memory circuit according to 3A ;

4 a schematic diagram of a memory cell according to an embodiment;

5A a memory circuit having a memory cell according to an embodiment of the invention;

5B a plan view of a layout of a substrate in which the memory circuit of 5A is implemented; and

6A to 6E Processes indicating the method of manufacturing a memory device according to another embodiment of the present invention.

In 1 Fig. 10 is a schematic diagram of a resistive memory cell 1 shown for use in a memory device. The resistance memory cell 1 includes a selection transistor 2 and a resistance memory element 3 connected in series between a bit line 4 and a plate element 5 are switched. The plate element 5 provides a predetermined plate potential that is set to a fixed plate potential value. In detail, a first terminal (source / drain) of the selection transistor 2 with the bit line and a second terminal (source / drain) of the selection transistor 2 via a node N to a first terminal of the resistive memory element 3 connected. A second terminal of the resistor storage element 3 is with the plate element 5 connected. A gate terminal of the selection transistor 2 is with a wordline 6 on which an activation signal can be applied to the selection transistor 2 to make conductive or non-conductive.

The resistance memory element 3 is formed as a CBRAM memory element having a solid electrolyte material disposed between an anode and a cathode. The anode comprises a material that can migrate into or be removed from the solid state electrolyte material, depending on the sign and strength of an electric field applied across the electrodes. The cathode is made of an inert material.

The resistance memory element 3 can be set to different resistance states, eg. To a low resistance state with a low resistance and a high resistance state with a high resistance. In the high resistance state, the resistance memory element 3 a resistance in the range of 1 to 10 MOhm, so that the node N is connected to the plate member through this resistor. In a state where the resistive memory element 3 is in the high resistance state and the selection transistor 2 is not conducting, the node N is floating between the selection transistor 2 and the resistance memory element 3 , so that disturbances can be coupled into it, which leads to a constant potential change at the node N.

The disturbances at node N may cause the voltage drop across the resistive memory element 3 occurs, which may lead to a decrease in the resistance of the resistance state, so that a logic state associated with the resistance state changes and the stored information is undesirably modified.

As in the signal-time diagram of 2 is shown, a level transition of the activation signal on the word line (word line voltage) may inject such a disturbance at the node N. When dependent on the activation signal of the selection transistor 2 becomes conductive, the node N does not float, so that a disturbance caused by a level crossing on the word line has no significant effect on the voltage drop across the resistive memory element 3 Has. When the level transition of the activation signal is the selection transistor 2 the node N blocks, the node N floats, so that the level transition of the activation signal is coupled to the potential of the node N, resulting in a voltage drop across the resistive memory element 3 leads. Depending on the direction of the voltage drop, the voltage drop may lead to a drop in the resistance, thereby changing the logic state associated therewith, so that the information stored in the memory cell is undesirably changed. Even if the voltage drop does not result in a significant change in resistance, the coupling of an interference potential can repeatedly lead to a degradation of the information stored in the memory cell, ie a resistance drop which makes it more difficult to store the information stored in the corresponding memory cell to detect.

In the 3A is a memory cell array 10 representing a number of word lines 6 ₁ to 6 ₄ and a number of bit lines 4 ₁ and 4 ₂ has, at each of which resistance memory cells can be arranged. In the illustrated example, there are two resistive memory cells 1 ₁ and 1 ₂ with the first bit line 4 ₁ and two resistive memory cells 1 ₃ and 1 ₄ with the second bit line 4 ₂ connected. In detail, the two resistive memory cells 1 at the first bit line 4 ₁ arranged so that the first terminals of the respective selection transistors 2 together with the first bit line 4 ₁ are connected and connected with their gate terminals to two adjacent word lines. The gate terminals are connected to the third word line 6 ₃ and with the fourth word line 6 ₄ connected. The second terminals of the resistive memory elements of the first and second resistive memory cells 1 ₁ and 1 ₂ are with the plate element 5 connected in different places.

At the second bit line 4 ₂ are a third and a fourth resistance memory cell 1 ₃ and 1 ₄ arranged. The first terminals of the respective selection transistors 2 are shared with the second bitline 4 ₂ connected, wherein the second terminals of the corresponding resistance memory elements 3 to the plate element 5 are connected at different positions. The second terminal of the resistance memory element of the first resistance memory cell and the second terminal of the resistance memory element 3 the fourth resistance memory cell 1 ₄ are connected to the plate element in the same place.

In 3B FIG. 12 is a schematic plan view of a layout of the memory device according to FIG 3A shown. It can be seen that a pair of two resistive memory cells, whose first terminals of the select transistors are commonly connected to the corresponding bitline, are offset from each other on two different bitlines, so that a kind of checkerboard pattern with respect to the arrangement of the pairs of resistive memory cells 1 ₁ and 1 ₂ such as 1 ₃ and 1 ₄ is reached. In detail, the plan view of the layout shows bitlines 4 ₁ and 4 ₂ that are about the active areas 15 extending the source / drain regions and the channel region of the respective selection transistors 2 represent. The active areas 15 across which the bit line extends are physically isolated from non-active regions and from the active regions over which an adjacent bit line extends by means of trench isolation (STI: Shallow Trench Isolation). Along one of the bit lines 4 ₁ . 4 ₂ In each second source / drain region, a connection element is provided which connects the corresponding source / drain region to a layer which comprises the resistance storage element. In every other source / drain region arranged along the bit line therebetween, the bit line is with the sour ce- / drain area connected. Thus, in the illustrated example, every fourth source / drain region along the bit line is connected to the bit line.

Thereby remains a source / drain region, which is not for contacting with a corresponding Resistor memory element still for a contact with the Bit line is used. The second bit line has the same Configuration, wherein the source / drain region, with the corresponding bit line is connected to a neigh th source / drain region over which the adjacent bit line extends, is unused. Thus, will an offset arrangement of the memory cells in the memory cell array intended.

To the problem of the disturbances that can be induced in the node N, when the selection transistor is not conductive and the resistive memory element 3 is in a high resistance state, another transistor is connected to node N. The further transistor connects node N to a predetermined potential, at least during the time when the selection transistor is nonconductive and the resistive memory element is in a high resistance state.

For example, it can be provided that the further transistor connects the predetermined potential at the node N during the period during which the selection transistor is not conducting. It is further preferred to connect the node N to the predetermined potential by means of the further transistor and to disconnect the node N from the predetermined potential after the selection transistor has become conductive. As a result, it can be achieved that the node N is always connected to a specified potential. To avoid the provision of a further predetermined potential, the plate potential provided by the plate member may be increased 5 is provided as the predetermined potential to be selected.

In detail, as in 4 shown, the more transistor 7 parallel to the resistance memory element 3 be switched so that he has the node N with the plate element 5 connects when the other transistor 7 becomes conductive and the node N of the plate element 5 disconnects when the more transistor 7 does not become conductive. In detail, the first terminal of the further transistor 7 with the node N and the second terminal of the further transistor 7 with the plate element 5 connected. A gate terminal of the further transistor 7 is with an adjacent second wordline 6 ' connected, the drive is selected so that the further transistor 7 can be controlled independently, without the selection transistors 2 of further memory cells, which are arranged on adjacent bit lines, activate and / or deactivate. This can be achieved in that the further transistors 7 are formed as field effect transistors of a depletion type, while the selection transistors 2 that with the first word line 6 are connected, as field effect transistors of an accumulation type are formed or vice versa.

In the example given, for controlling the selection transistor 2 the activation signal has a signal level of a first potential, e.g. B. a ground potential, and a second signal level of a second potential, for. B. have a high level, wherein the selection transistor 2 becomes non-conductive when the first potential is applied and becomes conductive when the second potential is applied. As the further transistor 7 of the depletion type results in the application of a first potential to the adjacent wordline 6 ' to that the further transistor 7 becomes conductive and the selection transistor, which is arranged on the adjacent word line, is not yet conductive. Therefore, the node N becomes the non-addressed memory cell 1 in a quiescent state with the plate potential of the plate element 5 over the further transistor 7 connected. If the corresponding memory cell 1 must be addressed, the activation signal of the word line 6 from the first potential to a second potential, so that the selection transistor 2 becomes conductive. To now the other transistor 7 make non-conductive, without the further selection transistors of further memory cells connected to the adjacent word line 6 ' are arranged to make conductive becomes a third potential on the adjacent word line 6 ' created, which is selected to the other transistor 7 make non-conductive, without the selection transistor of the other memory cells on the adjacent word lines 6 ' to make conductive. The third potential therefore preferably has a sign that is different from the sign of the second potential with respect to the first potential. In other words, the first potential is in the range between the second potential and the third potential. General are the selection transistor 2 and the further transistor 7 designed so that when they are arranged on the same word line, the selection transistor 2 and the further transistor 7 can be put into a state in which both are nonconductive and can be put into states in which either the selection transistor 2 or the further transistor 7 are conductive, while the other is not conductive.

In general, the selection transistor 2 become conductive when the second potential is applied and does not become conductive when the first potential is applied, the further transistor can become conductive when the first potential is applied and can not become conductive when the third Po potential is created.

Farther is the selection transistor via a first word line and the further transistor via a second word line controlled. The third potential can be chosen so that the selection transistor is not conductive. this makes possible it that the second word line can also be used to one another selection transistor of a further resistance memory cell, which is arranged to control. It may be further provided be that the selection transistor is a field effect transistor of a Enrichment type and the other transistor is a field effect transistor is a depletion type, with the first potential in the range between the second and third potentials. This can be achieved that the further transistor and the selection transistor independently can be controlled from each other, even if they are arranged on the same word line by the first, second and third potential is applied.

In 5A an embodiment of the present invention is shown. Unlike the memory device of 3A are now at the crossing points of the wordlines 6 ₁ to 6 ₄ and bitlines 4 ₁ to 4 ₂ , not by the memory cells with respect to the embodiment of the 3A are occupied, more transistors 7 arranged by the appropriate word line 6 ₁ to 6 ₄ be controlled while the second terminals of the corresponding further transistors 7 with the plate element 5 are connected. This allows resistance memory cells 1 ₁ to 1 ₄ be provided, each one pair of a selection transistor 2 and another transistor 7 has, which are arranged side by side. The memory cells are alternately arranged along a bit line according to their structure, so that a first memory cell with a corresponding left word line 6 ₂ , at which the corresponding further transistor 7 is arranged and with a corresponding right word line 6 ₃ , at the corresponding selection transistor 2 is arranged and adjacent to a second memory cell, wherein the corresponding selection transistor to the corresponding left word line 6 ₂ and the corresponding further transistor 7 at the corresponding right word line 6 ₃ is arranged. This allows alternating pairs of two further transistors 7 and two select transistors 2 on each two adjacent word lines 6 ₁ to 6 ₄ along one of the bit lines 4 ₁ or 4 ₂ be arranged. Along one of the word lines 6 ₁ to 6 ₄ are another transistor 7 and a selection transistor 2 alternately arranged with respect to the respective bit line.

General is the control circuit 8th provided to apply the first, second and third potential to the first and second word lines and to a write or read potential on the bit line 4 to apply. The control circuit 8th It may be appropriate to apply the second potential to the first and second word lines in an idle state of the memory circuit, such that the selection transistors 2 are not conductive and the other transistors 7 are conductive to apply the predetermined potential to the resistive memory elements. For addressing the first resistance memory element, the control circuit is further configured, the first potential on the first word line 6 ₂ to apply to the selection transistor 2 make conductive to apply a bit line potential to the resistive memory element and the third potential to the second word line 6 ₃ apply to the other transistor 7 not to make it conductive. The applied third potential on the second word line 6 ₃ ensures that the second selection transistor 2 , which is connected to the second word line, remains non-conductive, so that the second resistance memory element 3 not addressed. For addressing a second of the resistance memory elements, the control circuit 8th be suitable, the first potential on the second word line 6 ₃ to make the second selection transistor conductive, to apply a bit line potential to the second resistive memory element, and the third potential to the first word line 6 ₂ in order to make the second further transistor non-conductive. The bit line potential is applied to the bit line 4 applied after the second more transistor 7 was made non-conductive to avoid a short circuit between the bit line and the plate element via the second further transistor.

As in 5B is shown and unlike 3B is the source / drain region that was previously a non-active region and therefore in the example of FIG 3B was unused, now with another connector 20 provided the corresponding source / drain region 16 with the plate element 5 combines. Furthermore, another active area 19 intended. To the other transistors 7 as field effect transistors of a depletion type in the further active region 19 provide, becomes the other active area 19 with a depletion implantation (indicated by the dotted line). Thus, the other transistors should 7 be formed as depletion transistors. The depletion implantation may be made by an implantation process, diffusion process and the like.

With reference to the 6A to 6E are process states for illustrating the manufacturing process of a memory device according to an embodiment of the invention shown. As in 6A shown is a semiconductor substrate 30 vorgese hen, in the source / drain areas 16 and channel areas 17 of the two select transistors in the active region 15 are arranged and in the further active area 19 are provided with a depletion implantation, in which two further transistors are arranged. Along the bit line (not shown) are the active areas 15 and the other active areas 19 arranged alternately. In the 6A to 6E the bit line extends parallel to the plane of the drawing, with the word lines 23 that over the corresponding channel areas 17 are arranged, extend substantially perpendicular to the bit line. Every second source / drain region located in the active region 15 is located with a connector 18 provided for contacting by an insulating signaling layer 21 in which mutually insulated signal lines are to provide a solid electrolyte material, which later forms the resistance storage element. Between two of the fasteners 18 in the corresponding source / drain region, that in the further active region 19 is the other connecting element 20 provided, which is preferably made with the same one or more method steps, with which the connecting element 18 was produced. The connecting elements 18 . 20 become by lithographic processes in the signaling layer 21 formed having an insulating material, for. As silica and the like., So that the connecting elements 18 . 20 free on the surface of the signaling layer 21 are contactable.

As in 6B is shown on the surface of the signaling layer 21 a solid electrolyte material 22 applied, z. B. deposited, so that a portion of each of the connecting elements 18 and the other connecting elements 20 to come in contact with it.

As in the proceedings of the 6C is shown, the solid electrolyte material 22 that the surface of the further connecting element 20 covered, away and as in 6D is shown, insulating elements (spacers) are provided on the side walls of the trenches thus formed, so that the further connecting elements 20 from the solid electrolyte material 22 separated and isolated. Thereafter, a conductive plate member material 23 applied to cover the cell array so that one electrode of the resistive memory element 3 formed with the solid electrolyte material, and an end of the further connection member 20 which is not covered by the solid electrolyte material, are contacted simultaneously with the plate member.

This creates a memory cell that is partially over the active area 15 and over the further active area 19 is arranged along a bit line.

Compared to the conventional one Storage device of this kind is defined by the area in which the Depletion implantation is provided, and which usually remains unused, no additional chip area needed to for every the resistance memory cells the corresponding further transistor provided.

1

Resistive memory cell

2

selection transistor

3

Resistive memory element

4

bit

5

Plate potential element

6

wordline

7

Another transistor

10

Memory cell array

15

active Area

16

Source / drain region

18

connecting element

17

channel area

19

active Area

20

additional connecting element

21

signaling layer

22

Solid electrolyte material

23

Wordline

Claims (27)

Memory circuit ( 1 ) with a resistance memory element ( 3 ), a bit line ( 4 ), one between the resistive memory element ( 3 ) and the bit line ( 4 ) arranged selection transistor ( 2 ), which is nonconductive in a quiescent state, around the resistive memory element ( 3 ) to separate from the bit line and which is conductive to addressing the resistive memory element to the resistive memory element ( 3 ) to connect to the bit line, and another transistor ( 7 ), characterized in that the further transistor ( 7 ) with a node (N) between the resistance memory element ( 3 ) and the selection transistor ( 2 ), and the selection transistor ( 2 ) and the further transistor are designed such that in the idle state to a predetermined potential across the further transistor ( 7 ) at the resistive memory element ( 3 ), the selection transistor ( 2 ) non-conducting and the further transistor ( 7 ) is conductive, and that for addressing the resistance memory element of the selection transistor ( 2 ) conductive and the further transistor ( 7 ) is non-conductive. A memory circuit according to claim 1, wherein the resistive memory element ( 3 ) comprises a programmable metallization cell. Memory circuit according to claim 1 or 2, characterized in that the selection transistor ( 2 ) is conductive when a first potential is applied and is non-conductive when a second potential is applied, the further transistor ( 7 ) is conductive when the second potential is applied and nonconductive when a third potential is applied. Memory circuit according to one of Claims 1 to 3, characterized in that the selection transistor ( 2 ) via a first word line ( 6 ) and the further transistor ( 7 ) via a second word line ( 6 ' ) is controlled. Memory circuit according to claim 4, characterized in that the third potential is chosen so that the selection transistor ( 2 ) is non-conductive. Memory circuit according to one of Claims 3 to 5, characterized in that the selection transistor ( 2 ) of an enrichment type and the further transistor ( 7 ) is of a depletion type, the first potential being provided in a range between the second and third potentials. Memory circuit according to one of Claims 4 to 6, characterized in that a control circuit ( 8th ) is provided to the first, second and third potential to the first and second word line ( 6 . 6 ' ) and a write or read potential on the bit line ( 4 ). Memory circuit according to claim 7, characterized in that the control circuit ( 8th ) is configured to, in the idle state, the second potential at the first and second word line ( 6 . 6 ' ), so that the selection transistor ( 2 ) non-conducting and the further transistor ( 7 ) is conductive, and to address the resistor memory element ( 3 ) the first potential at the first word line ( 6 ), so that the selection transistor is conductive, the third potential at the second word line ( 6 ' ), so that the further transistor ( 7 ) is non-conductive, and the write or read potential on the bit line ( 4 ). Memory circuit according to claim 8, characterized in that the control circuit ( 8th ) is adapted to the third potential on the second word line ( 6 ' ), either simultaneously or after the first potential has been applied to the first word line ( 6 ) has been created. Memory circuit according to one of claims 1 to 9, characterized in that a first terminal of the resistive memory element ( 3 ) with a first terminal of the selection transistor ( 2 ) and a plate element ( 5 ) with a second terminal of the resistance memory element ( 3 ) is connected to apply a plate potential, wherein a second terminal of the selection transistor ( 2 ) with the bit line ( 4 ) and wherein the further transistor ( 7 ) has a first terminal connected to the first terminal of the resistive memory element ( 3 ) and a second terminal to which the predetermined potential is applied. Memory circuit according to claim 10, characterized in that the second terminal of the further transistor ( 7 ) with the plate element ( 5 ) and the predetermined potential is the plate potential. Memory circuit according to one of claims 4 to 11, characterized in that a gate terminal of the further transistor ( 7 ) with the second word line ( 6 ' ) and a gate terminal of the selection transistor ( 2 ) with the first word line ( 6 ) are connected. Memory circuit according to one of Claims 1 to 12, characterized by the first and a second resistance memory element ( 3 ); the first and a second bit line ( 4 ₁ . 4 ₂ ); the first selection transistor ( 2 ) to the first resistive memory element ( 3 ), the first resistive memory element ( 3 ) with the first bit line ( 4 ₁ ) is connectable; a second selection transistor to connect the second resistive memory element ( 3 ), the second resistive memory element ( 3 ) is connectable to the second bit line; the first further transistor ( 7 ) connected to the first resistive memory element ( 3 ) is connected to the predetermined potential at the first node between the first selection transistor ( 2 ) and the first resistive memory element ( 3 ) and a second further transistor ( 7 ) connected to the second resistive memory element ( 3 ) is connected to the predetermined potential at a second node between the second selection transistor ( 2 ) and the second resistive memory element ( 3 ). Memory circuit according to claim 13, characterized in that the first word line ( 6 ) is provided to control the first selection transistor and the second further transistor, and the second word line ( 6 ' ) is provided to control the second selection transistor and the first further transistor. Memory device according to claim 13 or 14, characterized in that the second bit line is substantially parallel to the first bit line, wherein in one direction substantially at right angles to the course of the bit line, the selection transistors and the further transistors are arranged alternately. A memory device according to any one of claims 10 to 15, characterized by a semiconductor substrate comprising the selection transistor and the further transistor structure as a field effect transistor structure having first and second source / drain region and a gate terminal; a signaling layer ( 21 ) disposed on the semiconductor substrate and comprising the first bit line and the first and second word lines, a memory layer (14) 22 ) disposed on the signaling layer and comprising the resistive memory element as solid electrolyte material and the plate element disposed on the memory layer. Storage device according to claim 16, characterized in that a connecting element ( 18 ) in the signaling layer ( 21 ) an electrical contact between the one source / drain region of the selection transistor and the further transistor and the memory layer ( 22 ). Storage device according to claim 17, characterized in that a further connecting element ( 20 ) is provided, which connects the second source / drain region of the further transistor and the plate member with each other. Storage device according to one of claims 15 to 18, characterized in that the selection transistor as a Transistor structure of the enrichment type and the further transistor is provided as a depletion type transistor structure, wherein the two transistor structures in a doping well within the semiconductor substrate are arranged, wherein the doping well a to the semiconductor substrate has different doping concentration. Method for operating a memory circuit ( 1 ) with a resistance memory element ( 3 ), a bit line ( 4 ), one between the resistive memory element ( 3 ) and the bit line ( 4 ) arranged selection transistor ( 2 ), which is nonconductive in a quiescent state, around the resistive memory element ( 3 ) to separate from the bit line and which is conductive to addressing the resistive memory element to the resistive memory element ( 3 ) to connect to the bit line, and another transistor ( 7 ), characterized by the steps of opening the selection transistor ( 2 ) and closing the further transistor ( 7 ) in the idle state to a vorbe certain potential via the further transistor ( 7 ) to a node (N) between the resistive memory element ( 3 ) and the selection transistor ( 2 ) create; Close the selection transistor ( 2 ) and opening the further transistor ( 7 ) for addressing the resistor memory element ( 3 ). Method according to claim 20, characterized in that the selection transistor ( 2 ) becomes conductive when a first potential is applied and becomes non-conductive when a second potential is applied, the further transistor ( 7 ) becomes conductive when the second potential is applied and becomes nonconductive when a third potential is applied, wherein the third potential is selected so that the selection transistor becomes nonconductive. Method according to claim 20 or 21, characterized in that the selection transistor ( 2 ) via a first word line ( 6 ) and the further transistor ( 7 ) via a second word line ( 6 ' ) to be controlled. Method according to one of claims 20 to 22, characterized through the following steps: Providing a semiconductor substrate with a first memory cell, the selection transistor and the other Transistor includes, Provision of a signaling layer the semiconductor substrate, wherein the signaling layer is a first Includes bit line and first and second word lines, Provide a memory layer on the signaling layer comprising a solid state electrolyte material and Providing a plate element structure on the storage layer. A method according to claim 23, characterized in that the selection transistor and the further transistor are each provided with a first source / drain region, wherein a connecting element ( 18 ) is provided in the signaling layer, which establishes an electrical contact between the first source / drain regions and the memory layer. A method according to claim 24, characterized in that the further transistor is provided with a second source / drain region, wherein a further connecting element ( 20 ) connecting the second source / drain region and the plate element structure. Method according to claim 25, characterized in that the connecting element ( 18 ) and the further connecting element ( 20 ) in one or more identical process steps can be seen, wherein after the provision of the storage layer in at least the region which is arranged above the further connecting element, the storage layer is removed and arranged according to a plate element structure so that the further Ver connecting element comes into electrical contact with the plate element structure. Method according to claim 26, characterized in that that after removing the storage layer over the further connecting element a Side wall of the storage layer provided with an insulating layer is applied before the plate element structure is applied.