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DE102006011366B8 - Verfahren zum Zeit sparenden Testen von Bauteilpositionen auf einem Wafer, Tester und Prober - Google Patents

Verfahren zum Zeit sparenden Testen von Bauteilpositionen auf einem Wafer, Tester und Prober Download PDF

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Publication number
DE102006011366B8
DE102006011366B8 DE102006011366.7A DE102006011366A DE102006011366B8 DE 102006011366 B8 DE102006011366 B8 DE 102006011366B8 DE 102006011366 A DE102006011366 A DE 102006011366A DE 102006011366 B8 DE102006011366 B8 DE 102006011366B8
Authority
DE
Germany
Prior art keywords
prober
tester
wafer
time
component positions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102006011366.7A
Other languages
English (en)
Other versions
DE102006011366B4 (de
DE102006011366A1 (de
Inventor
Dipl.-Ing. Werner (FH) Müller
Dipl.-Ing. Josef (FH) Wimbauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Priority to DE102006011366.7A priority Critical patent/DE102006011366B8/de
Publication of DE102006011366A1 publication Critical patent/DE102006011366A1/de
Publication of DE102006011366B4 publication Critical patent/DE102006011366B4/de
Application granted granted Critical
Publication of DE102006011366B8 publication Critical patent/DE102006011366B8/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2887—Features relating to contacting the IC under test, e.g. probe heads; chucks involving moving the probe head or the IC under test; docking stations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE102006011366.7A 2006-03-09 2006-03-09 Verfahren zum Zeit sparenden Testen von Bauteilpositionen auf einem Wafer, Tester und Prober Expired - Fee Related DE102006011366B8 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102006011366.7A DE102006011366B8 (de) 2006-03-09 2006-03-09 Verfahren zum Zeit sparenden Testen von Bauteilpositionen auf einem Wafer, Tester und Prober

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102006011366.7A DE102006011366B8 (de) 2006-03-09 2006-03-09 Verfahren zum Zeit sparenden Testen von Bauteilpositionen auf einem Wafer, Tester und Prober

Publications (3)

Publication Number Publication Date
DE102006011366A1 DE102006011366A1 (de) 2007-09-13
DE102006011366B4 DE102006011366B4 (de) 2017-06-01
DE102006011366B8 true DE102006011366B8 (de) 2017-09-14

Family

ID=38336095

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102006011366.7A Expired - Fee Related DE102006011366B8 (de) 2006-03-09 2006-03-09 Verfahren zum Zeit sparenden Testen von Bauteilpositionen auf einem Wafer, Tester und Prober

Country Status (1)

Country Link
DE (1) DE102006011366B8 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018160557A1 (en) * 2017-03-03 2018-09-07 Aehr Test Systems Electronics tester

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6505138B1 (en) * 1999-10-28 2003-01-07 Credence Systems Corporation Function-based control interface for integrated circuit tester prober and handler devices
US20040162682A1 (en) * 2003-01-28 2004-08-19 Texas Instruments Incorporated Method and apparatus for performing multi-site integrated circuit device testing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6505138B1 (en) * 1999-10-28 2003-01-07 Credence Systems Corporation Function-based control interface for integrated circuit tester prober and handler devices
US20040162682A1 (en) * 2003-01-28 2004-08-19 Texas Instruments Incorporated Method and apparatus for performing multi-site integrated circuit device testing

Also Published As

Publication number Publication date
DE102006011366B4 (de) 2017-06-01
DE102006011366A1 (de) 2007-09-13

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
R082 Change of representative

Representative=s name: WESTPHAL, MUSSGNUG & PARTNER PATENTANWAELTE MI, DE

R082 Change of representative
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R082 Change of representative

Representative=s name: WESTPHAL, MUSSGNUG & PARTNER PATENTANWAELTE MI, DE

R020 Patent grant now final
R082 Change of representative
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee