DE102006019940B3 - Memory cell field of non volatile semiconductor memory cells, comprises semiconductor body with semiconductor zone of conductivity type, extending up to surface of body, where bit line is formed and buried in semiconductor zone - Google Patents

Abstract

The field comprises a semiconductor body (1) with a semiconductor zone (2) of a conductivity type, extending up to a surface (3) of the semiconductor body. A bit line (4) is formed and buried in the semiconductor zone and serves as source or drain regions. A channel area (5) is formed at the surface between two bit lines, where a dielectric layer pile (6) is formed on the channel area and serves as charge accumulating zone. A gate electrode (7) is formed on the dielectric layer pile, where the gate electrode is attached electrically to a word line (8). A space charge zone is formed in a space charge zone structure, during the operation of semiconductor memory cells. A minority carrier drain of other conductivity type is formed, in the semiconductor body, opposite to the former conductivity type. The minority carrier drain is arranged outside the space charge zone structure and is short circuited in the semiconductor zone.

Description

The The invention relates to a minority carrier sink for a Memory cell array of non-volatile semiconductor memory cells with minority carrier sink.

At the Operation of memory cell arrays with non-volatile memory cells such as For example, twin-flash memory cells form minority carriers within a semiconductor zone such as a well zone of the memory cells. The life of such Minority carrier is for example, in known memory cell fields of crystalline Silicon so big, that these can diffuse far microns before recombination done with a majority carrier. While this diffusion can the minority bearers too Interface states of a lower oxide layer of an ONO (oxide-nitride-oxide) storage layer reach from adjacent memory cells, are trapped there or even in the presence of corresponding electric fields injected into the nitride layer. This changes the state of charge within the ONO storage layer the adjacent memory cells, causing an undesirable loss of information brings with it.

WHERE 86/02202 A1 relates to a discharge protection for a charge storage depletion area. For this purpose, an apparatus and a method for shielding Semiconductor charge storage devices against the influence of particles or ionizing Radiation that absorbs within the volume of the semiconductor substrate be specified by providing a free carrier shield consisting of a buried layer with a very short life in the undisturbed Material below the depletion areas associated with the charge storage devices connected are. The very low lifetime coating is by ion implantation a supersaturated Zone of foreign substances such as oxygen, the deep recombination centers and chemically react with the substrate material provided, whereby thermally stable complexes are indicated, which during a downstream Do not cure implantation heating cycle.

US 2006/0049464 A1 relates to a stepped semiconductor device Dotierstoffgebieten. The predominant Number of semiconductor devices manufactured today according to this Reference to a uniform dopant concentration on, either along the lateral as well as the vertical active (and isolated) areas of the device. By grading the dopant concentration let yourself the performance in various semiconductor devices significantly improve. The improvements can be made in application-specific areas be achieved, for. B. an increase the operating frequency of digital logic, various power MOSFETS and IGBT ICs, an improvement in the refresh time for DRAMS, a reduction in programming time for non-volatile memory, a better visible quality including the pixel resolution and color sensitivity for Imaging ICs, a better sensitivity for varactors in tunable Filter, a higher Driver capability for JFETS.

Of the Invention is based on the object, a minority wear sink for a Memory cell array of non-volatile To specify semiconductor memory cells, the above in the context explained with the diffusion of minority carriers Counteracts problems.

These The object is achieved by a Memory cell array of non-volatile Semiconductor memory cells according to independent claims 1, 5 and 7 solved. Advantageous embodiments The invention are the subject of the dependent claims.

One In order to explain The invention relates to a memory cell array from non-volatile Semiconductor memory cells having a semiconductor body with one to one surface of the semiconductor body reaching semiconductor zone of a first conductivity type, within the Semiconductor zone formed and serving as source / drain regions buried bitlines, one on the surface between each two of the buried bitlines formed channel area, one on the Channel area formed and serving as a charge storage zone dielectric layer stack, one on the dielectric layer stack formed gate electrode, wherein the gate electrode electrically connected to a word line, a space charge zone structure, which comprises those regions within the semiconductor zone in which while the operation of the semiconductor memory cells form a space charge zone can, and at least one formed within the semiconductor body Minority carrier sink wherein the at least one minority carrier sink is outside the space charge zone structure is arranged and a smaller compared to the semiconductor zone Minority carrier lifetime having.

Of the Semiconductor body For example, Si, Ge, SiGe, SiC, III-V compound semiconductors such as GaAs or other semiconductor materials or compound semiconductors be educated. The buried ones serving as source / drain regions Bit lines are preferably formed as doped semiconductor regions and extend along the memory cell array along one Sequence of non-volatile Semiconductor memory cells.

Of the dielectric layer stack preferably has stacked one on top of the other dielectric layers, wherein at least one of these dielectric Layers chosen in such a way is that this serves as a charge storage layer. For example For example, the dielectric layer stack may be an ONO stack in which the nitride layer as a charge carrier storage layer serves. The gate electrode is preferably made of a conductive material formed and can for example consist of a doped semicon termaterial, from an intrinsic semiconductor material with sufficient intrinsic conductivity or even made of a metal. For example, the gate electrode formed of doped polycrystalline silicon. To the wordline Likewise, a sequence of semiconductor memory cells is connected. The word line can be made of the same material as the Gate electrode may be formed or else from one of the material the gate electrode different conductive material. As with the gate electrode may be, for example, a doped one Semiconductor material to an intrinsic semiconductor material at sufficient intrinsic conductivity or even a Trade metal. In an advantageous manner can be selected via selected bit lines and a Word line a particular semiconductor memory cell in the memory cell array drive.

The Space charge zone structure includes all areas within the semiconductor zone, in which form a space charge zone under operating conditions can. This may be, for example, one of the bit lines surrounding space charge zone at present voltage drop between bit line and semiconductor zone. Likewise possible space charge zone areas are detected thereby, due to a voltage drop between the gate electrode and the Semiconductor zone are due. The semiconductor zone may, for example, be a doped well zone be. The first conductivity type may be a p-type such that a second opposite thereto conductivity type is an n-type. It is also possible that the first conductivity type is an n-type and the second conductivity type is formed as a p-type is.

The Minority carrier sink represents an area or a collection of areas within the semiconductor body and has no overlap the space charge zone structure. This will ensure that no additional Leakage current is generated within the semiconductor zone.

at an advantageous embodiment is the minority carrier life within the at least one Minoritätsträ gersenke at least 10 times less than within the semiconductor zone. This is possible an undesirable Diffusion of minority carriers in adjacent semiconductor memory cells and in particular in the environment Counteract local charge storage zones.

Advantageous it is, if one of the minority carrier lifetimes corresponding diffusion length within the at least one minority carrier sink smaller than a distance adjacent memory cells is set. A reduction in the Minority carrier lifetime and thus a shortening the diffusion length from minority groups can be by elevating minority carrier recombination achieve within the at least one minority carrier sink. An increased recombination rate For example, by enlarging one Crystal defect density and thus the introduction of recombination centers or also by enlarging one Dopant concentration within the at least one minority carrier sink to increase be achieved by Auger recombination.

In Advantageously, the at least one minority carrier sink at least one deep impurity or a deep impurity distribution on. This leaves an intensified Achieve recombination, for example, by the so-called Shockley-read-Hall recombination model can be described.

at an embodiment the at least one minority carrier sink has at least one of the deep impurities causative elements of the group consisting of Au, Ge, Fe, Ni, Cu, C, Ta, V, Cd and Co on. When introducing such metallic impurities in the semiconductor body However, it is important to ensure that after inserting a or more of these elements during the further process flow still to be performed temperature budget no such strong outdiffusion of these elements leads that the electrical properties of the semiconductor memory cells thereby deteriorated become.

at a particularly advantageous embodiment, the at least a minority carrier sink at least partially an amorphous structure. The amorphous structure leads to a deep impurity distribution within an energy band gap of the semiconductor body and thus to the desired reinforcement the recombination. It is conceivable, the semiconductor zone from the surface to recrystallize into the semiconductor body to a certain depth, e.g. by laser crystallization, one below the recrystallized Area remaining amorphous area as minority carrier sink serves.

In a further advantageous embodiment, dislocations having a density of at least 10 ¹¹ cm ^{-2 are} formed within the at least one minority carrier sink. At displacements If increased recombination occurs and with dislocation densities above 10 ¹¹ cm ^-2 , a favorable reduction in minority carrier ^lifetime can be achieved.

In a further advantageous embodiment, the at least one minority carrier sink has a maximum dopant concentration of greater than 10 ¹⁷ cm ^-3 . For example, such high dopant concentrations lead to increased Auger recombination in silicon. The mechanism of Auger recombination can thus be used via the dopant concentration to adjust the minority carrier lifetime. The at least one minority carrier sink can be designed, for example, as a well zone implanted deep into the semiconductor body.

at a further advantageous embodiment, the at least a minority carrier sink embedded within the semiconductor zone.

According to one another preferred embodiment The invention is a memory cell array with non-volatile Semiconductor memory cells indicated with a semiconductor body with one to a surface of the semiconductor body reaching semiconductor zone of a first conductivity type, within the Semiconductor zone formed and serving as source / drain regions buried bitlines, one on the surface between each two of the buried bitlines formed channel area, one on the Channel area formed and serving as a charge storage zone dielectric layer stack, one on the dielectric layer stack formed gate electrode, wherein the gate electrode electrically is connected to a word line, a space charge zone structure, the includes those regions within the semiconductor zone in which while the operation of the semiconductor memory cells form a space charge zone can, at least one formed within the semiconductor body minority carrier sink from one to the first conductivity type opposite second conductivity type, wherein the at least one minority carrier sink is outside the space charge zone structure is arranged and shorted to the semiconductor zone.

Consequently can the minority bearers like in a solar cell in the short circuit over a between the at least a minority bearer sink and the semiconductor zone built-in electric field in an advantageous Be vacuumed way.

at a further advantageous embodiment, the at least a minority carrier sink and the semiconductor zone over an electrical connection outside of the semiconductor body shorted. For example, the semiconductor zone as also the at least one minority carrier sink over the surface contacted, e.g. with a conductive contact plug and connected to a common metal level and thus be shorted. The at least one minority carrier sink within of the semiconductor body can, for example, over another semiconductor zone of the same conductivity type are led to the surface, e.g. over one so-called buried layer. Likewise, the at least one minority wear sink for example about a trench with conductive filling material to the surface guided become.

alternative For this purpose it may also be advantageous if the at least one Minority bearer sink and the semiconductor zone within the semiconductor body are short-circuited. Such a short circuit between these two zones can for example via a Silicide can be provided within the semiconductor body. It is also possible to have one Short circuit due to charge carrier tunneling at a correspondingly high dopant concentration in a transition region provided for this purpose provide.

In Advantageously, the at least one minority wear sink and the semiconductor zone connected to a lower supply voltage. at the lower supply voltage may be, for example, a Ground (GND), ground or earth potential act.

In a further advantageous embodiment, a memory cell array of non-volatile semiconductor memory cells is provided with a semiconductor body having a reaching to a surface of the semiconductor body semiconductor zone of a first conductivity type, formed within the semiconductor zone and serving as source / drain regions buried bit lines, one at the Surface between each two of the buried bit lines formed channel region, a formed on the channel region and serving as a charge storage zone dielectric layer stack, formed on the dielectric layer stack gate electrode, wherein the gate electrode is electrically connected to a word line, a space charge zone structure comprising those areas within the semiconductor zone in which a space charge zone can form during the operation of the semiconductor memory cells, and at least one inside the semiconductor body formed minority carrier sinks of a second conductivity type opposite to the first conductivity type, wherein the at least one minority carrier sink outside the space charge zone structure is arranged floating. Thus, the at least one minority carrier sink is connected to no defined potential, ie this is potential-free. For example, the little ones at least one minority carrier sink is entirely surrounded by a semiconductor zone of the opposite first conductivity type.

In Advantageously, the at least one minority carrier sink embedded within the semiconductor zone. Such an embedding let yourself for example, by a deep implantation to form the Achieve sink.

at a further advantageous embodiment of the invention a memory cell array of non-volatile semiconductor memory cells indicated with a semiconductor body with one to a surface of the semiconductor body reaching semiconductor zone of a first conductivity type, within the Semiconductor zone formed and serving as source / drain regions buried bitlines, one on the surface between each two of the buried bitlines formed channel area, one on the Channel area formed and serving as a charge storage zone dielectric layer stack, one on the dielectric layer stack formed gate electrode, wherein the gate electrode electrically is connected to a word line, a space charge zone structure, the includes those regions within the semiconductor zone in which while the operation of the semiconductor memory cells form a space charge zone can, and at least one formed within the semiconductor body Minority carrier sink of one to the first conductivity type opposite second conductivity type, wherein the at least one minority carrier sink is outside the space charge zone structure is arranged and the semiconductor zone to a relative to at least a minority bearer sink in the range of -2 V is connected to 0 V or 0 V to 2 V, If the semiconductor zone of the p-conductivity type or n-type conductivity is. Thus, the semiconductor zone is opposite to the at least one minority carrier sink Poled in the reverse direction. While on the one hand a secondary generation slightly increased by minority bearers on the other hand, as a result of the at least one Minority carrier sink to the surface expanding more space charge zone structure a more effective Extraction of the minority carrier achieved become.

at A further advantageous embodiment is the voltage between the semiconductor zone and the at least one minority carrier sink adjustable. Dependent From the operating state of the memory cell array can thus an advantageous Extraction of the minority carrier achieved become.

In Advantageously, the at least one minority carrier sink in this case connected to a lower supply voltage.

at a further embodiment are the non-volatile Semiconductor Memory Cells Twin Flash Memory Cells.

at a further advantageous embodiment, the at least a minority carrier sink arranged as a plurality of at regular intervals individual minority bearers sinking educated. The distance of the adjacent individual minority carrier sinks for example, can match be selected to the distance between adjacent semiconductor memory cells. It is particularly advantageous if the individual minority carriers sink without a specially for this provided lithographic mask can be trained. For example, could the individual minority bearer sinks over one Implantation step with the help of an inherent in the process Source / drain mask can be formed. Of course it is it is also possible to train the individual minority bearer sinks to use suitable masks. Thus, the individual minority bearers can sink formed congruent with other semiconductor zones within the semiconductor body become.

Further Aspects and advantages of the invention will become apparent from the following detailed Description in conjunction with the accompanying drawings clarified. Show it:

1A and B is a schematic cross-sectional view and a schematic plan view of a section of a memory cell array of known non-volatile semiconductor memory cells;

2 a schematic cross-sectional view of a section of a memory cell array of nonvolatile semiconductor memory cells according to a first embodiment of the invention;

3 a schematic cross-sectional view of a section of a memory cell array of nonvolatile semiconductor memory cells according to a second embodiment of the invention;

4 a schematic cross-sectional view of a section of a memory cell array of non-volatile semiconductor memory cells according to a third embodiment of the invention;

5 a schematic cross-sectional view of a section of a memory cell array of nonvolatile semiconductor memory cells according to a fourth embodiment of the invention.

In 1A FIG. 12 is a schematic cross-sectional view of a portion of a memory cell array of known nonvolatile semiconductor memory cells. FIG. Within a semiconductor body 1 is a semiconductor zone 2 up to one surface 3 of the semiconductor body 1 educated. Within the semiconductor zone 2 are adjacent bit lines and serving as source / drain regions 4 educated. Between adjacent bit lines 4 lies a channel area 5 , On the canal area 5 is a dielectric layer stack 6 shown in simplified form. The dielectric layer stack 6 For example, it may be formed as an ONO (oxide-nitride-oxide) layer sequence and serves as a charge storage region. On the the lektrischen layer stacks 6 lies a gate electrode 7 which is connected to a simplified word line 8th connected. The word line 8th is with a plurality of gate electrodes 7 a sequence of sequentially arranged memory cells connected. In this case, a memory cell becomes, for example, via two adjacent bit lines 4 as respective source and drain region as well as the intermediate channel region 5 , the dielectric layer structure 6 and the gate electrode 7 educated. Like the one in 1A shown section of the memory cell array is shown, serves approximately the middle of the three illustrated bit lines 4 as a common source / drain region of a left or right to said bit line 4 adjacent semiconductor memory cell. The semiconductor zone 2 is shown in simplified form connected to a lower supply voltage GND. Such a connection can, for example, by means of a semiconductor zone 2 over the surface 3 contacting dummy word line are provided. It is assumed that a minority carrier (simplified as "-" marked) was created at location A. The minority carrier can now diffuse to an adjacent memory cell to the schematically marked location B and there in the presence of electric fields in a charge storage layer of the dielectric layer stack 6 reach. This may change the memory state of the corresponding memory cell.

In 1B is a schematic view of the in 1A shown as a cross-section memory cell array. Here the bit lines run 4 perpendicular to the word lines 8th wherein the dimensions of a single memory cell 9 are schematically indicated. The single memory cell 9 can thus be via an associated word line 8th as well as over two associated bitlines 4 drive.

In 2 FIG. 12 is a schematic cross-sectional view of a portion of a memory cell array of non-volatile semiconductor memory cells according to a first embodiment of the invention. FIG.

Components compatible with those of the known memory cell array in 1A agree to be in 2 as well as in the other figures with the same reference numerals and a renewed description derselbigen is omitted. Here is the description of the 1A directed.

The memory cell array has a space charge zone structure 10 on, thereby reducing those areas within the semiconductor zone 2 be characterized in which can form a space charge zone during operation of the semiconductor memory cells. Outside the space charge zone structure 10 and deeper within the semiconductor body 1 located is a minority carrier sink 11 educated. The minority bearer sink 11 indicates one of the conductivity type of the semiconductor zone 2 opposite conductivity type. For example, the semiconductor zone 2 p-type and minority carrier sinks 11 be of the n-type. The minority bearer sink 11 adjoins down to another semiconductor zone 2 ' at. The further semiconductor zone 2 ' is of the same conductivity type as the semiconductor zone 2 , For example, the semiconductor zone 2 and the further semiconductor zone 2 ' be designed as a common tub zone, so that the minority carrier sink 11 embedded in it. Such an embedding of minority carrier sinks 11 can be achieved for example via a deep implantation. The semiconductor zone 2 , the minority carrier sink 11 as well as the further semiconductor zone 2 ' are short-circuited and connected to a lower supply potential GND. An Indian 2 simplified illustrated shorting the zones 2 . 11 . 2 ' can, for example, within the semiconductor body 1 respectively. Likewise, the zones can 2 . 11 . 2 ' also outside the semiconductor body 1 be short-circuited, for example by means of a metal level and contact plugs. In the transition area between the minority bearer sink 11 and the semiconductor zone 2 as well as the minority carrier sink 11 and the further semiconductor zone 2 ' despite the short-circuited areas forms another space charge zone structure 10 ' with a built-in electric field. A minority carrier generated at location A can thus at location B via the built-in electric field of the further space charge zone structure 10 ' be sucked off. This makes it possible to counteract a diffusion of the minority charge carriers to adjacent memory cells.

In 3 FIG. 12 is a schematic cross-sectional view of a portion of a memory cell array of non-volatile semiconductor memory cells according to a second embodiment of the invention. FIG. Unlike in 2 shown first embodiment, the minority carrier sink 11 floating, ie potential-free, are formed. Likewise, the minority bearer sink 11 For example, be designed as a zone with recombination centers. In this case, it is not necessary for the minority carrier sink to be one of the semiconductors zones 2 . 2 ' having different conductivity type, which in the former case of floating minority carrier sinks 11 however, given. A reduction in minority carrier lifetime can be achieved by increased recombination at recombination centers within the minority carrier sinks, for example by means of so-called lifetime killers, such as Au, or crystal defects, such as dislocations. As already in connection with the first embodiment in 2 For example, by lowering the minority carrier lifetime, it is made more difficult for a minority carrier generated at location A to diffuse to an adjacent memory cell because the minority carrier at location B is diffused by the minority carrier sink 11 can be sucked off.

In 4 FIG. 12 is a schematic cross-sectional view of a portion of a memory cell array of nonvolatile semiconductor memory cells according to a third embodiment of the invention. FIG. Unlike in the 2 and 3 In the first and second embodiments shown, the third embodiment of the invention has individual ones within the semiconductor zone 2 embedded minority bearers sinking 11 ' on. The semiconductor zone 2 is connected to the lower supply voltage GND. The individual minority bearers ken 11 ' are arranged at regular intervals. The positioning of the individual minority bearers 11 ' coincides with the arrangement of the bit lines 4 , Preferably, for the formation of one for the bit lines 4 provided mask used. The individual minority bearers sinking 11 For example, have one compared to the semiconductor zone 2 increased concentration of recombination centers on. The recombination centers can be formed for example by so-called lifetime killers such as Au or by crystal defects such as dislocations. Likewise, it is conceivable that the individual minority carrier sinks are floating semiconductor regions of one compared to the semiconductor zone 2 form opposite conductivity type.

In 5 FIG. 12 is a schematic cross-sectional view of a portion of a memory cell array of nonvolatile semiconductor memory cells according to a fourth embodiment of the invention. FIG. Unlike in the 2 shown first embodiment, the semiconductor zone 2 a potential in the range of -2V to 0V. It is assumed that the semiconductor zone 2 as well as the further semiconductor zone 2 ' of the p-conductivity type. The minority carrier sink is of the n-conductivity type. Thus, there is a pn junction between the semiconductor zone 2 and the minority carrier sink 11 poled in the reverse direction, which is why the further semiconductor zone structure 10 ' up into the semiconductor zone 2 extends into it and a better suction of minority carriers is possible. A limitation of the bias voltage of the semiconductor zone 2 to voltages up to -2V makes it possible to keep a generation of secondary minority carriers at a harmless for the operation of the memory cells level.

1

Semiconductor body

2

Semiconductor zone

2 '

Further Semiconductor zone

3

surface

4

bit

5

channel area

6

dielectric layer stack

7

gate electrode

8th

wordline

9

separate memory cell

10

Space charge zone structure

10 '

Further Space charge zone structure

11

Minority carrier sink

11 '

separate Minority carrier sinks

Claims (12)

Memory cell array of nonvolatile semiconductor memory cells comprising: a semiconductor body ( 1 ) with one to a surface ( 3 ) of the semiconductor body ( 1 ) semiconductor zone ( 2 ) of a first conductivity type; within the semiconductor zone ( 2 ) and buried bit lines serving as source / drain regions ( 4 ); one on the surface ( 3 ) between each two of the buried bit lines ( 4 ) formed channel area ( 5 ); one on the channel area ( 5 ) and serving as a charge storage zone dielectric layer stack ( 6 ); one on the dielectric layer stack ( 6 ) formed gate electrode ( 7 ), wherein the gate electrode ( 7 ) electrically to a word line ( 8th ) connected; a space charge zone structure ( 10 ), those areas within the semiconductor zone ( 2 ), in which a space charge zone can form during the operation of the semiconductor memory cells; and at least one within the semiconductor body ( 1 ) trained minority bearer sinks ( 11 ) of a second conductivity type opposite to the first conductivity type, wherein the at least one minority carrier sink ( 11 ) outside the space charge zone structure ( 10 ) and with the semiconductor zone ( 2 ) is shorted. Memory cell array according to claim 1, characterized in that the at least one minority carrier sink ( 11 ) and the semiconductor zone ( 2 ) via an electrical connection outside the semiconductor body ( 1 ) are shorted. Memory cell array according to claim 1, characterized in that the at least one minority carrier sink ( 11 ) and the semiconductor zone ( 2 ) within the semiconductor body ( 1 ) are shorted. Memory cell array according to one of claims 1 to 3, characterized in that the at least one minority carrier sink ( 11 ) and the semiconductor zone ( 2 ) are connected to a lower supply voltage (GND). Memory cell array of nonvolatile semiconductor memory cells comprising: a semiconductor body having one to a surface ( 3 ) of the semiconductor body ( 1 ) semiconductor zone ( 2 ) of a first conductivity type; within the semiconductor zone ( 2 ) and buried bit lines serving as source / drain regions ( 4 ); one on the surface ( 3 ) between each two of the buried bit lines ( 4 ) formed channel area ( 5 ); one on the channel area ( 5 ) and serving as a charge storage zone dielectric layer stack ( 6 ); one on the dielectric layer stack ( 6 ) formed gate electrode ( 7 ), wherein the gate electrode ( 7 ) electrically to a word line ( 8th ) connected; a space charge zone structure ( 10 ), those areas within the semiconductor zone ( 2 ), in which a space charge zone can form during the operation of the semiconductor memory cells; and at least one within the semiconductor body ( 1 ) trained minority bearer sinks ( 11 ) of a second conductivity type opposite to the first conductivity type, wherein the at least one minority carrier sink ( 11 ) outside the space charge zone structure ( 10 ) is arranged floating. Memory cell array according to claim 5, characterized in that the at least one minority carrier sink ( 11 ) within the semiconductor zone ( 2 ) is embedded. Memory cell array of nonvolatile semiconductor memory cells comprising: a semiconductor body ( 1 ) with one to a surface ( 3 ) of the semiconductor body ( 1 ) semiconductor zone ( 2 ) of a first conductivity type; within the semiconductor zone ( 2 ) and buried bit lines serving as source / drain regions ( 4 ); one on the surface ( 3 ) between each two of the buried bit lines ( 4 ) formed channel area ( 5 ); one on the channel area ( 5 ) and serving as a charge storage zone dielectric layer stack ( 6 ); one on the dielectric layer stack ( 6 ) formed gate electrode ( 7 ), wherein the gate electrode ( 7 ) electrically to a word line ( 8th ) connected; a space charge zone structure ( 10 ), those areas within the semiconductor zone ( 2 ), in which a space charge zone can form during the operation of the semiconductor memory cells; at least one within the semiconductor body ( 1 ) trained minority bearer sinks ( 11 ) of a second conductivity type opposite to the first conductivity type, wherein the at least one minority carrier sink ( 11 ) outside the space charge zone structure ( 10 ) and the semiconductor zone ( 2 ) to a relative to at least one minority carrier sink ( 11 ) in the range of -2V to 0V or 0V to 2V voltage is connected, if the semiconductor zone ( 2 ) is of the p-conductivity type or n-type conductivity. Memory cell array according to claim 7, characterized in that the voltage between the semiconductor zone ( 2 ) and the at least one minority carrier sink ( 11 ) is controllable. Memory cell array according to claim 7 or 8, characterized in that the at least one minority carrier sink ( 11 ) is connected to a lower supply voltage. Memory cell array according to one of the preceding Claims, characterized in that the non-volatile semiconductor memory cells are twin-flash memory cells are. Memory cell array according to one of the preceding claims, characterized in that the at least one minority carrier sink ( 11 ) as a plurality of regularly spaced individual minority carrier sinks ( 11 ' ) is trained. Memory cell array according to claim 11, characterized in that the individual minority carriers sink ( 11 ' ) congruent with other semiconductor zones within the semiconductor body ( 1 ) lie.