DE102006004627B3 - Power semiconductor device with charge compensation structure and method for producing the same - Google Patents

Abstract

The invention relates to a power semiconductor component with a charge compensation structure (3) and a method for producing the same. The power semiconductor component (1, 2) has a drift path (5) between two electrodes in a monocrystalline semiconductor body (4). The drift path (5) has drift zones (9) of a first conductivity type, which provide a current path (16) between the electrodes in the drift path (5) and charge compensation zones (11) of a conductivity type complementary to the first conductivity type, which form the current path of the drift path (5) constrict. The zones of the drift path (5) have diffusion-inhibiting areas (23) with diffusion-inhibiting imperfections and / or with diffusion-inhibiting point defects for at least one of the conduction types, the diffusion-inhibiting areas (23) being arranged in such a way that they the charge compensation zones (11) in their lateral Limit extension.

Description

The invention relates to a power semiconductor device with charge compensation structure and method for producing the same. The power semiconductor element has a drift path between two electrodes in a monocrystalline semiconductor body, as is known from the document DE 103 40 131 is known. The drift path has drift zones of a first conductivity type which provide a current path between the electrodes in the drift path and charge compensation zones of a conductivity type complementary to the first conductivity type, which narrow the current path of the drift path.

One Disadvantage of this known power semiconductor element is that the compensation zones are columnar are and with their complementary impurity in the manufacture in addition to a vertical diffusion in the construction of compensation columns also subject to horizontal diffusion, and thus the drift zones stronger constrict it as oppressive lateral diffusion possible is. By this to a certain extent uncontrolled narrowing of the Drift zones of a drift path will further reduce the On resistance of such a power semiconductor element hindered in the form of a so-called "CoolMOS".

For the circuit breaker "CoolMOS" as well as for others novel concepts of power semiconductor elements therefore exists the problem of an undesirable Dopant diffusion, which an improvement of the electrical Properties of the power semiconductor elements counteracts, especially the for the Kom pensationszonen used boron as an acceptor not only vertically diffused, but also lateral, so that the n-type current path narrows in the on state of the power semiconductor element, which leads to an increase of the on-resistance.

task The invention is a power semiconductor element with charge compensation structure and to provide methods of production with which the on-resistance of such power semiconductor elements on than previously can be reduced.

Is solved this task with the independent ones Claims. Advantageous developments of the invention will become apparent from the dependent Claims.

According to the invention is a Power semiconductor element with charge compensation structure indicated, wherein the power semiconductor element in a monocrystalline semiconductor body Has drift path between two electrodes. The drift path in turn has drift zones of a first conductivity type which has a current path between the electrodes in the drift path, and charge compensation zones a type of line complementary to the first type of line, comprising the current path of the Narrow down the drift path. The zones of the drift path have diffusion-inhibiting Areas with diffusion-inhibiting impurities and / or with diffusion-inhibiting Point defects for one of the conductivity types, wherein the diffusion-inhibiting regions are arranged so that they the charge compensation zones in limit their lateral extent.

One Such power semiconductor element has the advantage that by the diffusion-inhibiting regions cause lateral outdiffusion of Impurities out For example, charge compensation zones in areas of planned Drift zones is almost suppressed, so that slimmer compensation zones feasible are. This in turn has the advantage that the on-resistance can be further reduced.

In a preferred embodiment The invention relates to the drift zones and the charge compensation zones arranged vertically so that the drift path with arbitrarily large cross-section to enlarge the live Drift zones can be produced, which also reduces the on-resistance.

Farther it is provided that the semiconductor body is a highly doped substrate the first or the complementary Has conductivity type on which a weak to medium doped Epitaxial layer of the first conductivity type arranged with the drift path is. Due to the high doping of the substrate continues to the on-resistance reduced such a power semiconductor element. Only the epitaxial layer that for the reverse voltage resistance must have a predetermined thickness, is medium to weakly doped.

In a further preferred embodiment the invention, the semiconductor body on the highly doped Substrate a non-structured, weakly doped base epitaxial layer of the first conductivity type, which is free of charge compensation zones is. This base epitaxial layer improves the blocking behavior of a such power semiconductor element.

Depending on whether or not a base epitaxial layer is provided for the power semiconductor element, the charge compensation zones extend in their depth from an upper side of the semiconductor body to an upper side of the substrate or up to a top of the unstructured base epitaxial layer. The diffusion-inhibiting regions, which are arranged between the compensation zones in the region of the drift zones, have a thickness d in the range of 10 nm ≦ d ≦ 1 × 10 ⁴ nm, preferably in the range of 10 nm ≦ d ≦ 300 nm and in particular in the region of 10 nm ≤ d ≤ 150 nm. A thickness of 10 nm is already sufficient to impair the outdiffusion of impurities of the charge compensation zones during production in the drift zones.

To effectively hinder or inhibit diffusion, the diffusion-inhibiting regions have z. B. germanium, carbon and / or fluorine atoms as impurities on substitution grid sites of the monocrystalline semiconductor body. In particular, the diffusion-inhibiting regions have a monocrystalline layer having the composition Si _x Ge _y and / or Si _x Ge _y C _z , where x> y and x> z. Preferably, the diffusion-inhibiting regions have a composition of about 0 ≦ y ≦ 0.40 and about 0 ≦ z ≦ 0.25.

In a further preferred embodiment According to the invention, the diffusion-inhibiting regions have an increased concentration at lattice vacancies in the semiconductor material as point defects. Such increased Concentrations of lattice vacancies can, for. B. by implantation generated by protons or argon ions. It is also possible, more diffusion-promoting Regions by means of interstitially arranged semiconductor atoms as Provide point defects. In terstitiell arranged semiconductor atoms represent point defects that distort the silicon lattice and thus the diffusion coefficients of the impurity atoms in the silicon lattice influence.

The diffusion-inhibiting areas can on the one hand inhibit diffusion of acceptor ions from p-type regions and on the other hand, the diffusion of donor ions from n-type zones inhibit. Whether one mechanism or the other mechanism outweighs depends on the one hand of the size and the Condition of the foreign atoms, which cause a diffusion inhibition. Furthermore it depends on the type of lattice distortion, either by foreign atoms and / or can be triggered by point defects. In each Case it is possible diffusion-inhibiting and / or diffusion-promoting areas z. B. by Ion implantation, preferably in conjunction with subsequent high-temperature steps or through epitaxial growth to create an improvement the electrical properties of power semiconductor elements enable.

in the Process of "CoolMOS" produced today will be individual first p-type islands, also called "p-bubbles", between Epitaxial layers generated in subsequent diffusion processes diffuse in the vertical direction to corresponding p-type columns as charge compensation zones. In such processes may have the disadvantage that the boron, which acts as an acceptor in the silicon lattice is incorporated, not only diffused vertically, but also laterally, be prevented by that in a preferred embodiment invention, the diffusion-inhibiting regions laterally or orthogonally be arranged to the current path in the drift zones. This has the advantage that an improvement of the on-resistance to today's technologies narrower and slimmer p-type zones is possible. A scalability the power semiconductor elements is also advantageously given with the existing equipment. In addition, there are cost advantages in terms of of today's technologies.

A such embodiment The invention has charge compensation zones in epitaxial layers made up of layered structured and incorporated, in particular implanted and diffused columns of the complementary conductivity type consist. These charge compensation zones are surrounded by drift zones, in which epitaxial layerwise impurity atoms or point defects are arranged are. These form a diffusion-inhibiting lateral layer in the Diffusion zones and hinder a lateral spread of the charge compensation zones in the epitaxial layers and thus a broadening of the columns of the Charge compensation zones.

In a further preferred embodiment of the invention in the vertically extending drift zones highly doped and weakly doped horizontal areas are stacked on each other alternately, taking the highly doped areas arranged in the same vertical position are like heavily doped areas in adjacent charge compensation zones. This is done by deposition of undoped epitaxial layers reached, in which the n-doping by a subsequent implantation is introduced. The p- and the n-implantation are thus on same height in the respective epitaxial layers, which does not lead to a lower outdiffusion of the p-type dopant leads, however, the pn junction penetrates because of the higher n-dopant levels at the same level as the higher p-type dopant level less far into the n-conducting area of the drift zone. That means, that the p-type pillar of the Charge compensation zones remains slimmer than when using homogeneously doped n-type epitaxial layers.

A further improvement of the "CoolMOS" structure can be achieved in that a power semiconductor element is provided in which the diffusion-inhibiting areas are vertical and there be introduced parallel to the current path direction by walls of a trench structure are covered with corresponding diffusion-inhibiting areas. In this case, advantageously, a diffusion-inhibiting monocrystalline epitaxial layer with a thickness d in the range between 10 nm ≦ d ≦ 1 × 10 ³ nm, preferably in the range of 10 nm ≦ d ≦ 300 nm and in particular in the range of 10 nm ≦ d may be applied to the trench walls ≤ 150 nm grown from germanium-containing silicon. In particular, the germanium-containing silicon has a composition Si _x Ge _y with x> y and x ≦ 0.90 and y ≦ 0.40.

To can the drift zones monocrystalline on a highly doped monocrystalline Substrate grown in a trench structure semiconductor material or the charge compensation zones may be monocrystalline on the highly doped monocrystalline substrate in a trench structure Have grown semiconductor material. In both cases, the with a germanium containing silicon epitaxial layer occupied trench walls the Diffusion of impurities from the compensation zones into the diffusion zones and thus one hinder lateral spread of the compensation zones. Will not only the moat walls coated with a corresponding germanium-containing silicon layer, but also the trench bottom, this results in diffusion-inhibiting Areas that have a U-shape in cross section.

In a further preferred embodiment According to the invention, the drift zones in the trench structure have several in cross-section U-shaped diffusion-inhibiting regions which are stacked in one another, wherein between the diffusion-inhibiting regions monocrystalline Material of the first conductivity type is arranged. With this construction can both the avalanche behavior and the latch-up behavior of the Power semiconductor elements are improved. Finally exists also the possibility that several diffusion - inhibiting areas vertically and parallel to the Rung paths are arranged in the drift zones, between each of which strips of monocrystalline semiconductor material of the first conductivity type be provided.

In a further preferred embodiment According to the invention, the drift zone consists of several alternately arranged ones Regions of silicon of the first conductivity type and diffusion-inhibiting Areas.

In a further preferred embodiment The invention relates to charge compensation zones and drift zones in strips arranged side by side between the electrodes, wherein in each case a strip-shaped Drift zone of two strip-shaped Charge compensation zones in the direction of the current path across their width are limited to the current path. This striped pattern with in between arranged diffusion-inhibiting areas has the advantage that on a conventional pillar shape the compensation zones completely omitted can be.

One Method for producing power semiconductor elements with horizontal arranged diffusion-inhibiting areas in multiple epitaxial layers on a highly doped substrate has the following process steps on. First, will a heavily doped semiconductor wafer of a first or a complementary conductivity type with a plurality of power semiconductor device locations arranged in rows and columns as a substrate of a semiconductor body provided.

On In this substrate or semiconductor wafer, an epitaxial layer becomes monocrystalline grown up, which has the doping of the drift zones. After that a diffusion-inhibiting layer is produced by diffusion-inhibiting Impurities and / or point defects, such as vacancies in the epitaxial layer, preferably by ion implantation of foreign atoms such. B. protons or argon ions are introduced. On this epitaxial layer with diffusion-inhibiting layer becomes a photolithographic layer under release of surfaces for charge compensation zones applied. The diffusion-inhibiting layer is in the range of released surfaces preferably by etching or laser ablation removed. Subsequently, impurities are of the complementary Type of conductivity in the epitaxial layer in the area of the released surfaces brought in. Also for that Preferably, the ion implantation is used.

After that For example, the photolithographic layer can be removed, which is preferable by detaching the photolithographic layer or by ashing the photolithographic Layer is performed. These steps are now repeated several times until one for the dielectric strength the power semiconductor device sufficient thickness of a vertical Drift distance is reached. Thereafter, the semiconductor wafer is placed on a Diffusion temperature heated, being columnar, by diffusion-inhibiting Areas laterally limited charge compensation zones in the out Epitaxial layers constructed drift path in the power semiconductor device positions of the semiconductor wafer.

This method has the advantage that it provides power semiconductor elements in which the on-resistance is further reduced. In addition, the method has the advantage that a plurality of power semiconductor elements can be produced in parallel on a semiconductor wafer in corresponding power semiconductor element positions. at However, this method requires that the epitaxial layer already has the medium-high doping of the drift zones.

Becomes but worked with undoped growth of epitaxial layers, this results in a somewhat differentiated implementation example from this method. It will be first again a semiconductor wafer as a substrate with a variety of in lines and columns of arranged power semiconductor element positions for disposal posed. On this semiconductor wafer becomes a monocrystalline epitaxial layer grew up. In this implementation example The method is thereby added no dopant. The first Epitaxial layer (pedestal epitaxy) may also be considered low-doped layer of the first conductivity type become. In this epitaxial layer are then preferably by ion implantation Diffusion-inhibiting impurities and / or point defects, such as vacancy introduced by proton implantation or argon implantation. Thereafter, a photolithographic layer is applied to the epitaxial layer leaving open areas for charge compensation zones applied and structured.

In the released areas becomes the layer with diffusion-inhibiting impurities and / or point defects removed and then become impurities of the complementary Conduction type in the epitaxial layer in the area of exposed Introduced surfaces. Now the photolithographic layer can be removed and opened The entire semiconductor wafer will now be impurities for drift zone doping the epitaxial layers without dopant addition by ion implantation brought in. Drift zone doping can also be done before application the photolithographic layer or even before application the diffusion-inhibiting impurities and / or point defects produced become. These steps are repeated until one for the dielectric strength of the power semiconductor element sufficient thickness D of a vertical Drift distance is reached. Well, as in the first variant of the process, the semiconductor wafer to a diffusion temperature be heated to a columnar, through diffusion-inhibiting areas laterally limited charge compensation zone in the drift path built up from epitaxial layers, wherein simultaneously doping the drift zones in the power semiconductor device positions of the semiconductor wafer takes place. In this differentiated implementation example the diffusion-inhibiting effect may mainly affect the dopant the charge compensation zones act while the dopant of the drift zone in its vertical outdiffusion may be disturbed relatively slightly.

are such semiconductor wafers are made, with the following additional Steps from the semiconductor wafers individual power semiconductor elements made by now surface side structures and backside structures in and / or on the semiconductor wafer for completion of the power semiconductor elements in the power semiconductor element positions of the semiconductor wafer be realized, and then the semiconductor wafer in several Power semiconductor elements is separated.

The The second variant of this method supports the limitation of the charge compensation zones across from the drift zones by producing highly doped areas both in the charge compensation zones and in the adjacent ones Drift zones on the same epitaxial layer heights, so that the effect of diffusion-inhibiting layers is further supported by this measure.

is for a Power semiconductor element provided a base epitaxial layer, so this may be before the growth of a middle-doped epitaxial layer of the first conductivity type on the semiconductor wafer by growth a lightly doped pedestal epitaxial layer of the first conductivity type getting produced. In the production of a diffusion-inhibiting Layer are as diffusion-inhibiting foreign atoms, preferably germanium ions and / or Carbon ions and / or fluorine ions by ion implantation in all or introduced individual epitaxial layers. The effect of diffusion-inhibiting Layer can be reinforced be that the diffusion-inhibiting impurities by means of a multi-stage Ion implantation with different ion implantation energy be introduced into the individual epitaxial layers. This is especially advantageous if the diffusion-inhibiting impurities have a low diffusion coefficient.

Preferably is used for introducing diffusion-inhibiting point defects, such as lattice vacancies, an implantation with argon ions and / or carried out with protons.

In Another aspect of the invention is a method of manufacture of power semiconductor elements, in which vertical diffusion-inhibiting Areas between the drift zones and the charge compensation zones to be provided. For this purpose, the method has the following Procedural steps on. First is again a heavily doped semiconductor wafer of a first or a complementary one Line type with a large number of rows and columns Power semiconductor device positions provided as a substrate of a semiconductor body.

Thereafter, an epitaxial layer whose Di corresponds to the required dielectric strength of the drift path, applied to the semiconductor wafer with a first or a complementary conductivity type as the starting material for the drift path. Thereafter, a trench structure having nearly vertical trench walls and a trench bottom is introduced into the epitaxial layer in the respective power semiconductor device positions. Thereafter, a diffusion-inhibiting region of a germanium-containing monocrystalline silicon layer is deposited on the semiconductor wafer, which can also be doped, in particular of the first conductivity type.

In order to arise both on the mesen as well as on the moat walls as well on the trench bottom of the trench structure corresponding diffusion-inhibiting Areas. Thereafter, by anisotropic free etching of the trench bottom of the trench structure and the tops of the mesen from epitaxial material of the germanium-containing Silicon layer freed. For anisotropic free etching of the bottom area of the Trench structure and / or top of mesen becomes a dry etching process, as well as for the introduction of the trench structure used in accordance with the above is used. Now, one can grow up to be complementary to the one Mesen doped epitaxial layer done filling the trench structure. This results in a vertical diffusion-inhibiting area the trench walls, which Diffusion hindered so that the dimensions of the planned Compensation zones hardly change. By filling up the trench structure with a doped epitaxial layer becomes the top the semiconductor wafer is extremely uneven, as deposited on the mesen such epitaxial layer becomes.

Therefore Preferably, a leveling of the top of the semiconductor wafer up to the drift distance from drift and charge compensation zones a semiconductor body with leveled top and flat back. Now this semiconductor body can go through Producing top structures and back structures in and / or on the semiconductor body for completing the power semiconductor elements in the power semiconductor device positions of the semiconductor wafer to be completed. Finally will the semiconductor wafer separated into individual power semiconductor components.

This Method has the advantage that no variety of epitaxial layers to structure each other, which is a considerable multiple Photolithographic effort means here through the trench structure is avoided. Instead of a monocrystalline deposition of diffusion-inhibiting areas of germanium-containing silicon the trench walls, can diffusion-inhibiting areas by introduction, preferably by Ion implantation of germanium, carbon or fluorine reached into the trench walls become. Also in this method, before growing up a Epitaxy layers a lightly doped pedestal epitaxial layer on the semiconductor wafer of the first conductivity type.

The described method leaves about it also apply to the variant of a multi-step epitaxy, so that the process block consisting of epitaxy, mesa etching, insertion diffusion-inhibiting layer, epitaxial filling, re-etching multiple times in succession is carried out.

In a preferred implementation of the method, prior to the growth of an epitaxial layer of the first conductivity type on the semiconductor wafer or on the pedestal epitaxy, a structured auxiliary layer is applied epitaxially in regions of the trench structure to be etched, which enables an etch stop and preferably Si _x Ge _y with x> y or Si _x Ge _y C _z with x> y and x> z. This has the advantage that during a subsequent etching of the trench structure, these layers act as etching stop layers. In this case, the composition of this auxiliary layer is preferably provided as 0.86 ≦ x ≦ 1, y ≦ 0.40 and z ≦ 0.25.

In a further embodiment of the Process is called etch stop an auxiliary layer of semiconductor oxide or semiconductor nitride provided, wherein the structure of the auxiliary layer in the areas to be etched Trench structure is applied in such a fine structure, that a lateral monocrystalline overgrowth of the fine structure within the trench becomes. Such etch stop layers have proven themselves in semiconductor technology and are used here, to define the etching to end the trench structure.

Around a trench structure composed of strips into which To introduce epitaxial layer of the first conductivity type, an etch mask on the semiconductor wafer with a striped pattern in the area of Drift path in the respective power semiconductor component positions applied by photolithography. The introduction of the trench structure can by both anisotropic and isotropic etching of the Trench structure done. For introducing a trench structure by means of an anisotropic etching becomes a reactive ion etching performed or a directed plasma etch intended. In this case, an end point detection by providing an etch stop layer, as described above, an advantage.

After the introduction of the trench structure and before the application of a diffusion-inhibiting area, the surfaces of the trench walls are chemically cleaned or the surface of the trench walls becomes dry Semiconductor wafer and thus also the trench walls oxidized and then wet-chemically etched the oxide layer, preferably with dilute or with buffered hydrofluoric acid, so that a prepared for the epitaxial growth surface is available in the trench structures.

Another way to prepare the trench walls for an epitaxial layer is, alternatively or additionally, to provide a hydrogen tempering step wherein the surface area of oxygen particles or atoms is reduced. If the trench structure is prepared accordingly, a diffusion-inhibiting region of a monocrystalline layer of germanium-containing silicon with a thickness d in nanometers in the range of 10 nm ≦ d ≦ 1 × 10 ³ nm, preferably in the range of 10 nm ≦ d ≦ 300 nm and especially in the range of 10 nm ≤ d ≤ 150 nm.

In a further preferred embodiment The invention also provides a diffusion-inhibiting area on the Maintain trench bottom. This results in a cross-sectionally U-shaped diffusion-inhibiting Area in the trench structure.

In a further embodiment of the Process become on the trench walls several monocrystalline Layers of germanium-containing silicon for diffusion-inhibiting areas alternately vertically aligned with doped silicon as diffusion zones produced. This results in a cross-section of a strip-shaped structure, in both the diffusion-inhibiting areas and the areas Contribute with drift zone doping to conduct electricity.

Farther it is envisaged that on the moat walls and on the trench bottom several monocrystalline layers of germanium-containing silicon for diffusion-inhibiting Areas alternately stacked with doped silicon be prepared as drift zones. This results in a stacking of U-shaped diffusion-inhibiting areas within the trench structure, what those already mentioned above Benefits.

One Problem with the technique of trench structures, the drift distance too structure, forms the requirement, which after filling up the Trench structure level relatively uneven top of the semiconductor wafer. This is preferably by a chemical mechanical polishing method (CMP) reached. Another possibility is that for leveling the top of the semiconductor wafer to a semiconductor body with flattened top and with a flat back first a leveling photoresist layer or a spin-on-glass layer the uneven top is applied.

The etch selectivity factor across from The semiconductor material of the drift path is for such spin-on-glass layers or photoresist layers in conjunction with the selected etching process or removal process with almost 1 chosen. Only then can be assumed that a leveling of the top of the semiconductor wafer to a semiconductor body with a flattened top can be done easily by the applied planarized photoresist layer or spin-on-glass layer and the epitaxial material is evenly etched back.

The The invention will now be described with reference to the accompanying figures.

1 to 8th show schematic cross sections through portions of a semiconductor wafer for the production of power semiconductor devices of a first aspect of the invention;

1 shows a schematic cross section through a portion of a semiconductor wafer as a monocrystalline silicon substrate of a power semiconductor device;

2 shows a schematic cross section through the semiconductor wafer according to 1 after growing a doped epitaxial layer;

3 shows a schematic cross section through the semiconductor wafer according to 2 after implantation of diffusion-inhibiting contaminants in the top of the epitaxial layer;

4 shows a schematic cross section through the semiconductor wafer according to 3 after forming a diffusion-inhibiting region on top of the epitaxial layer;

5 shows a schematic cross section through the semiconductor wafer according to 4 after exposure of an area and ion implantation of acceptor ions through the exposed area;

6 shows a schematic cross section through the semiconductor wafer after re-growth of an epitaxial layer;

7 shows a schematic cross section through the semiconductor wafer after multiple growth of an epitaxial layer;

8th shows a schematic cross section through a section of a semiconductor wafer in the region of a drift path of a power semiconductor device after formation of a columnar charge compensation zone;

9 to 16 show schematic Cross sections through portions of a semiconductor wafer for producing a variant of power semiconductor devices of the first aspect of the invention;

9 shows a schematic cross section through a portion of a semiconductor wafer as monocrystalline silicon substrate of a power semiconductor device;

10 shows a schematic cross section through the semiconductor wafer according to 9 after growing an undoped epitaxial layer;

11 shows a schematic cross section through the semiconductor wafer according to 10 after forming a diffusion-inhibiting region on top of the epitaxial layer;

12 shows a schematic cross section through the semiconductor wafer according to 11 after exposure of an area and ion implantation of acceptor ions through the exposed area;

13 shows a schematic cross section through the semiconductor wafer according to 12 after full-surface implantation of donor ions for doping the undoped epitaxial layer;

14 shows a schematic cross section through the semiconductor wafer according to 13 after re growing an undoped epitaxial layer;

15 shows a schematic cross section through the semiconductor wafer according to 14 after multiple growth of an undoped epitaxial layer;

16 shows a schematic cross section through the semiconductor wafer according to 15 in the region of a drift path of a power semiconductor component after formation of columnar compensation zones;

17 to 21 show schematic cross-sections through portions of a semiconductor wafer for the production of power semiconductor devices of a second aspect of the invention;

17 shows a schematic cross section through a portion of a semiconductor wafer with grown monocrystalline and middle doped silicon epitaxial layer;

18 shows a schematic cross section through the semiconductor wafer according to 17 after introducing a trench structure and applying a diffusion-inhibiting layer to the patterned semiconductor wafer;

19 shows a schematic cross section through the semiconductor wafer according to 18 after anisotropic etching of the diffusion-inhibiting layer to form diffusion-inhibiting regions;

20 shows a schematic cross section through the semiconductor wafer according to 19 after filling the trench structure with a complementary to the in 19 mesene doped monocrystalline epitaxial layer;

21 shows a schematic cross section through the semiconductor wafer according to 20 after leveling the top of the semiconductor body to form a drift path of a power semiconductor device having vertically disposed diffusion-inhibiting areas;

22 shows a schematic cross section of the semiconductor wafer after forming an alternative drift path structure;

23 shows a schematic cross section of the semiconductor wafer after forming a further alternative drift path structure;

24 shows a schematic cross section of the semiconductor wafer after forming a further alternative drift path structure;

25 shows a schematic cross section of the semiconductor wafer after forming a further alternative drift path structure.

The 1 to 8th show schematic cross sections through portions of a semiconductor wafer 22 for the production of power semiconductor components 1 a first aspect of the invention. Components with the same functions in the 1 to 8th are denoted by the same reference numerals and are not explained repeatedly.

1 shows a schematic cross section through a portion of a semiconductor wafer 22 as monocrystalline silicon substrate 12 a power semiconductor device. In this embodiment of the invention, the monocrystalline silicon substrate is 12 n ⁺ -type and thus heavily doped to minimize the on-resistance of the power semiconductor device. The semiconductor wafer 22 and thus also the silicon substrate 12 have a top 19 and a back 31 on.

2 shows a schematic cross section through the semiconductor wafer 22 according to 1 after growing a doped epitaxial layer 7 on the top 19 of the silicon substrate 12 , The Dopant concentration of the epitaxial layer 7 is lower than that of the silicon substrate and reaches a medium high concentration, with the conductivity type being the same as that of the silicon substrate 12 ,

3 shows a schematic cross section through the semiconductor wafer according to 2 after ion implantation of diffusion-inhibiting contaminants in the top 27 the epitaxial layer 7 , For such ion implantation z. B. germanium ions, carbon ions and / or fluorine ions from the top 27 the epitaxial layer 7 be implanted out. For impurities with a low diffusion coefficient, such as germanium, the ion implantation can be carried out in several stages with different implantation energy in order to achieve a sufficient depth and thickness d of the diffusion-inhibiting region. Another way to increase the diffusion rate of germanium, is to increase the introduced dose, because the diffusion rate of germanium and / or other impurities increases with their concentration.

Also other measures, which could affect the diffusion constant locally are possible, such as z. For example, local injection of silicon lattice vacancies for reduction the diffusion constant in the region where the lateral diffusion is suppressed should. It is also possible a local increase the diffusion constant in the area where the charge compensation zones should occur, for example, by injection from additional interstitial silicon.

By the reduction of the lateral diffusion of the pillars Dopants it is about it out possible, with reduced or equal waviness of the columns, the vertical diffusion across from to increase the lateral diffusion and thus the separation of the areas of the columnar charge compensation zones to improve from the drift zones.

4 shows a schematic cross section through the semiconductor wafer 22 according to 3 after making a diffusion-inhibiting area 23 on the top 27 the epitaxial layer 7 , As already mentioned above, the thickness d of this diffusion-inhibiting region can 23 be designed arbitrarily and preferably has a range in nanometers of 10 nm ≤ d ≤ 300 nm and in particular in the range of 10 nm ≤ d ≤ 150 nm.

5 shows a schematic cross section through the semiconductor wafer 22 according to 4 after exposing a surface 28 and ion implantation of acceptor ions through the exposed area 28 , Around this area 28 first, put on the top 27 the epitaxial layer 7 a photolithographically structured layer is applied, in which the surface 28 is released, so that by means of an etching step in the area of the surface 28 located diffusion-inhibiting layer 29 can be etched away.

Subsequently, the exposed area 28 used to accept in this area acceptor ions through the exposed area 28 to implant through. Boron ions preferably become through the exposed surface 28 introduced at a higher concentration than the concentration of the surrounding epitaxial material. These areas introduced by boron ion implantation 35 under the exposed area 28 are also called "bubbles". After introducing the acceptor ions through the exposed area 28 The photolithographically structured layer can be removed, so that the in 5 shown schematic cross section arises.

6 shows a schematic cross section through the semiconductor wafer 22 after re growing an epitaxial layer 7 and introducing impurity atoms as diffusion-inhibiting regions 23 and applying a photolithographically structured layer, which in turn is a surface 28 which leaves exactly above the already introduced acceptor ion area 35 is exposed so that again an ion implantation of acceptor ions to another so-called "p-bubble" can be performed.

7 shows a schematic cross section through the semiconductor wafer 22 after multiple growth of an epitaxial layer 7 until a total thickness D of the epitaxial layer required for the blocking capability of the power semiconductor device to be formed is reached. Through this layered structure of the epitaxial layers 7 become simultaneously diffusion-inhibiting areas 23 made laterally or horizontally along the tops of the epitaxial layers and surfaces 28 leave open, in which the so-called "p-bubbles" are to be provided for a diffusion of columnar compensation zones.

8th shows a schematic cross section through a section in the region of a drift path 5 a power semiconductor device 1 after forming columnar charge compensation zones 11 , Due to the diffusion-inhibiting areas 23 as they are in 7 are shown, the lateral diffusion of the p-type charge compensation zones 11 clearly limited, so that reliable a narrower or slender charge compensation zone column can be produced, thus improving the on-resistance of the power semiconductor device 1 connected is. In this embodiment of the invention reaches the charge compensation zone 11 in column form not up to the heavily doped silicon substrate 12 down, but has a depth t, which is at the top 21 a so-called base epitaxy layer 20 ends. The doping of the base epitaxial layer 20 may be less than the doping of the remaining epitaxial layers 7 and improves the avalanche behavior of the power semiconductor device 1 with the charge compensation structure 3 ,

The 9 to 16 show schematic cross sections through portions of a semiconductor wafer 22 for the production of power semiconductor components. This semiconductor wafer 22 forms a monocrystalline n-type and heavily doped silicon substrate 12 as a starting material for the power semiconductor component. This output material of the power semiconductor device does not differ from that in FIG 1 shown monocrystalline silicon substrate 12 ,

10 shows a schematic cross section through the semiconductor wafer 22 according to 9 after growing an undoped epitaxial layer 32 , Under an undoped epitaxial layer 32 Here, an epitaxial layer is understood, which is extremely weak doped and can be referred to as n-type silicon material. The term "undoped epitaxial layer" does not denote a semiconductor material that is so pure as to achieve so-called intrinsic conductivity. This intrinsic state is practically unattainable with epitaxial layers on a silicon substrate that is already highly contaminated with donors since it is n ⁺ -conductive.

However, it is quite possible to reduce the donor concentration to below 10 ¹⁴ cm ^-3 , so that can be spoken of an undoped epitaxial layer, especially since no dopants in addition to the deposition of monocrystalline silicon on the silicon substrate 12 be supplied during the epitaxial process. While in the embodiment according to the 1 to 8th an average dopant concentration is supplied during growth of the epitaxial layer, this is in the embodiment according to the 9 to 16 not the case.

11 shows a schematic cross section through the semiconductor wafer 22 according to 10 after making a diffusion-inhibiting area 23 on the top 27 the epitaxial layer 32 , This diffusion-inhibiting area 23 becomes in a similar way, as it already at the 3 and 4 so that a further discussion of the production process of such diffusion-inhibiting areas 23 unnecessary.

12 shows a schematic cross section of the semiconductor wafer 22 according to 11 after exposing a surface 28 and ion implantation of acceptor ions through the exposed surface 28 through into the epitaxial layer 32 , Also, this manufacturing step is not different from the manufacturing step that already with 5 has been described.

13 shows a schematic cross section through the semiconductor wafer 22 according to 12 after whole-area ion implantation of donor ions for a doping of the undoped epitaxial layer 32 , By a correspondingly increased implantation energy, the maximum of donor ions or a highly doped region 24 in the drift zone below the diffusion-inhibiting area 23 be achieved. The donor ions can be in the range 24 even at an earlier date, about the 10 or the 11 corresponds to be introduced. In this case, the area 24 also locally in the area of the area 28 be removed when they are exposed.

14 shows a schematic cross section through the semiconductor wafer 22 according to 13 after re growing an epitaxial layer 32 without dopant addition on the already structured epitaxial layer 32 according to 13 , Again, the processing steps in the form of introducing impurity atoms as a diffusion-inhibiting layer 29 such as clearing a window in this layer 29 for introducing acceptor ions in the etched window. The introduction of donor ions for doping the undoped epitaxial layer is also carried out again.

15 shows a schematic cross section through the semiconductor wafer 22 according to 14 After multiple growth of an undoped epitaxial layer 32 on the silicon substrate 12 , Finally, this structure is heated in a diffusion furnace such that the columnar compensation zone, as they 16 shows, arises.

16 shows a schematic cross section through the semiconductor wafer 22 according to 15 in the area of a drift path 5 a power semiconductor device 1 after forming columnar compensation zones 11 , The difference to the embodiment of the invention according to the 1 to 8th lies in the fact that the doping of the drift zones 9 is not homogeneous, but from highly doped areas 24 and weakly doped areas 25 , which extend horizontally or laterally composed.

Become these areas 24 and 25 Nevertheless, a certain inhomogeneity is maintained in the doping of the epitaxial layers, as determined by the diffusion process in their concentrations is designed so that it does not prevent the lateral diffusion of the so-called "p bubbles", but ensures that the pn junction between charge compensation zone 11 and diffusion zone 9 not indefinitely deep into the diffusion zone 9 can spread, as well as an increased doping of the drift zone 9 is present. In addition, by the in 15 shown diffusion-inhibiting areas 23 the lateral diffusion of the "p-bubbles" is prevented so that two effects act simultaneously to create slimmer charge-compensation columns 8th for the charge compensation zones 11 to realize.

The 17 to 21 show schematic cross sections through portions of a semiconductor wafer 22 for the production of power semiconductor components 2 a second aspect of the invention. While in the first aspect of the invention, the diffusion-inhibiting regions 23 are aligned horizontally and laterally and thus to the current path 16 orthogonal, in the second aspect of the invention, the diffusion-inhibiting regions 23 vertically and thus parallel to the current path 16 aligned, allowing a more accurate confinement of the charge compensation zones 11 is possible.

17 shows a schematic cross section through a portion of a semiconductor wafer 22 with grown monocrystalline and middle doped silicon epitaxial layer 17 , The thickness D of this epitaxial layer is achieved with a single method step and adjusted such that the thickness D is sufficient to increase the dielectric strength of the power semiconductor component to be produced. guarantee. Depending on the required dielectric strength, the thickness D in micrometers may be between 1 μm ≦ D ≦ 150 μm. This epitaxial layer is center-doped while the monocrystalline silicon substrate 12 has a high dopant concentration.

18 shows a schematic cross section through the semiconductor wafer 22 according to 17 after introduction of a trench structure 13 and applying a diffusion-inhibiting layer 29 on the structured semiconductor wafer 22 , The introduction of the trench structure 13 is by covering the top 18 of the semiconductor body 4 with the epitaxial layer 17 achieved by a photolithographic layer, wherein only the area of photolithographic layer is kept free, in which the trench structure 13 is to bring. Subsequently, by an anisotropic etching, preferably by an anisotropic reactive ion etching, the trench structure 13 into the epitaxial layer 17 introduced so that mesen 33 with a height H on the top 19 of the substrate 12 remain.

After the introduction of the trench structure 13 into the epitaxial layer 17 the photolithographic mask is removed and on top of the semiconductor wafer with drift zones 9 in the manufactured mesen 33 becomes a diffusion-inhibiting layer 29 , preferably made of a monocrystalline germanium-containing silicon epitaxial layer. In addition to germanium, this diffusion-inhibiting layer 29 for example, also contain carbon and / or fluorine. This monocrystalline SiGe or SiGeC layer 6 as they are in 18 is shown, extends both horizontally, for example on the tops 34 the mesen 33 and on the ditch floor 30 , as well as vertically along the moat walls 14 and 15 the trench structure 13 , By further anisotropic etching can be achieved that the horizontal areas on the topsides 34 the mesen 33 and on the ditch floor 30 be removed, leaving only vertical diffusion-inhibiting areas on the trench walls 14 and 15 left over. This shows the 19 ,

19 shows a schematic cross section through the semiconductor wafer 22 according to 18 after anisotropic etching of the diffusion-inhibiting layer 29 as they are in 18 is shown, forming vertical diffusion-inhibiting areas 23 ,

20 shows a schematic cross section through the semiconductor wafer 22 according to 19 after filling the trench structure 13 with a complement to the mesen 33 of the 19 doped monocrystalline grown semiconductor material 10 in the trench structure 13 , When filling with a monocrystalline semiconductor material 10 the trench structure 13 is at the same time a relatively uneven top of Halbleitwa fers 22 generated. This will be leveled in a next step.

21 shows a schematic cross section of the semiconductor wafer 22 after leveling the top 18 of the semiconductor body 4 forming a drift path 5 a power semiconductor device 2 with vertically arranged diffusion-inhibiting areas 23 , In this embodiment of the invention according to the 17 to 21 was used as the starting material for the drift route 5 an epitaxial layer 17 applied, which already has the Driftzonendotierung.

22 shows a schematic cross section of the semiconductor wafer 22 after forming an alternative charge compensation structure 3 , In this charge compensation structure 3 was on the semiconductor wafer 22 first an epitaxial layer 17 applied with middle-doped, p-type silicon and in this middle-doped p-type epitaxial layer 17 a trench structure 13 introduced, wherein an outward diffusion of acceptors from this epitaxial region by applying a diffusion-inhibiting layer, such as, for example, the monocrystalline SiGe or SiGeC layer 6 represents, clearly prevented, leaving in the trench structure 13 a middle-doped, monocrystalline n-type epitaxial layer for corresponding drift zones 9 could be introduced.

23 shows a schematic cross section of the semiconductor wafer 22 after forming another alternative charge compensation structure 3 , In this alternative charge compensation structure 3 was also on the ditch floor 30 the trench structure 13 the diffusion-inhibiting area 23 maintained so that in cross-section a U-shape 26 for the diffusion-inhibiting areas 23 results. A particular advantage of this U-shape 26 is that by appropriate choice of the germanium content in the silicon, the mobility of the free charge carriers in these layers can be noticeably increased, so that the on-resistance can be further reduced. This effect is the stronger the higher the germanium content per silicon germanium layer. Regardless, however, the critical layer thickness in the drift path must be 5 be respected and if necessary, several thin, separated by silicon layers silicon germanium layers must be grown as it 24 shows.

24 shows a schematic cross section of the semiconductor wafer 22 after forming another alternative drift zone structure, in which case vertically oriented diffusion-inhibiting regions 23 with germanium-containing silicon and n-type doped silicon regions in the cross section of the trench structure 13 alternate each other. Instead of a monocrystalline deposition of germanium-containing silicon can also in the walls 14 and 15 the trench structure 13 Impurities and / or point defects are implanted around vertical diffusion-inhibiting areas 23 to accomplish.

25 shows a schematic cross section of the semiconductor wafer 22 after forming another alternative drift zone structure. In this case, a plurality of U-shaped, diffusion-inhibiting regions are intermeshed in the region of the trench structure 13 stacked, being between the U-shaped diffusion-inhibiting areas 23 n-type doped silicon for the drift zones 9 the drift path 5 are arranged.

1

Power semiconductor element (1st embodiment)

2

Power semiconductor element (2nd embodiment)

3

Charge compensation structure

4

Semiconductor body

5

drift

6

monocrystalline SiGe layer or SiGeC layer

7

epitaxial layer

8th

Pillar out complementary cable type

9

drift region

10

Semiconductor material monocrystalline grown in trench structure

11

Charge compensation zone

12

monocrystalline substratum

13

grave structure

14

wall the trench structure

15

wall the trench structure

16

current path

17

medium doped epitaxial layer

18

top of the semiconductor body

19

top of the substrate

20

pedestal

21

top the pedestal epitaxy layer

22

Semiconductor wafer

23

diffusion-inhibiting Area

24

highly paid Area in drift zone

25

lightly doped Area in drift zone

26

U-shape

27

top the epitaxial layer

28

area

29

diffusion-inhibiting layer

30

grave soil

31

back of the semiconductor body

32

undoped epitaxial layer

33

Mesen

34

top the mesen

35

borimplantierter Area or acceptor area

H

Height of the mesen

D

total thickness the epitaxial layer

d

thickness a diffusion-inhibiting area

t

depth the charge compensation zone

Claims (57)

Power semiconductor component with charge compensation structure ( 3 ), wherein the power semiconductor component ( 1 . 2 ) in a monocrystalline semiconductor body ( 4 ) a drift path ( 5 ) between two electrodes, and the drift path ( 5 ) Drift zones ( 9 ) of a first conductivity type having a current path ( 16 ) between the electrodes in the drift path ( 5 ) and charge compensation zones ( 11 ) of a type of line complementary to the first type of line, comprising the current path of the drift path ( 5 ), wherein the zones of the drift path ( 5 ) diffusion-inhibiting regions ( 23 ) with diffusion-inhibiting impurities and / or with diffusion-inhibiting point defects for at least one of the conductivity types, the diffusion-inhibiting regions ( 23 ) are arranged so that they the charge compensation zones ( 11 ) in their lateral extent. Power semiconductor component according to claim 1, characterized in that the drift zones ( 9 ) and the charge compensation zones ( 11 ) are arranged vertically. Power semiconductor component according to claim 1 or claim 2, characterized in that the semiconductor body ( 4 ) a highly doped substrate ( 12 ) of the first or of the complementary conductivity type, on which a weakly to medium-doped epitaxial layer ( 17 ) of the first conductivity type with the drift path ( 5 ) is arranged. Power semiconductor component according to claim 3, characterized in that the semiconductor body on the highly doped substrate ( 12 ) an unstructured lightly doped pedestal epitaxial layer ( 20 ) of the first conductivity type, which is free of charge compensation zones ( 11 ). Power semiconductor component according to claim 3, characterized in that the charge compensation zones ( 11 ) in their depth (t) from a top ( 18 ) of the semiconductor body ( 4 ) up to a top ( 19 ) of the substrate ( 12 ). Power semiconductor component according to claim 4, characterized in that the charge compensation zones ( 11 ) in their depth (t) from a top ( 18 ) of the semiconductor body ( 4 ) up to a top ( 21 ) of an unstructured pedestal epitaxial layer ( 20 ). Power semiconductor component according to one of the preceding claims, characterized in that the diffusion-inhibiting regions ( 23 ) have a thickness d in nanometers in the range of 10 nm ≦ d ≦ 1 × 10 ⁴ nm, preferably in the range of 10 nm ≦ d ≦ 300 nm and in particular in the range of 10 nm ≦ d ≦ 150 nm. Power semiconductor component according to one of the preceding claims, characterized in that the diffusion-inhibiting regions ( 23 ) Germanium, carbon and / or fluorine atoms as impurities on substitution grid sites of the monocrystalline semiconductor body ( 4 ) exhibit. Power semiconductor component according to one of the preceding claims, characterized in that the diffusion-inhibiting regions ( 23 ) a monocrystalline layer ( 6 ) having the composition Si _x Ge _y C _z , where x> y and x> z, preferably with y ≤ 0.40 and z ≤ 0.25. Power semiconductor component according to one of the preceding claims, characterized in that the diffusion-inhibiting regions ( 23 ) Have vacancies as point defects. Power semiconductor component according to one of the preceding Claims, characterized in that diffusion-promoting areas interstitial have arranged semiconductor atoms as point defects. Power semiconductor component according to one of the preceding claims, characterized in that the diffusion-inhibiting regions ( 23 ) inhibit diffusion of acceptor ions from p-type regions. Power semiconductor component according to one of the preceding claims, characterized in that the diffusion-inhibiting regions ( 23 ) inhibit diffusion of donor ions from n-type regions. Power semiconductor component according to one of the preceding Claims, characterized in that the diffusion-inhibiting regions are parallel or orthogonal to the current path. Power semiconductor component according to one of the preceding claims, characterized in that the charge compensation zones ( 11 ) in epitaxial layers ( 7 ) layered, implanted and diffused columns ( 8th ) of the complementary conductivity type. Power semiconductor component according to one of the preceding claims, characterized in that in vertically extending drift zones ( 9 ) highly doped and lightly doped horizontal areas ( 24 . 25 ) stacked on each other, the highly doped regions ( 24 ) are arranged in the same vertical position as highly doped regions in adjacent charge compensation zones (FIG. 11 ). Power semiconductor component according to one of Claims 1 to 13, characterized in that the drift zones ( 9 ) monocrystalline on a highly doped monocrystalline substrate ( 12 ) in a trench structure ( 13 ) grown semiconductor material ( 10 ) exhibit. Power semiconductor component according to one of Claims 1 to 13 or 17, characterized in that the charge compensation zones ( 11 ) monocrystalline on a highly doped monocrystalline substrate ( 12 ) in a trench structure ( 13 ) grown semiconductor material ( 10 ) exhibit. Power semiconductor component according to one of Claims 1 to 13 or 17 or 18, characterized in that the diffusion-inhibiting regions ( 23 ) vertically or parallel to the current path ( 16 ) are arranged. Power semiconductor component according to one of Claims 1 to 13 or 17 to 19, characterized in that the diffusion-inhibiting regions ( 23 ) in cross section a U-shape ( 26 ) exhibit. Power semiconductor component according to one of Claims 1 to 13 or 17 to 20, characterized in that the drift zones ( 5 ) in the trench structure ( 13 ) several in cross-section U-shaped ( 26 ) diffusion-inhibiting regions ( 23 ), which are stacked in one another, wherein between the diffusion-inhibiting regions ( 23 ) monocrystalline material ( 27 ) of the first conductivity type is arranged. Power semiconductor component according to one of claims 1 to 13 or 17 to 21, characterized in that the charge compensation zones ( 11 ) and the drift zones ( 9 ) are arranged in strips next to each other between the electrodes. Power semiconductor component according to one of claims 1 to 13 or 17 to 22, characterized in that in each case a strip-shaped drift zone ( 9 ) of two strip-shaped charge compensation zones ( 11 ) in the direction of the current path in their width transversely to the current path ( 16 ) are limited. Power semiconductor component according to one of the preceding claims, characterized in that the drift zone ( 9 ) a plurality of alternately arranged regions of silicon ( 10 ) of the first conductivity type and diffusion-inhibiting regions ( 6 ) having. Method for producing power semiconductor components ( 1 ) having the features of one of claims 1 to 16, wherein a plurality of the doping of the drift zones ( 9 ) having epitaxial layers ( 7 ) on a heavily doped substrate ( 12 a method comprising the steps of: a) providing a highly doped semiconductor wafer of a first or a complementary conductivity type with a multiplicity of power semiconductor component positions arranged in rows and columns as substrate ( 12 ) of a semiconductor body ( 4 ); b) growing a monocrystalline doping of the drift zones ( 9 ) epitaxial layer ( 7 ) on the semiconductor wafer; c) producing a diffusion-inhibiting layer ( 29 ) by introduction of diffusion-inhibiting impurities and / or point defects such as vacancies in the epitaxial layer ( 7 ); d) applying and structuring a photolithographic layer to the epitaxial layer ( 7 ) leaving areas free ( 28 ), for charge compensation zones ( 11 ); e) removing the diffusion-inhibiting layer ( 29 ) in the area of released areas ( 28 ); f) introduction of impurities of the complementary conductivity type into the epitaxial layer in the region of the exposed surfaces; g) removing the photolithographic layer h) repeating steps b) to g) to one for the dielectric strength of the power semiconductor component ( 1 ) sufficient thickness of a vertical drift path ( 5 ) is reached; i) heating the semiconductor wafer to a diffusion temperature to form columnar diffusion-inhibiting regions ( 23 ) laterally delimited charge compensation zones ( 11 ) in the epitaxial layers ( 7 ) constructed drift path ( 5 ) in the power semiconductor device positions of the semiconductor wafer. Method for producing power semiconductor components ( 1 ) having the features of one of claims 1 to 16, wherein a plurality of undoped epitaxial layers ( 32 ) on a heavily doped substrate ( 12 a method comprising the steps of: a) providing a highly doped semiconductor wafer of a first or a complementary conductivity type with a multiplicity of power semiconductor component positions arranged in rows and columns as substrate ( 12 ) of a semiconductor body ( 4 ); b) growing a monocrystalline undoped epitaxial layer ( 32 ) on the semiconductor wafer; c) producing a diffusion-inhibiting layer ( 29 by introduction of diffusion-inhibiting foreign atoms and / or point defects such as vacancies or interstitial semiconductor atoms into the epitaxial layer ( 32 ); d) applying and structuring a photolithographic layer to the epitaxial layer ( 32 ) leaving areas free ( 28 ), for charge compensation zones ( 11 ); e) removing the diffusion-inhibiting layer ( 29 ) with diffusion-inhibiting impurities and / or point defects in the area of the released surfaces ( 28 ); f) introduction of impurities of the complementary conductivity type into the epitaxial layer ( 32 ) in the area of released areas ( 28 ); g) removing the photolithographic layer; h) introduction of impurities for drift zone doping of the undoped epitaxial layer ( 32 ); i) repeating steps b) to h) to one for the dielectric strength of the power semiconductor component ( 2 ) sufficient thickness D of a vertical drift path ( 9 ) is reached; j) heating the semiconductor wafer to a diffusion temperature to form columnar diffusion-inhibiting regions ( 23 ) laterally delimited charge compensation zones ( 11 ) in the epitaxial layers ( 32 ) constructed drift path ( 5 ) and the doping of the drift cells ( 9 ) in the power semiconductor device positions of the semiconductor wafer. The method of claim 25 or claim 26 with the following additional steps: Production of top structures and back structures in and / or on the semiconductor wafer for completing the power semiconductor components (FIG. 1 ) in the power semiconductor device positions of the semiconductor wafer; Separating the semiconductor wafer into a plurality of power semiconductor components ( 1 ). Method according to one of claims 25 to 27, characterized in that prior to the growth of a medium-doped or undoped epitaxial layer ( 7 ) of the first conductivity type on the semiconductor wafer a weakly doped base epitaxial layer ( 20 ) of the first conductivity type is grown. Method according to one of claims 25 to 28, characterized in that for producing a diffusion-inhibiting layer ( 29 ) germanium ions and / or carbon ions and / or fluorine ions are introduced by means of ion implantation as diffusion-inhibiting foreign atoms. Method according to one of claims 25 to 29, characterized in that for producing a diffusion-inhibiting layer ( 29 ) diffusion-inhibiting impurities are introduced by means of a multi-stage ion implantation with different implantation energies. Method according to one of claims 25 to 30, characterized that for introduction of diffusion-inhibiting point defects such as lattice vacancies an implantation with argon ions is performed. Method for producing power semiconductor components ( 2 ) having the features of one of claims 1 to 13 or one of claims 17 to 23, wherein at least one of the doping of the drift zones ( 9 ) or the charge compensation zones ( 11 ) a drift path ( 5 ) epitaxial layer ( 17 ) is produced on a highly doped substrate, and wherein the method comprises the following method steps: providing a highly doped semiconductor wafer of a first or a complementary conductivity type with a multiplicity of power semiconductor element positions arranged in rows and columns as substrate ( 12 ) of a semiconductor body ( 4 ); Growing an epitaxial layer ( 17 ) of the first conductivity type or of a complementary conductivity type on the semiconductor wafer as a starting material for a drift path ( 5 ) with drift zones ( 9 ) and landing compensation zones ( 11 ); - introduction of a trench structure ( 13 ) with almost vertical trench walls ( 14 . 15 ) and a trench bottom ( 30 ) into the epitaxial layer ( 17 ) in the power semiconductor element positions; Deposition of a diffusion-inhibiting area ( 23 ) of a monocrystalline semiconductor layer on the semiconductor wafer; Anisotropic free etching of the trench bottom ( 30 ) of the trench structure ( 13 ) and the tops ( 34 ) the mesen ( 33 ) of epitaxial material from the monocrystalline semiconductor layer; - growing up a complementary to the mesen ( 33 ) doped epitaxial layer with filling of the trench structure ( 13 ); Production of top side structures and rear side structures in and / or on the semiconductor body ( 4 ) for completing the power semiconductor elements ( 2 ) in the power semiconductor element positions of the semiconductor wafer; Separating the semiconductor wafer into individual power semiconductor elements ( 2 ). Method according to claim 32, characterized in that that for the monocrystalline semiconductor layer silicon is used and germanium, carbon and / or fluorine added for diffusion inhibition becomes. A method according to claim 32 or claim 33, characterized in that after the growth of an epitaxial layer while filling the trench structure ( 31 ) the top of the semiconductor wafer to the drift path ( 5 ) from drift and charge compensation zones ( 9 . 11 ) to a semiconductor body ( 4 ) with leveled top ( 18 ) and flat back ( 31 ) is leveled. Method according to one of claims 32 to 34, characterized in that prior to the growth of an epitaxial layer ( 17 ) on the semiconductor wafer a weakly doped base epitaxial layer ( 20 ) of the first conductivity type is grown. Method according to one of claims 32 to 35, characterized in that prior to the growth of an epitaxial layer ( 17 ) of the first conductivity type on the semiconductor wafer or on the base epitaxial layer ( 20 ) a structured auxiliary layer in areas of the trench structure to be etched ( 13 ) is provided epitaxially, which enables an etching stop and preferably Si _x Ge _y with x> y or Si _x Ge _y C _z with x> y and x> z. Method according to Claim 36, characterized that a composition of the auxiliary layer with y ≤ 0.40 and z ≤ 0.25 is complied with. Method according to one of claims 32 to 37, characterized in that prior to the growth of an epitaxial layer ( 17 ) of the first conductivity type on the semiconductor wafer or on the base epitaxial layer ( 20 ) a structured auxiliary layer in areas of the trench structure to be etched ( 13 ) is applied, which enables an etching stop and preferably comprises a semiconductor oxide or semiconductor nitride, wherein the structure of the auxiliary layer in the regions of the trench structure to be etched ( 13 ) is applied in such a fine structure that a lateral mono-crystalline overgrowth of the fine structure is made possible. Method according to one of claims 32 to 38, characterized in that for introducing the trench structure ( 13 ) into the epitaxial layer ( 17 ) of the first conductivity type, an etching mask on the semiconductor wafer with stripe-shaped patterns in the region of the drift path ( 5 ) is photolithographically applied in the power semiconductor device positions. Method according to one of claims 32 to 39, characterized in that for introducing the trench structure ( 13 ) an anisotropic and / or isotropic etching of the trench structure ( 13 ) he follows. Method according to one of claims 32 to 39, characterized in that for introducing the trench structure ( 13 ) Anisotropic reactive ion etching is performed. Method according to one of claims 32 to 39, characterized in that for introducing the trench structure ( 13 ) a directed plasma etching is performed. Method according to one of claims 32 to 42, characterized in that for introducing the trench structure ( 13 ) a directional plasma etch with endpoint detection is performed. Method according to one of claims 39 to 43, characterized in that the photolithographic mask is removed, and the upper side of the semiconductor wafer drift zones ( 9 ) with the prepared mesen ( 33 ) between the trench structures ( 13 ). Method according to one of claims 39 to 44, characterized in that prior to the application of the etching mask, a structured Endpunktkontrollschicht preferably of a semiconductor oxide and / or a semiconductor nitride and / or a Si _x -Ge _y C _z layer with x> y and x> z, preferably with Si _0.86 Ge _0.07 C _0.07 . is applied, which the tops of the diffusion zones ( 9 ) covered. Method according to one of claims 32 to 45, characterized in that after the introduction of the trench structure ( 13 ) and before the application of a diffusion-inhibiting area ( 23 ) on the trench walls ( 14 . 15 ) the surfaces of the trench structure ( 13 ) are chemically cleaned. Method according to one of claims 32 to 46, characterized in that after the introduction of the trench structure ( 13 ) and before the application of a diffusion-inhibiting area ( 23 ) on the trench walls ( 14 . 15 ) the surface of the semiconductor wafer is oxidized and then the oxide layer is etched away. Method according to one of claims 32 to 47, characterized in that after the introduction of the trench structure ( 13 ) and before the application of a diffusion-inhibiting area ( 23 ) on the trench walls ( 14 . 15 ) These are smoothed by means of a hydrogen annealing step. Method according to one of claims 32 to 48, characterized in that as diffusion-inhibiting area ( 23 ) a monocrystalline layer of germanium-containing silicon with a thickness d in nanometers in the range of 10 nm ≦ d ≦ 1 × 10 ³ nm, preferably in the range of 10 nm ≦ d ≦ 300 nm and in particular in the range of 10 nm ≦ d ≦ 150 nm is grown up. Method according to one of claims 32 to 49, characterized in that a diffusion-inhibiting area ( 23 ) also on the trench bottom ( 30 ) is maintained. Method according to one of claims 32 to 50, characterized in that on the trench walls ( 14 . 15 ) several monocrystalline layers of germanium-containing silicon for diffusion-inhibiting regions ( 23 ) alternating with doped silicon vertically aligned as drift zones ( 9 ) getting produced. Method according to one of claims 32 to 51, characterized in that on the trench walls ( 14 . 15 ) and on the trench bottom several monocrystalline layers of germanium-containing silicon for diffusion-inhibiting areas ( 23 ) in alternating with doped silicon stacked as drift zones ( 9 ) getting produced. Method according to one of claims 32 to 52, characterized in that for the anisotropic free etching of the ground area ( 30 ) of the trench structure ( 13 ) and / or the tops ( 34 ) of Mesen ( 33 ) a dry etching method as it is also used for the introduction of the trench structure according to one of claims 38 to 40 is used. Method according to one of claims 32 to 53, characterized in that for flattening the upper side of the semiconductor wafer to a semiconductor body ( 4 ) with leveled top ( 18 ) a chemical mechanical polishing (CMP) method is used. Method according to one of claims 32 to 54, characterized in that for flattening the upper side of the semiconductor wafer to a semiconductor body ( 4 ) with leveled top ( 18 ) and back ( 31 ), a leveling photoresist layer or a spin-on-glass layer is first applied to the uneven upper side, the etch selectivity factor of which relative to the semiconductor material of the drift path (FIG. 5 ) in connection with the selected etching or Abtragverfahren is almost 1. Method according to one of claims 32 to 55, characterized in that for flattening the upper side of the semiconductor wafer up to the grown drift and charge compensation zones ( 9 . 11 ) the deposited planarized photoresist layer or spin on glass layer and the epitaxial material are etched back. Method according to one of Claims 32 to 56, characterized that the process block consisting of applying an epitaxy, mesa etching, Introduction of diffusion-inhibiting layers, epitaxial filling and Recharge multiple times performed one after the other becomes.