DE102005046734A1 - Semiconductor component with integrated capacitive structure has at least two groups of electrically conductive planes with stripe element having opposite polarity and vertical and lateral interconnections - Google Patents

Abstract

A semiconductor component has an integrated capacitance structure which is implemented in at least two groups of at least partially electrically conductive planes and which is structured in such a way that at least one plane has a plurality of strip elements in at least each group of planes, with first strip elements (SE¶11 ¶ to SE¶1n¶) represent a first polarity of the capacitance structure and second strip elements (SE¶21¶ to SE¶2n¶) represent a second polarity of the capacitance structure, with the first strip elements (SE¶11¶ to SE¶1n¶) with second strip elements (SE¶21¶ to SE¶2n¶) are at least partially interlocked and strip elements of the same polarity at least partially overlap in at least two planes and strip elements (SE) of the first group of planes by means of vertical connections (vias) with Strip elements (SE) of the same polarity of the second group of levels electrically lei are connected capable and that strip elements (SE) of the same polarity of the second group of planes with lateral connecting elements (V) are connected to one another.

Description

The The present invention relates to a semiconductor device with integrated Capacity structure the preamble of claim 1.

In The semiconductor circuit technology consists of the integration of analog Circuit parts the need for integrated capacity structures of high production quality and - reproducibility at the same time great capacitance value and small space requirement. Due to the continued steady increase in operating frequencies additionally the need for good high-frequency properties (HF properties) of these integrated capacity structures.

From the US 5,939,766 is an integrated capacity structure known. The arrangement disclosed therein is embodied in a plurality of mutually insulated, electrically conductive planes, wherein in each plane two comb structures, which represent the two electrodes of the capacitance structure, repeat themselves in identical form. Due to this complete iteration of the comb structures in each plane, however, the available base area is not optimally utilized. The proportion of comb structures given by the comb bases does not contribute to the effective capacity. Furthermore, no optimization with respect to the RF properties is possible by this design.

It is therefore an object of the present invention, a semiconductor device with integrated capacity structure to disposal to provide what a maximum capacity density has.

These The object is achieved by a semiconductor device having the features of claim 1, solved.

at the semiconductor device according to the invention is the capacity structure executed within two groups of electrically conductive levels. each Group consists of at least one level. In a first These levels of the first group are executed by a plurality of strip elements at least partially interlocked. The strip elements, which in strip elements of a first and a second polarity of the capacitance structure are not interconnected at this level. In at least one electrically conductive plane of the second group also becomes a plurality of electrically conductive strip elements executed which in turn are interlocked and which at least partially Cover the strip elements of the first level. In this second Group of levels now finds a contacting of the strip elements same polarity by means of lateral connecting elements. The electrical connection the strip elements of the first group of levels to the strip elements the second group of levels is done via vertical links, For example, vias (claim 1).

A has built-up capacity structure a big capacitance value at the same time low volume requirement, in particular small footprint. In the first set of levels of this capacity structure, the available area Completely for the realization of useful capacity used.

Farther has such a capacity structure good HF properties, this means it has low, parasitic inductance and capacity. this leads to to a high quality when using the structure in an RF circuit.

A constructed according to the invention capacitance structure owns moreover the advantage that the individual lengths, widths and thicknesses of individual strip elements in all levels and groups flexible can be adjusted. The strip elements are therefore in their respective geometry adapted to the needs of each level and group. So For example, the structure widths and structure distances of the Strip elements in higher Wiring levels for manufacturing reasons usually greater than the structural dimensions will be in lower wiring levels.

advantageous Embodiments of the semiconductor device according to the invention are in the subclaims specified.

In a first preferred embodiment become the lateral connecting elements in a plane of the second Group of electrically conductive Layers each at the free ends of the strip elements of the first and the second polarity arranged. This creates two comb structures in this plane, which are inserted into each other (claim 2).

In a further embodiment, the lateral connecting elements of a plane of the second group are arranged centrally, so that two comb-shaped substructures are formed, which are facing away from each other. Within these two comb-shaped substructures are in each case strip elements of the respective other polarity, which are connected via vertical connections with strip elements of an adjacent plane of the first group to the capacitance structure (claim 3). By such a central arrangement of the verbin Elements are given particularly advantageous RF characteristics, since due to this arrangement, a low inductance and at the same time a low series resistance of the capacitance structure is achieved. This increases the quality of the capacitance in an HF circuit.

at an analysis of the direction of the Umladungsströme in such a structure capacitance structure It should be noted that the transhipment flows are divided into two adjacent Strip elements flow in opposite directions (claim 4). This results a low, parasitic inductance the capacity structure.

Of the effect according to the invention the increase of Usable capacity is particularly pronounced when the arrangement of the strip elements in a first group of Layers as periodically as possible often repeated. This reduces the for the calculation the useful capacity non-effective portion of the structures, that is the area fraction of the connecting elements, relative to the total usable area. This should under total floor space the summary area percentage all for the capacity structure to disposal standing levels are understood (claim 5).

The electrically conductive Levels can go through Use of for the semiconductor device anyway required metallization levels to be provided. Usually find here metals or metal alloys based on aluminum (Al) or copper (Cu) preferred application. However, it's every bit electric conductive Material for this use in principle suitable (claim 6).

alternative may be at least one electrically conductive layers of polysilicon exist (claim 7).

In a further embodiment of the invention is at least one of the electrically conductive planes by doping of the semiconductor substrate generated (claim 8).

It There are two alternatives for structuring, which are in terms of differ the choice of doping. In a first embodiment the substrate is homogeneously doped. For the production of strip elements the substrate plane is structured by the strip elements each separated by an insulating layer. to Isolation comes here, for example, the methods LOGOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) for use. As a result, strip elements of two different polarities are present (Claim 9).

In a second embodiment For example, the substrate plane can be made of two different types of dopants become. Here, the strip elements of the first polarity in one first dopant produced while the strip elements of the second polarity in a second doping getting produced. An additional Separation of the respective strip elements from each other, z. B. by Separate insulating layers, this is unnecessary, since between the individual Strip elements each form a junction capacitance due to the pn junction (Claim 10).

following become a capacity structure the prior art, as well as several embodiments of the invention such a generic structure closer to the drawing explained.

It demonstrate:

1 a level of an integrated capacitance structure according to the prior art,

2 a first, inventive embodiment of an integrated capacity structure, consisting of a total of four levels, wherein a plane is designed as a connection level,

3 A second, inventive embodiment of a connection level of an integrated capacity structure,

4 A third, inventive embodiment of a connection level of an integrated capacity structure,

5 A fourth, inventive embodiment of an integrated capacitance structure, wherein there are two levels of connection,

6 a fifth, inventive embodiment of an integrated capacity structure.

In the same reference numerals designate the same or functionally identical Elements.

1 shows an integrated capacitance structure according to the prior art in plan view. Above a substrate, for example a semiconductor substrate (not shown), first and second strip _elements SE _1n and SE _{2n are} regularly intermeshed. The capacity of the arrangement depends essentially on both the length, thickness and number of the strip elements SE and the distance between the individual strip elements SE from each other. Both groups of strip _elements SE _1n and SE _2n are each electrically conductively connected to each other with a laterally arranged connecting element V ₁ or V ₂ prevented. The resulting two comb-shaped structures represent a capacitance structure with two polarities. To increase the total capacitance, the present structure can be repeated congruently several times in the vertical direction. For making contact with the individual capacitance structures of different levels, at least one via is required which connects the connection elements of the same polarity but different levels.

In 2 a first, inventive embodiment of an integrated capacitance structure is shown. In contrast to the prior art, the individual partial capacity structures do not repeat within the levels M1 to M4. In the bottom rewiring planes M1 to M3, as seen from the substrate (not shown), there are exclusively regularly iterating strip elements of a first and a second polarity SE _1n and SE _2n . Both polarities comprise a plurality of strip elements SE, which are shown in the drawing by identical hatching. Since the increase in the number of strip elements has a purely additive effect, an allocation of reference symbols to all further strip elements is dispensed with for reasons of clarity. It is clear to the person skilled in the art that he can set the desired capacitance value, inter alia, by the choice of the relevant parameters, ie both length, thickness and number of strip elements as well as the number of planes used.

Due to the absence of lateral connecting elements V in the levels M1 to M3 compared to the prior art, the full base area is available in order to achieve the largest possible capacitance value. In contrast, the plane M4 is structured in such a way that there are two lateral connecting elements V ₁ and V ₂ in the center, which connect the strip elements of the respective same group laterally to each other in an electrically conductive manner.

Non-central arrangements of the connecting elements V ₁ and V ₂ are possible, as will be shown in further embodiments of the invention. However, the central arrangement herein has the added advantage of improved high frequency characteristics. The charge-generating currents generated by the application of a high-frequency operating voltage within the integrated capacitance structure K run in antiparallel fashion in adjacent strip elements, for example SE ₁₁ and SE ₂₁ . This largely avoids the generation of undesired, parasitic inductances.

The Connection of strip elements of the same group between different Levels take place by means of at least one via. To the technically simple Realization here are strip elements of each same polarity essentially congruent one above the other stacked. Also arrangements in which only a partial overlap exist, are possible, however. While in principle for the realization of the inventive idea ever one Via between the individual strip elements each different Plains is sufficient, a plurality of vias is preferably provided. This has the advantage that the contact probability in the manufacturing process, which in turn increases the overall yield (Yield) increases in the device manufacturing. On the other hand, there is still the additional one Advantage that the vias contribute to increasing the total capacity, by making the vertical faces facing each other different Increase capacitor plates.

For the realization of the inventive concept, it is irrelevant whether the group of planes with the connecting elements V ₁ and V _{2 is} the uppermost level. Rather, this at least one connection level V can be realized in any stacking sequence.

There due to manufacturing fluctuations the smallest possible, freely selectable distance structures (pitch) with increasing distance from the substrate as well Often, the at least one connection level often does not to be the top level. Rather, over the at least one connection level be executed even more strip elements SE whose width due Design Rules for higher levels greater than that of the strip elements is lower levels. For example Every second strip element can be omitted periodically up to twice the width become.

3 shows an alternative according to the invention of the connection plane M _v as a second embodiment. To simplify the pictorial representation is based on a new representation of other levels, for example, from the already in 2 Levels M1 and M2 shown omitted.

The connecting elements V ₁ and V ₂ are arranged in this embodiment at the outer ends of the strip elements SE.

One Advantage of this embodiment consists in a reduction of the series resistance of the capacitance structure K. Another advantage is that regardless of the latitudes and distances the strip elements SE the capacitance structure K of problem above can be contacted, for example via vias different Size. As well is a flexible contact over the entire width of the arrangement, that is along the length of the Connecting elements V, possible.

4 shows a further inventive alternative of the connection plane M _v as a third embodiment. To simplify the pictorial representation is based on a new representation of other levels, for example, from the already in 2 Levels M1 and M2 shown omitted.

Between the in 2 shown embodiment, where the connecting elements V ₁ and V ₂ are arranged centrally, and the in 3 In the embodiment shown, where the connecting elements V ₁ and V ₂ are arranged on the outside, an intermediate position for V ₁ and V _{2 has been} selected in the present embodiment.

By the lateral displacement of the connecting elements along the Strip elements SE becomes a flexible contacting possibility created, which in turn leads to an improved adaptation to others Circuit parts leads.

5 shows a fourth embodiment of an integrated capacity structure. For the sake of simplicity, reference is made to a renewed representation of further levels, for example of those already in 2 Levels M1 and M2 shown omitted.

The functionality of the lateral connection, in contrast to the previously discussed embodiments, is now distributed over two levels. In the plane M _v , a lateral, electrically conductive connection between the strip elements of the second polarity SE _{2n is} produced via connecting element V ₂ . In the plane M _{v ± 1} , ie, a plane which is located, for example, directly below or directly above the plane M _v , a lateral, electrically conductive connection between the strip elements of the first polarity SE _{1n is} established via connecting element V ₁ .

An advantage of this arrangement is that a substantial compensation of the magnetic stray fields is achieved. This leads to a reduction of the parasitic inductance of the capacitance structure. Furthermore, with an adjacent, vertical arrangement of the connecting elements V ₁ and V ₂ , their thus existing, vertical capacity proportion to each other can additionally be used.

Also designs, in which the two connection levels, ie levels of the second group of layers, are in any vertical stacking sequence, are possible. So can For example, the two connection levels of at least one level from the first group of strip elements SE, where no lateral Connections of the strip elements are present, vertically from each other be separated.

6 shows a fifth embodiment of an integrated capacity structure. For the sake of simplicity, reference is made to a renewed representation of further levels, for example of those already in 2 Levels M1 and M2 shown omitted.

In this embodiment, the lateral, geometric extent of the capacitance structure along the strip elements SE is much greater than the lateral extent perpendicular thereto. In order to minimize the ohmic resistance of the capacitance structure in this embodiment, a plurality of first and second connecting elements V ₁ and V _{2 are} provided, which are connected in parallel.

K

integrated capacitance structure

SE _nm

mth Strip element of the nth polarity

Ma

a-te electrically conductive level

M _v

connecting plane to the lateral electric

conductive connection of strip elements

V ₁

first lateral connecting element

V ₂

second lateral connecting element

Via

vertical, electrically conductive connection

Claims (10)

Semiconductor device having an integrated capacitance structure, which is designed in at least two groups of at least partially electrically conductive levels, and which is structured such that at least one level has a plurality of strip elements in at least each group of planes, wherein in each case first strip elements (SE ₁₁ to SE _1n ) represent a first polarity of the capacitance structure and second strip elements (SE ₂₁ to SE _2n ) represent a second polarity of the capacitance structure, wherein furthermore in each case first strip elements (SE ₁₁ to SE _1n ) with second strip elements (SE ₂₁ to SE _2n ) at least partially into one another are interleaved and in at least two levels strip elements of the same polarity at least partially overlap, characterized in that strip elements (SE) of the first group of levels by means of vertical connections (Vias) with strip elements (SE) of the same polarity of the second set of levels electris ch are conductively connected and that further strip elements (SE) of the same polarity of the second group of planes with lateral connecting elements (V) are each interconnected. Semiconductor component according to Claim 1, characterized that the lateral connecting elements the strip elements one each polarity connect together at their ends. Semiconductor component according to claim 1, characterized in that the lateral Verbin tion elements connect the strip elements each one polarity centered. Semiconductor component according to Claim 1, characterized that the transhipment flows in two adjacent strip elements of different polarity at least flow in opposite directions in one section. Semiconductor component according to Claim 1, characterized that the first group of strip elements in substantially identical shape exists in at least two levels. Semiconductor component according to one of the preceding Claims, characterized in that at least one of the electrically conductive planes a metallization level of the semiconductor device is. Semiconductor component according to one of Claims 1 to 5, characterized in that at least one of the electrically conductive planes made of polysilicon. Semiconductor component according to one of Claims 1 to 5, characterized in that at least one of the electrically conductive planes is a doped plane of a semiconductor substrate. Semiconductor component according to Claim 8, characterized in that at least one doped plane of the semiconductor substrate in one Doping performed is such that the strip elements of the first polarity of the Strip elements of the second polarity by means of a vertical Insulating layer are separated from each other. Semiconductor component according to claim 8, characterized in that the at least one doped plane of the semiconductor substrate in such a way accomplished is that the strip elements of the first polarity in one first doping and the strip elements of the second polarity in one second doping carried out are.