DE102005046007A1 - Lateral compensation semiconductor component for use as high voltage transistor, has coupling layers for connection of compensation cells with each other, where layers are of p-type conduction and are in connection with source region - Google Patents

Abstract

The invention relates to a lateral compensation semiconductor component (1) with coupled compensation cells (18) and a method for its production. For this purpose, the lateral compensation semiconductor component (1) has a drift region (19) which surrounds the compensation cells (18) and is arranged in a semiconductor body (22) between a source region (20) and a drain region (19). The drift region (21) with the compensation cells (18) is arranged on a substrate (23) of the same conductivity type as the compensation cells (18). The substrate (23) is electrically connected to the source region (20), with coupling layers (24) or coupling structures of the same conductivity type as the compensation cells (18) being arranged in the lateral compensation semiconductor component (1) for the electrical coupling of the highly doped compensation cells (18) and are electrically connected to the source region (20).

Description

The The invention relates to a lateral compensation semiconductor device with mutually coupled highly doped compensation cells, in a surrounding the compensation cells drift region with complementary Line type between a source area and a drain area in a semiconductor body are arranged.

Such a lateral compensation semiconductor component is described as a lateral high-voltage transistor from the document DE 198 28 191 C1 known. Like the adjoining 23 shows, the known compensation semiconductor device 17 a p-type silicon semiconductor substrate 23 on. On the p-type silicon semiconductor substrate 23 is an n-type epitaxial layer 41 provided in its surface 16 an n ⁺ -type drain electrode junction region 40 , to which a voltage + U _DS is applied, is arranged. A p-type pan 42 and an n ⁺ -type source electrode terminal region 37 are opposite to the Draninelektroden Anschlussgebiet 40 in the surface 26 the epitaxial layer 41 brought in. The tub 42 and the area 37 are connected to ground.

Above the p-type well 42 is over a gate insulating layer 39 For example, silicon dioxide is a gate electrode 38 arranged with a contact G. According to this prior art are located between the terminal area 37 for the source electrode 45 and the connection area 40 for the drain electrode 46 trenches 43 For example, by etching in the epitaxial layer 41 are introduced and their walls 53 with p ⁺ dopant, such as boron, are highly doped. This can be done by outdiffusion from p-doped polycrystalline silicon or from a corresponding oxide filling. The Trenche 43 are in rows parallel to the source area 20 and rows perpendicular thereto, line by line on the surface with a narrow p-type stripe 44 connected to each other. The Trenche 43 are mainly capacitively coupled and over the narrow p-type stripes 44 line by line with each other and with the p-type well 42 connected with high resistance.

Upon application of an increasing voltage + U _DS to the connection region 40 the space charge zone grows from the side of the source region 20 with the source electrode connection region 37 out toward the drain electrode side 46 in the drain electrode terminal region 40 at. When the voltage has risen far enough to make the p-type strip 44 to clear out, the p ⁺ -type trenches floated 43 and are in rows at the potential, with which the space charge zone reaches the corresponding row.

The distance a between the rows of trenches 43 is dimensioned such that the removal of charge carriers of the epitaxial layer 41 between the rows earlier takes place as the Trenche 43 to the n-type epitaxial layer 41 reach the so-called breakdown voltage. The structure of the Trenche 43 is formed in a columnar shape with an annular or elongated elliptoid-like cross section and reaches a depth of penetration T, which is less than the thickness D of the epitaxial layer 41 , Thus, a buffer zone remains under the trenches 27 of lightly doped n ^- type material, which is the material of the n ^- type epitaxial layer 41 equivalent.

The only capacitively coupled highly doped "floating" compensation cells 18 are particularly disadvantageous in fast switching operations, because then these highly doped areas even over the narrow very high-impedance p ^- -line stripes 44 can not be unloaded fast enough. Especially in planar MOS structures is through these strips 44 the channel width of the channel area 52 at the transition to the drift area 19 narrowed, which losses are connected in the on state.

A further disadvantage, in particular in the case of vertical MOS components, is that the capacitance curve of the output capacitance drops sharply with the voltage increase at high drain-source voltages + U _DS and therefore generates high-frequency interference fields in switched-mode power supplies, which with high downstream filter expenditure in the case of such compensation semiconductor components 17 must be filtered out in order to comply with the relevant electromagnetic compatibility standards (EMC standards). This disadvantage exists especially with vertical compensation components. In. Components according to DE 198 28 191 C1 this adverse effect is less pronounced because DE 198 28 19 C1 discloses a lateral compensation component. The burden of noise filters can be considerable for corresponding switching power supplies in terms of space as well as in terms of cost.

task The invention is to overcome the above-mentioned disadvantages of conventional ones Compensating to overcome semiconductor devices and a compensation semiconductor device indicate that cost can be produced and shows an improved switch-on and blocking characteristic.

This object is achieved with the subject of the independent claims. Advantageous developments of the invention will become apparent from the dependent claims.

According to the invention is in Referring to a first aspect of the invention, a lateral compensation semiconductor device with mutually coupled highly doped compensation cells created a type of line. The compensation cells are from a drift region with complementary Line type surrounded and between a source area and a drain area arranged in a semiconductor body. Drift region and compensation cells are on a substrate with the same conductivity type as the compensation cells arranged. there the substrate is electrically connected to the source region. For the electrical coupling of the heavily doped compensation cells between them are coupling layers or coupling structures of the same conductivity type like the compensation cells in the lateral compensation semiconductor device arranged and electrically connected to the source region.

Compensation cells are understood as meaning both columns or plates of highly doped semiconductor material of a conductivity type incorporated in one or more epitaxial layers, and trenches arranged in a drift region of a semiconductor body and introduced, for example, by etching or laser ablation and / or plasma sputtering, and in the wall regions the trenches are highly doped with the one conductivity type, as it is from the document DE 198 28 191 C1 is known. To a limited extent, the inventive structure can also be transferred to compensation semiconductor components with a field plate construction.

The compensation semiconductor device according to the invention has the advantage of a high dielectric strength, which is achieved by the spaced juxtaposition of compensation cells on the source-drain path. The spaced compensation cells in the drift region act as a voltage divider for the drain-source voltage + U _DS applied between source region and drain region. When starting up the voltage U _D , after clearing out the weakly doped p regions, first the surrounding drift region of the row of compensation cells that lies closest to the source region is eliminated.

One Advantage of the invention is, moreover, that the capacity curve by varying the distances can be introduced selectively between the compensation cells.

If the electric field has expanded so far in the drift area, until the next one Range of highly doped compensation cells is reached, then only the around this second row highly doped cells arranged around Drift area cleared. As long as the compensation cells equidistant arranged in rows between the source region and the drain region are thus results in a nearly constant course of the output capacitance. By Variation of the distance leaves but modulate the electric field well along the drift path, which is used in a further aspect of the embodiments according to the invention. Instead of a field increase can so z. B. to structural edges of the compensation cells or to Feldplattenenden the field can be influenced.

The lateral according to the invention Compensating semiconductor device also has the advantage that the compensation areas over the electrical coupling layers after a switching operation be discharged from high voltage, so that the on-resistance not increased becomes.

To be in a first embodiment invention, the highly doped compensation cells into the substrate area with the same conductivity type as the compensation cells with overcoming the above mentioned Buffer zones extended. In order to nevertheless adjacent highly doped areas at different potentials can lie must the connection area around the heavily doped area, d. H. the Drift area, can be cleared out otherwise the highly-paid areas will be at the same potential stay standing. To achieve that, it is envisaged that the Substrate, in which the highly doped cells protrude, in this first embodiment of the Invention is lightly doped. The heavily doped compensation cells become weak doped substrate connected, but not shorted, so that by a correspondingly low substrate doping potential separation achieved between adjacent highly doped compensation cells can be.

In a further embodiment Although the substrate is highly doped, but has a lightly doped layer on the heavily doped substrate, wherein the lightly doped layer forms the coupling layer and itself the compensation cells from the top of the semiconductor body up extend into the lightly doped coupling layer. Thus be the highly doped compensation cells via a weakly doped coupling layer connected to the substrate, which in turn connected to the source electrode of the compensation semiconductor device is electrically connected. On the one hand, this results in a discharge via the lightly doped coupling layer guaranteed and on the other hand for that ge ensures a potential separation between the adjacent highly doped Compensation cells possible is.

In a further embodiment of the invention A weakly doped layer is used in the region of the upper side of the semiconductor body as the coupling layer. In this embodiment, the compensation cells extend from the lightly doped layer in the region of the upper side of the semiconductor body to a buffer zone of drift region material above the substrate. Thus, the compensation cells do not extend into the substrate as in the first two embodiments of the invention. The critical region between the row of compensation cells closest to the source region can be structured in such a way that only lightly doped narrow strips connect this series to the body zone of the source region. Otherwise, the coupling layer extends over a large area over the entire drift region and electrically connects the highly doped compensation cells, wherein this coupling layer has a high surface resistance in order to ensure that a potential separation between adjacent rows of highly doped coupling cells remains ensured.

In a further embodiment According to the invention, most of the highly doped compensation cells will have one shallow Coupling layer interconnected. The problematic area at the channel end, however, without such a lightly doped coupling layer executed, wherein for the Coupling of the nearest adjacent row of compensation cells to the source region lightly doped layer region is arranged on the substrate. This embodiment The invention is thus characterized in that a weak doped layered Coupling structure partially on top of the semiconductor body and is disposed on the substrate, wherein the lightly doped coupling structure on the substrate at least the coupling cells below the body area connects to the first adjacent row of compensation cells, and the layered Coupling structure on top of the semiconductor body the remaining compensation cells electrically interconnects. In this case, the at least one immediately adjacent to the body region Compensation cell both in the layered coupling structure the top of the semiconductor body as well as in the weakly doped coupling structure on the substrate extend. This ensures that the problematic area at the End of the channel manages without a weakly doped coupling layer and nevertheless all compensation zones over one Coupling structure partly on the top and partly on can be discharged to the substrate after a locking operation, so that a low on resistance is achieved.

In a further embodiment In accordance with the invention, a lightly doped layered coupling structure is partially on the top of the semiconductor body and partially on the Substrate arranged. In this case, the weakly doped coupling structure is on the substrate at least below the source region in such a direction on the source area increases that the existing doping of the drift region in the blocking case without additional highly doped compensation cells can be compensated. Consequently has this embodiment The invention no highly doped compensation zones below the Bodyzone of the compensation semiconductor component on, it takes over the function of clearing the Drift zone below the body zone the extended area of the coupling layer in the area of the source area.

Preferably The compensation cells extend in a columnar shape starting from the top side of the semiconductor body orthogonal to the top into the semiconductor body and have a round or an oval or a polygonal, preferably one hexagonal or a square or a rectangular cross section. The function of the heavily doped compensation cells is not immediate from the cross section of the columnar compensation cells dependent, However, it affects the optimal design of a lateral Compensation semiconductor component. In particular, a bigger influence on the potential distribution between the source region and the drain region but has the distance between the compensation cells. In one Another aspect of the invention is this distance of the compensation cells not equidistant, but it varies between the source area and the drain area. This has the advantage that the potential distribution in the drift region is varied accordingly. At a large distance creates a large potential difference and at a small distance, a correspondingly lower potential difference between the compensation cells when applying a blocking voltage.

In addition, in a further embodiment of the invention, the coupling layer between differently spaced compensation cells does not have a uniformly weak dopant concentration but a laterally varied doping concentration. This lateral variation may be independent of, or correlated with, the distances of the compensation cells. It makes sense to provide a higher doping of the coupling layer in the region of larger distances of the compensation cells. In this case, the distances of the compensation cells from the source region to the drain region can vary, while the coupling layer has a uniformly weak dopant concentration from the source region to the drain region. As a result of these different correlations between the dopant concentration in the coupling layer and the distance of compensation zones from one another, the capacitance curve will be as the drain-source voltage increases The result is that an optimum over conventional lateral compensation semiconductor components is achieved. This optimum can be improved in such a way that switching power supplies can dispense with additional cost-intensive and space-consuming noise filters.

Of the Capacity progression over the Drain-source voltage can be determined by the variation of the dopant concentration in the coupling layers and by means of the distance variation of the Compensation cells between source region and drain region an ideal capacitance profile the output capacity be approximated with the voltage increase at high drain-source voltages. In this ideal capacity process The voltage increase is slowed down at high drain-source voltages respectively. Accordingly, the capacity should preferably not be linear, but at small drain-source voltages relatively large, at medium Drain-source voltages are relatively small and at high drain-source voltages again reach the same size as with small drain-source voltages. This results in a "tub profile-like" profile of the output capacitance over the drain-source voltage as an ideal capacity curve, the at fast switching operations no overshoots generated at the output of a compensation semiconductor device.

With the above mentioned options the variation of the impurity concentration in the coupling layers and the distance variation of the compensation zones from each other will be the problem of high frequency interference the kind solved, that less high-frequency components of the spectrum by the compensation semiconductor device according to the invention be generated and thus reduces the filter effort to be completely neglected can. Through a capacity over the Drain-source voltage the output capacity a MOSFET, the so-called. "Baths" run with a Minimum at an average drain-source voltage rounded the switching edges of the compensation semiconductor device with the result of reduced high frequency noise.

In a further embodiment According to the invention, the compensation semiconductor device has a compensation structure with a central region between the source region and the drain region on, in which the compensation cells have a greater distance than the compensation cells adjacent to the source region and the drainage area are arranged. The concentration of the Coupling layer kept constant on weak doping. In the middle, the electric field is in the range of increased distances now elevated. This results from the fact that more distant compensation cells only at higher Potential difference connected to the previous compensation cells can be which automatically a higher one Field means.

In A charge curve shows this in a slightly delayed increase the capacity what a rounding of the switching edge of the compensation semiconductor device equals. That way you can by the distance variation the field along the drift path in easy to modulate. Instead of a field increase can thus, for example, on turkanten structure of compensation cells or field plate ends the field are deliberately lowered.

Especially good However, the output capacity by a variation of the doping of the coupling layer with simultaneous Variation of distances adjust the compensation cells, so that in the other embodiments the possibilities the simultaneous variation of distances and dopant concentrations be shown.

In a preferred embodiment According to the invention, the compensation semiconductor device has a compensation structure with a central region between the source regions and the drain region, wherein the compensation cells in the middle region a smaller Distance than the compensation cells adjacent to the source region and the drain region are arranged. simultaneously the compensation semiconductor device has a at the top of the Semiconductor body arranged coupling layer with a lower dopant concentration in the central region and a correspondingly increased dopant concentration in the areas adjacent to the Source and Drain areas are. By the higher Doping can not be done between adjacent compensation areas more so much potential to be recorded, what the achievable voltage reduced. This effect can be counteracted by increasing the distance be, so a charge curve for small and big Tensions a delayed Voltage rise, so has an increased capacity.

The reason for this is that due to the higher doping of the coupling layer, several highly doped areas are cleared out at the same time. As a result, the capacity is greater in the moment in which these contiguous compensation areas are detected by the field. Although the higher doped coupling layer is eliminated, the capacity is again in a gradual progression. By means of the position of the varied regions and the extent of the variation, it is thus possible to modulate the course of the capacitance within wide limits. The embodiments claimed below are partly rough approximations. By narrower and wider compensation zones in addition to the Ab There are still room variations for the adaptation of the capacitance curve of a compensation semiconductor device. Thus, an increased output capacitance at the beginning and at the end of the drain-source voltage increase can be realized in an ideal manner.

The Coupling layer on the surface is not in all cases the whole area perform, but subareas can also strip-shaped Have coupling structures. The geometry of the compensation cells is not limited to planar structures. Trench cells are as well possible. These have the advantage that the coupling layer over the entire surface without be introduced negative impact on the on-resistance can.

In a further embodiment According to the invention, the compensation semiconductor device has a compensation structure with compensation cells whose distances from each other from the source region to remove the drain area, and the one coupling layer on the Top of the semiconductor body whose dopant concentration from the source region in Direction on the drain area decreases. This embodiment has the advantage that at low voltage, several highly doped regions near the source region eliminated at the same time which increases the capacity in the low voltage range. On the other hand, when the high voltages are reached, the distance between reduces the compensation areas towards the drainage area, which in turn involves an increase or increase in output capacity is. Thus, also with this embodiment of the invention a ideal "bathtub-shaped" course of the output capacity reached.

Instead of a coupling layer with decreasing dopant concentration from the source area towards the drain area on the top of the Semiconductor body can in a further embodiment the invention arranged this coupling layer on the substrate be, with the compensation zones from the top of the semiconductor body to protrude into the coupling layer. The advantages are the same this embodiment the invention the above-mentioned Advantages in the arrangement of the coupling layer on top of the The semiconductor body.

In a further preferred embodiment According to the invention, the compensation semiconductor device has a compensation structure with compensation cells whose distances from each other from the source region towards the drainage area, and that one coupling layer partially on top of the semiconductor body and partially disposed on the substrate. At the same time the dopant concentration increases of the coupling layer from the source region toward the drain region from. Furthermore The coupling layer extends at least on the substrate below the source region in the direction of the body zone to, that there existing doping of the drift zone in the case of blocking without additional highly doped compensation cells can be compensated.

at this embodiment the invention will advantageously be the critical area at the end of the MOS channel of the top of the semiconductor body not with a coupling layer provided, for that but the coupling layer on the substrate expands so that no number of compensation zones are required below the bodyzone becomes.

at Another aspect of the invention is the substrate material the coupling layer, wherein the compensation cells of the Top of the semiconductor body extend into the substrate of the same conductivity type. Limited a buried region of complementary conductivity type to the substrate material the coupling layer of substrate material in its thickness d. With this embodiment of the Invention is proposed, the highly doped compensation cells in the drift area over to connect the substrate, as already described above. However, in this embodiment A measure seized in the case of blocking the compensation zones over a Decoupling the space charge zone from the substrate. This happens through the complementary doped buried layer in the substrate material, with which the thickness d the coupling layer is limited from substrate material.

If the highly doped areas of the compensation cells over the Substrate are connected, there is the advantage that in Switching the charge carriers over the can drain on Sourceptotential placed substrate. Another advantage can be seen in the fact that in the manufacturing process no limitation arises that a distance of the compensation cells from the substrate must be set exactly in the form of a buffer zone. However, that is in this embodiment crucial to the invention that by the contact on the Substrate no Einschaltwiderstandsverlust as opposed to a Contacting via a low doped coupling layer placed in the drift zone must be accepted.

However, if the highly doped compensation zones are connected to the source potential via the substrate, and no further measures are taken, then the function of the voltage divider can be lost through the compensation regions. In order not to do so, in this embodiment of the invention, the buried region of complementary conductivity type becomes the substrate material as a constraint on the thickness of the coupling layer of substrate material provided.

Becomes waived such a buried layer, then can by the loss of the voltage divider function of the compensation zones the blocking voltage mainly fall between substrate electrode and drain electrode. Thereby This structure can only handle blocking voltages that are dependent on the substrate doping are. Around the compensation zones from the substrate potential decoupling them thereby making them virtually "floating" is in the present embodiment the invention, the drift path of the drift region by a buried n-region decoupled from the substrate potential.

there couples the region buried by this with complementary doping Space charge zone to the substrate caused the pillar structure of the compensation zones from the substrate potential when the complementarily doped buried region in Distance (from the drift path) and in doping on the substrate doping is adjusted. In this case, the distance of the complementarily doped corresponds Buried area of the thickness of the coupling layer of substrate material. In this embodiment of the invention should be the complementarily doped buried region Ideally not to reach below the so-called MOS cell, d. H., it should be before reaching a position below the source area end, because otherwise there is a compensation required. This premature end of the complementarily doped buried territory has the advantage that in the case of switching the charge carriers on the possible thereby Drain contact to the substrate can.

If in a compensation semiconductor device in which as a coupling layer the substrate is used, as mentioned above, a voltage dividing function The equipotential lines are no longer present in the compensation zones in the substrate perpendicular to the compensation zones or parallel to the top of the substrate. In contrast, the equipotential lines are in the substrate in the case of the structure with buried complementarily doped Area parallel to the compensation zones or perpendicular to the Aligned top of the substrate.

In a further embodiment According to the invention, the buried area has a structured buried one Layer on, which is divided into cells, with the gap of substrate material between the cells is dimensioned such that the substrate material in the blocking case in these spaces completely from carriers cleared is. As long as thus between the complementarily doped layer at the Top edge of the substrate can form space charge zones, is a decoupling of the compensation zones from the rest of the substrate in an advantageous Guaranteed manner.

In a further embodiment The invention relates to the buried region in the substrate material below the drainage area over a tie layer of the same conductivity type as the draft domain electrically connected. Thus, the buried layer on the Potential of the drain electrode placed and electrically coupled and no over capacitive coupling "floating" connected. Similar to in the previously discussed coupling layers, the concentration be varied in the buried territory. Through this variation can advantageously the electric field distribution in the Drift zone can be influenced.

In a preferred embodiment the invention is the dopant concentration in the buried Adjacent area in a central area between source and drain areas reduced to the source and drain regions arranged areas. Furthermore, it is possible that the buried area in the substrate material from below the drainage area extends to below the source region and the body zone of the source region extends so deeply into the semiconductor body is that a remaining area of the drift zone in the blocking case completely from Carriers are cleared out can. About that In addition, it is also conceivable, more buried layers below the complementary of the doped area, in particular on the drain side. These extra buried Layers influence the propagation of the space charge zone in the Substrate electrode.

The Thickness of the substrate influences the breakdown voltage in addition to the doping the substrate diode and over The relationship the length of the drift region to the thickness of the substrate as a coupling layer the course of the output capacity be set. About that in addition, as discussed above, the distances of the compensation zones be varied, which affects the distribution of the electric field.

Of the Cross-section of the compensation zones corresponds to those discussed above Cross sections and as MOS cell in the region of the source region comes both a planar cell in question as well as a trench cell or a turned trench cell. Such trench cells have the advantage a smaller channel length to realize what the switching speed of the MOS compensation semiconductor devices elevated.

The The invention will now be described with reference to the accompanying figures.

1 shows a schematic cross section through a compensation semiconductor device of a first embodiment of the invention;

2a) shows a schematic plan view of the compensation semiconductor device according to 1 in a first modification;

2 B) shows a schematic plan view of the compensation semiconductor device according to 1 in a second modification;

3 shows a schematic cross section through a compensation semiconductor device according to a second embodiment of the invention;

4 shows a schematic cross section through a compensation semiconductor device according to a third embodiment of the invention;

5 shows a schematic cross section through a compensation semiconductor device according to a fourth embodiment of the invention;

6 shows a schematic cross section through a compensation semiconductor device according to a fifth embodiment of the invention;

7 shows a schematic cross section through a compensation semiconductor device according to a sixth embodiment of the invention;

8th shows schematic diagrams of the output capacitance as a function of the drain-source voltage U _DS ,

9 shows a schematic diagram of variations in the field strength E _m over the source-drain line 1 with stored compensation cells;

10 shows a diagram of the voltage rise of the drain-source voltage U _DS as a function of time t;

11 shows a schematic cross section through a compensation semiconductor device according to a seventh embodiment of the invention;

12 shows a schematic cross section through a compensation semiconductor device according to an eighth embodiment of the invention;

13 shows a schematic cross section through a compensation semiconductor device according to a ninth embodiment of the invention;

14 shows a schematic cross section through a compensation semiconductor device according to a tenth embodiment of the invention;

15 shows a schematic cross section through a compensation semiconductor device according to an eleventh embodiment of the invention;

16 shows a schematic cross section through a compensation semiconductor device according to a twelfth embodiment of the invention;

17 shows a schematic course of equipotential lines of a compensation semiconductor device without buried complementarily doped region according to the prior art;

18 shows a schematic course of equipotential lines of a compensation semiconductor device according to 16 with buried complementarily doped area;

19 shows a schematic cross section through a compensation semiconductor device according to a thirteenth embodiment of the invention;

20 shows a schematic cross section through a compensation semiconductor device according to a fourteenth embodiment of the invention;

21 shows a schematic cross section through a compensation semiconductor device according to a fifteenth embodiment of the invention;

22 shows a schematic cross section through a compensation semiconductor device according to a sixteenth embodiment of the invention;

23 shows a schematic cross section through a compensation semiconductor device 17 according to the prior art.

1 shows a schematic cross section through a compensation semiconductor device 1 a first embodiment of the invention. This compensation semiconductor device 1 is lateral to a substrate 23 built from monocrystalline silicon. On the substrate 23 is a semiconductor body 22 arranged. The semiconductor body 22 has mutually coupled highly doped compensation cells 18 of a conductivity type p-type in this embodiment of the invention. The compensation cells 18 are from a drift area 19 surrounding a complementary conductivity type to the conductivity type of the heavily doped compensation cells 18 having. This complementary conductivity type is n ^- -conducting.

The drift area 19 is between a source area 20 on one side of the semiconductor body 22 from a source electrode connection region 37 , a bodyzone 36 and a gate electrode 38 with a gate insulating layer 39 and a drainage area 21 on an opposite side of the semiconductor body 22 with a drain electrode connection region 40 arranged. The source electrode connection region 37 has a metallic source electrode 45 on, that of an n ⁺ -type source zone 47 is surrounded and the bodyzone 36 contacted. The drain electrode connection region 40 has a drain electrode 46 on, that of an n ⁺ -type drain zone 48 is surrounded, which has the same conductivity type as the drift region 19 ,

The compensation cells 18 extend in the semiconductor body 22 to the substrate 23 , The semiconductor body 22 may have one or more epitaxial layers, and is on the substrate 23 same type of line as the compensation cells 18 applied by epitaxial crystal growth. However, the substrate is 23 extremely weakly doped in this embodiment, the acceptor concentration at this weak doping between 10 ¹³ cm ^-3 to 10 ¹⁵ cm ^-3 . This forms the substrate 23 for the heavily doped compensation cells 18 a coupling layer 24 that are electrically connected to the source area 20 via the compensation cells 49 extending vertically from the bodyzone 36 into the substrate 23 extend, communicating or over the back of the semiconductor body 22 connected directly to source. The doping of the substrate 23 is therefore extremely weakly doped, so that the voltage division function of the compensation cells 18 is maintained and no low-resistance short circuit between the compensation cells 18 over the substrate 23 he follows. Through this coupling layer 24 in the form of a lightly doped substrate 23 it is ensured that the heavily doped compensation cells charged in the blocking case 18 over the substrate 23 can discharge.

2a) shows a schematic plan view of the compensation semiconductor device 1 according to 1 in a first modification. For a better understanding of the drawing shows 2a) only the top 26 of the semiconductor body 22 , The structured metallization layers and the corresponding isolation layers of the compensation semiconductor device 1 are omitted. Only the electrically conductive strips of the source electrode 45 and the drain electrode 46 , which extend parallel and spaced apart in the direction of arrow C, are in this schematic representation of the top 26 of the semiconductor body 22 shown.

Perpendicular to the arrow C, in which the source electrode 45 and the drain electrode 46 extend, lies the section plane A-A ', which is a cross-section in 1 is shown. The columnar, in 1 illustrated highly doped compensation cells 18 are discharged from the lightly doped substrate as they extend into the substrate and across the P-type, in 1 shown series of compensation cells under the bodyzone 36 with the source electrode 45 are electrically connected. Thus, the substrate is at the potential of the source electrode 45 However, the voltage divider function of the heavily doped compensation cells 18 Therefore, ensured because the substrate with the above-mentioned concentration range between 10 ¹³ cm ^-3 to 10 ¹⁵ cm ^{-3 is} extremely low doped. The connection of the substrate to the source region can also take place via the backside of the semiconductor chip when the backside is placed on substrate potential.

In the section plane BB 'the 2a) extends between the source area 20 and the drainage area 21 a Driftge area 19 over the entire width of the MOS cell of the compensation semiconductor device 1 , The pillars of the heavily doped compensation cells 18 have in 2a) a square cross section 29 and are completely in the material of the complementary and weakly doped material of the drift region 19 embedded. In the blocking case of the complementary compensation semiconductor component 1 support the compensation cells 18 clearing out the charge carriers in the drift area 19 , The square cross section 29 supports advantageously an almost complete clearing out of the drift area 19 on load carriers.

2 B) shows a schematic plan view of the compensation semiconductor device 1 according to 1 in a second modification. Components having the same functions as in the previous figures are identified by the same reference numerals and will not be discussed separately. The second modification according to 2 B) differs from the first modification of the 2a) in that the compensation columns have a circular, round cross-section 28 exhibit.

3 shows a schematic cross section through a compensation semiconductor device 2 according to a second embodiment of the invention. In this second embodiment of the invention, the arrangement and density of the compensation cells remains 18 as well as the structure of the source area 20 and the drainage area 21 unchanged. However, in the first embodiment of the invention, a weakly doped substrate 23 the coupling layer between the highly doped compensation cells 18 is in this embodiment of the invention, a lightly doped p-type coupling layer 24 on the substrate 23 applied. This coupling layer 24 combines the high-doped compensation cells with high resistance 18 with each other, since the compensation cells 18 from the top 26 of the semiconductor body 22 until the weak do tated coupling layer 24 extend.

Consequently, the substrate can 23 be doped higher and as a p-type substrate 23 be used. The remaining structure of the lateral compensation semiconductor device 2 The second embodiment of the invention does not differ from the first embodiment of the invention. The weakly doped coupling layer 24 under the highly doped compensation cells 18 does not extend under the drainage area in this embodiment of the invention 21 although both are possible.

4 shows a schematic cross section through a compensation semiconductor device 3 according to a third embodiment of the invention. This embodiment of the invention differs from the preceding embodiments in that the compensation cells 18 neither through a coupling layer 24 on the substrate 23 still through the substrate 23 even as a high-impedance coupling layer 24 be electrically connected, but that between the compensation cells 18 and the top 50 of the substrate 23 a buffer zone 27 from material of the drift area 19 as usual in the art remains.

The electrical coupling is rather by a weakly doped p-type coupling layer 24 in the area of the top 26 of the semiconductor body 22 , While the ohmic connection in the prior art is implemented by geometrically narrow strips, it is possible here by correspondingly low doping of a large-area coupling layer 24 a similar effect can be achieved with the advantage that except for the first, the channel area 52 adjacent compensation cells 51 all other compensation cells 18 over the coupling layer 24 are interconnected over a large area, while the coupling layer 24 between the end of the channel and the compensation cells 51 adjacent to the channel have a structured transition, which does not unduly affect the channel effect.

5 shows a schematic cross section through a compensation semiconductor device 4 according to a fourth embodiment of the invention. This fourth embodiment of the invention differs from the preceding embodiments in that a lightly doped p-type layered coupling structure 25 partly on the top 26 of the semiconductor body 22 and partly on the substrate 23 is arranged. In this case, the weakly doped p-type coupling structure connects 25 on the substrate 23 at least the compensation cells 49 below the source area 20 with each other with a to the source area 20 adjacent row of coupling cells 51 , The remaining compensation cells 18 are via a coupling structure 25 on the top 26 of the semiconductor body 22 electrically connected with each other. This becomes the critical area between the channel area 52 and the first adjacent row of coupling cells 51 not directly to the bodyzone anymore 36 coupled, what the impairment of the channel area 52 reduced.

6 shows a schematic cross section through a compensation semiconductor device 5 according to a fifth embodiment of the invention. This fifth embodiment of the invention differs from the fourth embodiment of the invention only in that the series of compensation cells 49 under the bodyzone 36 as they are in 5 ge shows, no longer exists. But this is the coupling structure 25 on the substrate 23 towards the source area 20 been enlarged. This has the consequence that even without compensation columns under the body zone 36 the remaining draft area 19 can be completely cleared of storage supports in the case of blocking. The direct coupling of the bodyzone 36 with the coupling layer 24 However, this is no longer the case, so that the columns must be practically "floating" discharged by capacitive coupling after reaching the reverse voltage or an external connection between the source electrode 45 and the substrate 23 by a corresponding metallic compound is to make the compensation cells 18 via the coupling structure 25 to discharge, for example, in which the source electrode 45 and the p-type substrate 23 be set to ground potential.

7 shows a schematic cross section through a compensation semiconductor device 6 according to an embodiment of a further aspect of the invention. Components having the same functions as in the previous figures are identified by the same reference numerals and will not be discussed separately. The difference of this embodiment of the invention compared to the previous embodiments is that the compensation cells 18 are not equidistant from each other, but the distance a of the compensation cells 18 from the source area 20 to the drainage area 21 varied. In this particular sixth embodiment of the invention, the compensation semiconductor device 6 a compensation structure with a central area 30 between the source area 20 and the drainage area 21 on, in which the compensation cells 18 another, z. B. have a greater distance a ₁ than the compensation cells 18 with a distance a ₂ adjacent to the source region 20 or to the drainage area 21 are arranged. The advantageous effect of this distance variation will be in the following 8th to 10 explained in more detail.

8th shows schematic diagrams of the output capacitance C _DS as a function of the drain-source voltage U _DS . The curve I shows the characteristic curve of the output capacitance C _DS over the drain-source voltage U _DS for a vertical compensation semiconductor device with capacitive coupling of the compensation cells, wherein at very low drain-source voltage U _DS, the capacitance is relatively large. The capacitance C _DS then decreases at low drain-source voltage U _DS by more than an order of magnitude from and remains at this low output capacitance C _DS to reach the maximum drain-source voltage U _DS. The sudden drop at low source-drain voltages U _DS and the low, by more than a power of ten on a reduced output capacitance C _DS when reaching the maximum source-drain voltage U _DS caused in the conventional vertical Kompensationshalbleiterbauteilen in switching operation interference fields by overshoot, especially since the aperiodic limit case is not reached when switching due to the suddenly decreasing output capacitance C _DS .

The course of the output capacitance C _DS in dependence on the drain source voltage U _DS for conventional uncompensated lateral MOS structures schematically shows the curve II and demonstrates that the output capacitance C _DS remains relatively independent of the drain-source voltage U _DS. The effect of a steep drop in the output capacitance C _DS does not exist.

The curve II shows the curve of the output capacitance C _DS as a function of the drain-source voltage U _DS for a lateral MOS structure with charge-compensated drift path. The curve II shows a kind bath tub contour. On the one hand, the drain-source capacitance C _DS does not drop extremely in the middle region of the drain-source voltage U _DS , but instead remains on a capacitance which is smaller than in uncompensated lateral MOS structures and, on the other hand, with increasing drain-source voltage U _DS rises again. In this course of the source drain capacitance C _DS according to Kure III, the filtering effort to filter out interference fields can be reduced compared to vertical MOS structures and simultaneously achieved a space savings on the circuit boards, partly due to appropriate EMC filters (electromagnetic filters to meet compatibility standards ) can be omitted.

9 shows a schematic diagram of variations of the field strength E _m over the source-drain line with stored compensation cells. As can be seen from the diagram, the distances a _{2 of} the compensation cells adjacent to the source and drain regions are greater than the distances a ₁ in the central region. The larger distances are compensated in this case by a higher doping in the coupling layer. In this way, the electric field along the length l of the drift path can be well modulated with two design measures. Instead of a field increase can be such. B. at structural edges or field plate ends the field can be specifically lowered. The output capacitance can be adjusted particularly well by varying the p-type doping of the coupling layer and the distances of the compensation cells. In this case, in this embodiment 9 an increased doping of the coupling layer both near the source and in the vicinity of the drain and, in addition, increased distances a of the highly doped compensation cells are used. Due to the higher p-type doping, it is no longer possible to absorb so much potential between adjacent highly doped compensation cells, which lowers the achievable voltage. This effect can be counteracted by increasing the distance a.

10 shows two charging curves I and II, wherein the curve I corresponds to a charging curve for a lateral MOS structure of conventional components and the curve II in dashed lines shows the change of the charging curve through the MOS structure according to the invention. For small and large voltages results in a delayed voltage increase, so an increased capacity. The reason for this is that due to the higher doping of the coupling layer several highly doped compensation cells are cleared out at the same time. As a result, the capacity is greater in the moment in which these contiguous heavily doped compensation cells are detected by the field. Although the higher doped coupling layer is eliminated with the highly doped compensation cells of greater distance, the capacity goes back into the stage course. The location of the varied areas and the degree of variation can vary the capacity course within wide limits.

In the 10 Charging curves shown are a relatively rough approximation. With correspondingly weaker doping coupling structures and narrower interconnect paths, there is further scope for the variation of the charging curves and thus for the course of the source-drain capacitance. As the 10 shows, both at the beginning and at the end of reaching the reverse voltage greater capacity with the drain voltage increase can be realized. This has the advantage that the above-mentioned interference fields are superfluous and thus a considerable space savings on the boards as well as a reduction in the cost of the corresponding devices is possible.

11 shows a schematic cross cut through a compensation semiconductor device 7 according to a seventh embodiment of the invention. This schematic cross section shows the compensation semiconductor device 7 , the basis of in 9 and 10 shown diagrams. The distance a ₁ in the middle area 30 between the heavily doped compensation cells 18 here is less than the distance a ₂ for compensation cells 18 which are adjacent to the source area 20 or to the drainage area 21 are arranged. At the same time, the doping of the coupling layer 24 in the area of the larger-spaced compensation cells 18 higher than in the middle range 30 , with which the advantages mentioned above are connected. In this seventh embodiment of the invention, a buffer zone 27 between the substrate 23 and the compensation cells 18 complied with and the coupling layer 24 with variable doping surface area is in the top 26 of the semiconductor body 22 arranged. Furthermore, it is preferably possible that the distances of the compensation cells 18 from the source area 20 to the drainage area 21 vary, the coupling layer 24 but from the source area 20 to the drainage area 21 evenly weak dopant concentration. This has the advantage that the uniformly weak dopant concentration for the coupling layer can be achieved with a single doping process.

12 shows a schematic cross section through a compensation semiconductor device 8th according to an eighth embodiment of the invention. The difference from the semiconductor device according to 11 is that the coupling layer 24 for the electrical coupling of the heavily doped compensation cells 18 not on the top 26 of the semiconductor body 22 but on the top 50 of the semiconductor substrate 23 is arranged. The advantage of this eighth embodiment of the invention over the seventh embodiment of the invention is that the critical area between channel area 52 and the first row of adjacent highly doped compensation cells 51 from a p ^- -type coupling layer 24 remains. The other advantages of the seventh embodiment of the invention are retained for the eighth embodiment of the invention.

13 shows a schematic cross section through a compensation semiconductor device 9 according to a ninth embodiment of the invention. This compensation semiconductor device 9 shows a compensation structure 25 with compensation cells 18 whose distances a from each other from the source region 20 towards the drainage area 21 lose weight. In addition, the compensation semiconductor component has 9 a coupling layer 24 on the top 26 of the semiconductor body 22 on, whose dopant concentration from the source region 20 towards the drainage area 21 decreases. Also this compensation semiconductor component 9 shows advantages over compensation semiconductor components 9 with equidistantly arranged highly doped compensation cells 18 and with evenly weakly doped coupling layers 24 ,

14 shows a schematic cross section through a compensation semiconductor device 10 according to a tenth embodiment of the invention. This tenth embodiment of the invention, in turn, avoids the problems associated with a coupling layer 24 connected directly to the bodyzone 36 is coupled. Here is a coupling layer 24 with from the source area 20 to the drainage area 21 decreasing dopant concentration on the substrate 23 arranged and the highly doped compensation cells 18 reach into this coupling layer 24 , Nevertheless, the coupling layer remains 24 via the compensation cells 49 below the bodyzone 36 and thus with the source electrode 45 electrically connected.

15 shows a schematic cross section through a compensation semiconductor device 11 according to an eleventh embodiment of the invention. The difference to the ninth embodiment of the invention as it 13 shows is that under the bodyzone 36 no heavily doped compensation cell 18 is provided. For this the part of the coupling layer becomes 24 that is below the source area 20 extends, toward the source region 20 extended. The remaining heavily doped compensation cells 18 have a decreasing distance a from the source region 20 towards the drainage area 21 on. At the same time is the coupling layer 24 for these remaining highly doped coupling areas in the area of the top 26 of the semiconductor body 22 arranged. Thus, the at least one reaches the body area 36 immediately adjacent compensation cell 51 both in the layered coupling structure 25 on the top 26 of the semiconductor body 22 as well as in the weakly doped coupling structure 25 on the substrate 23 into it.

16 shows a schematic cross section through a compensation semiconductor device 12 according to a twelfth embodiment of the invention. This schematic cross section illustrates a further aspect of the invention in which a coupling layer 24 of substrate material is achieved in that below a coupling layer 24 made of substrate material 24 a buried area 31 is provided with complementary conductivity type p to the substrate material. The buried territory 31 limited on the one hand, the thickness d of the coupling layer 24 that also in 1 the entire substrate 23 On the other hand, it ensures that the voltage divider function of the heavily doped coupling zones 18 fully met. Components with sliding Functions as in the previous figures are identified by the same reference numerals and not discussed separately. In this twelfth embodiment of the invention, the body zone 36 towards the top 50 of the substrate 23 extended and on a highly doped compensation zone below the body zone 36 waived.

The effects of this complementarily doped buried territory 31 on the potential course within a compensation semiconductor device 12 will be with the 17 and 18 explained in more detail.

In 17 is done with the help of solid equipotential lines 54 as a function of the depth T in μm and as a function of the length l in μm along the source-drain line, the potential distribution in the substrate is shown. In this case, the initially strongly varying potential of highly doped compensation cell via weakly doped drift region to heavily doped compensation cell proceeds relatively quickly into equipotential lines which run parallel to the upper side of the semiconductor body in the semiconductor substrate or perpendicular to the compensation cells.

18 shows a schematic cross section of equipotential lines 54 a compensation semiconductor device according to 16 with buried complementary doped area. In this case, equipotential lines result, which penetrate into the semiconductor body perpendicular to the upper side of the semiconductor body and are aligned perpendicular to the compensation cells. This is achieved by decoupling the highly doped regions from the substrate via a space charge zone, although the highly doped compensation cells are incorporated into the substrate material of the coupling layer 24 protrude.

Become connected in this way the compensation cells via the substrate material, there is the advantage that in the case of switching the charge carriers on the can drain to source potential laid substrate. On the other hand arises In the manufacturing process, no limitation by the Distance of highly doped compensation cells to the substrate for formation a buffer zone must comply exactly. Crucial, however, is that through contact over the substrate no Einschaltwiderstandsverlust as opposed to a contact via a be placed in the drift zone placed coupling structure must, although the compensation cells contacted via the substrate become.

The space charge zone formed in the substrate by this buried, complementarily doped region decouples the compensation cells from the substrate potential when the compensation cells are adapted to the substrate doping at a distance from each other and in the doping. Ideally, the buried layer should not reach below the MOS cell, otherwise compensation will be needed there as well. This one has, like the 16 shows the advantage that in the case of switching the charge carriers can flow through this contact to the substrate.

19 shows a schematic cross section through a compensation semiconductor device 13 according to a thirteenth embodiment of the invention. In this embodiment of the invention, the buried region has a patterned buried layer 32 on. This textured buried layer 32 is in cells 33 divided. The gaps 34 of the substrate material between the cells 33 are dimensioned such that the substrate material in the case of blocking in these spaces 34 completely cleared of load carriers.

20 shows a schematic cross section through a compensation semiconductor device 14 according to a fourteenth embodiment of the invention. In this case, the buried territory stands 31 in the substrate material below the drain region 21 over a connection layer 35 same type of conductivity as the drift area 19 electrically connected. This has the advantage that the complementarily doped buried area 31 over the drift path in the drift area 19 not only capacitive to the potential of the drain zone 46 is coupled.

21 shows a schematic cross section through a compensation semiconductor device 15 according to a fifteenth embodiment of the invention. In this embodiment of the invention, the dopant concentration is in the buried region 31 in a middle area 30 between source and drain regions opposite regions arranged adjacent to the source and drain regions. With this variation of the dopant concentration of the buried region 31 can simultaneously the potential course in the drift area 19 between the compensation areas.

22 shows a schematic cross section through a compensation semiconductor device 16 according to a sixteenth embodiment of the invention. The difference from the previous embodiments of the invention is that the complementarily doped buried region 31 in the substrate material both below the drain region 21 as well as below the source area 20 is arranged. In addition, the body zone 36 of the source area 20 so deep into the semiconductor body 22 extended that a remaining area of the drift area 19 completely cleared of charge carriers in the blocking case. In this case, however, no connection layer to the drift region 19 under the drainage area 21 intended.

1

Compensation semiconductor component (1st embodiment)

2

Compensation semiconductor component (2nd embodiment)

3

Compensation semiconductor component (3rd embodiment)

4

Compensation semiconductor component (4th embodiment)

5

Compensation semiconductor component (5th embodiment)

6

Compensation semiconductor component (6th Embodiment)

7

Compensation semiconductor component (Seventh Embodiment)

8th

Compensation semiconductor component (8th embodiment)

9

Compensation semiconductor component (9th Embodiment)

10

Compensation semiconductor component (10th embodiment)

11

Compensation semiconductor component (11th Embodiment)

12

Compensation semiconductor component (12th Embodiment)

13

Compensation semiconductor component (13th embodiment)

14

Compensation semiconductor component (14th embodiment)

15

Compensation semiconductor component (15th embodiment)

16

Compensation semiconductor component (16th Embodiment)

17

Compensation semiconductor component (State of the art)

18

compensation cell

19

drift region

20

source region

21

drain region

22

Semiconductor body

23

substratum

24

coupling layer

25

coupling structure

26

top of the semiconductor body

27

buffer zone

28

round cross-section

29

square cross-section

30

mid-range

31

buried area

32

structured buried layer

33

cell the buried layer

34

gap between the cells

35

link layer

36

Body zone

37

Source electrode / connection area

38

gate electrode

39

Gate insulating layer

40

Drain electrode terminal area

41

n-type epitaxial layer

42

P-type tub

43

trench

44

p ^- conducting stripes

45

source electrode

46

drain

47

n ⁺ -conducting source zone

48

n ⁺ -type drain zone

49

compensation cell below the bodyzone

50

top of the substrate

51

compensation cells adjacent to the canal area

52

channel region

53

Walls of the trenches

54

equipotential

I

first turn in 8th

II

second turn in 8th

a

distance the compensation cells

a ₁

distance the compensation cells

a ₂

distance the compensation cells

A-A '

cutting plane

B-B '

cutting plane

C

arrow

C _DS

Drain-source capacitance

U _DS

Drain-source voltage

d

thickness the coupling layer

D

thickness the epitaxial layer

G

Gate contact

l

Along the length the source-drain route

n

n-type conductivity

p

p-conductivity type

S

Source contact

t

Time

T

depth the compensation cells

Claims (24)

Lateral compensating semiconductor component ( 1 ) with highly doped compensation cells ( 18 ) of a conductivity type (p), which in one of the compensation cells ( 18 ) surrounding drift area ( 19 ) with complementary conductivity type (s) between a source region ( 20 ) and a Draitgebiet ( 21 ) in a semiconductor body ( 22 ), the drift region ( 19 ) with the compensation cells ( 18 ) on a substrate ( 23 ) of the same conductivity type (p) as the compensation cells ( 18 ) is arranged, wherein the substrate ( 23 ) electrically to the source region ( 20 ) and wherein for the electrical coupling of the highly doped compensation cells ( 18 ) interconnect layers ( 24 ) or coupling structures ( 25 ) of the same conductivity type (p) as the compensation cells ( 18 ) in the lateral compensation semiconductor device ( 1 ) and with the source region ( 20 ) communicate electrically. Compensation semiconductor device according to claim 1, characterized in that the compensation semiconductor component ( 1 ) a weakly doped substrate ( 23 ) having the coupling layer ( 24 ), whereby the compensation cells ( 18 ) from the top ( 26 ) of the semiconductor body ( 22 ) into the weakly doped substrate ( 23 ) of the same conductivity type (p). Compensation semiconductor device according to claim 1 or claim 2, characterized in that a lightly doped layer on a heavily doped substrate ( 23 ), wherein the lightly doped layer is the coupling layer ( 24 ) and the compensation cells ( 18 ) from the top ( 26 ) of the semiconductor body ( 22 ) into the weakly doped coupling layer ( 24 ). Compensation semiconductor device according to claim 1, characterized in that a weakly doped layer in the region of the upper side ( 26 ) of the semiconductor body ( 22 ) the coupling layer ( 24 ) and the compensation cells ( 18 ) from the lightly doped layer in the area of the upper side ( 26 ) of the semiconductor body ( 22 ) to a buffer zone ( 27 ) of drift region material (s) over the substrate ( 23 ). Compensation semiconductor device according to claim 1, characterized in that a lightly doped layered coupling structure ( 25 ) partly on the top side ( 26 ) of the semiconductor body ( 22 ) and partly on the substrate ( 23 ), the weakly doped coupling structure ( 25 ) on the substrate ( 23 ) at least the compensation cells ( 18 ) below the body area ( 20 ) and the layered coupling structure ( 25 ) on the top ( 26 ) of the semiconductor body ( 22 ) the remaining compensation cells ( 18 ) electrically interconnects. Compensation semiconductor device according to claim 5, characterized in that the at least one of the body region ( 36 ) immediately adjacent compensation cell ( 51 ) in both the layered coupling structure ( 25 ) on the top ( 26 ) of the semiconductor body ( 22 ) as well as in the weakly doped coupling structure ( 25 ) on the substrate ( 23 ). Compensation semiconductor device according to claim 1, characterized in that a lightly doped layered coupling structure ( 25 ) partly on the top side ( 26 ) of the semiconductor body ( 22 ) and partly on the substrate ( 23 ), the weakly doped coupling structure ( 25 ) on the substrate ( 23 ) at least below the source region ( 20 ) in such a way towards the source area ( 20 ) that the doping of the drift region ( 19 ) in the blocking case without additional highly doped compensation cells ( 18 ) is compensated. Compensation semiconductor device according to one of the preceding claims, characterized in that the compensation cells ( 18 ) is columnar from the top ( 26 ) of the semiconductor body ( 22 ) from orthogonal to the top ( 26 ) in the semiconductor body ( 22 ) and a round cross section ( 28 ) or an oval or a polygonal, preferably a hexagonal, or a square ( 29 ) or have a rectangular cross-section. Compensation semiconductor device according to one of the preceding claims, characterized in that the compensation cells ( 18 ) are not equidistant from each other, but the distance (a) of Kom pensationszellen ( 18 ) from the source area ( 20 ) to the drainage area ( 21 ) varies. Compensation semiconductor device according to one of the preceding claims, characterized in that the distances of the compensation cells ( 18 ) from the source area ( 20 ) to the drainage area ( 21 ), the coupling layer ( 24 ) but from the source area ( 20 ) to the drainage area ( 21 ) evenly weak dopant concentration. Compensation semiconductor device according to one of the preceding claims, characterized in that the coupling layer ( 24 ) has not a uniformly weak dopant concentration, but one with the distance variation of the compensation cells ( 18 ) correlated increasing impurity concentration with increasing distances (a ₁ , a ₂ ) between the compensation cells ( 18 ) having. Compensation semiconductor device according to one of Claims 9 to 11, characterized in that the compensation semiconductor component ( 6 ) a compensation structure with a central area ( 30 ) between the source area ( 20 ) and the drainage area ( 21 ), in which the compensation cells ( 18 ) have a greater distance (a ₁ ) than the compensation cells ( 18 ) adjacent to the source region ( 20 ) and the drainage area ( 21 ) are arranged. Compensation semiconductor device according to one of Claims 9 to 11, characterized in that the compensation semiconductor component ( 7 ) a compensation structure with a central area ( 30 ) between the source area ( 20 ) and the drainage area ( 21 ), in which the compensation cells ( 18 ) have a smaller distance (a ₁ ) than the compensation cells ( 18 ) adjacent to the source region ( 20 ) and the drainage area ( 21 ) are arranged and one being at the top ( 26 ) of the semiconductor body ( 22 ) arranged coupling layer ( 24 ) a lower dopant concentration in the central region ( 30 ) as adjacent to the source ( 20 ) and the drainage area ( 21 ). Compensation semiconductor device according to one of Claims 9 to 11, characterized in that the compensation semiconductor component ( 12 ) a compensation structure with a central area ( 30 ) between the source area ( 20 ) and the drainage area ( 21 ), in which the compensation cells ( 18 ) have a smaller distance (a ₁ ) than the compensation cells which are adjacent to the source region ( 20 ) and the drainage area ( 21 ) and one on the substrate ( 23 ) arranged coupling layer ( 24 ) a lower dopant concentration in the central region ( 30 ) as adjacent to the source ( 20 ) and the drainage area ( 21 ). Compensation semiconductor device according to one of Claims 9 to 11, characterized in that the compensation semiconductor component ( 9 ) a compensation structure with compensation cells ( 18 ) whose distances (a) from each other from the source region ( 20 ) to the drainage area ( 21 ), and the one coupling layer ( 24 ) on the top ( 26 ) of the semiconductor body ( 22 ) whose dopant concentration from the source region ( 20 ) towards the drainage area ( 21 ) decreases. Compensation semiconductor device according to one of Claims 9 to 11, characterized in that the compensation semiconductor component ( 10 ) a compensation structure with compensation zones ( 18 ) whose distances (a) from each other from the source region ( 20 ) to the drainage area ( 21 ), and the one coupling layer ( 24 ) on the substrate ( 23 ) whose dopant concentration from the source region ( 20 ) towards the drainage area ( 21 ) decreases. Compensation semiconductor device according to one of Claims 9 to 11, characterized in that the compensation semiconductor component ( 11 ) a compensation structure with compensation zones ( 18 ) whose distances (a) from each other from the source region ( 20 ) towards the drainage area ( 21 ), and the one coupling layer ( 24 ), partially on the top ( 26 ) of the semiconductor body ( 22 ) and partly on the substrate ( 23 ), the dopant concentration of which from the source region ( 20 ) towards the drainage area ( 21 ) and wherein the coupling layer ( 24 ) on the substrate ( 23 ) at least below the source region ( 20 ) in such a way towards the source area ( 20 ) that the doping of the drift region ( 19 ) is compensated in the blocking case without additional highly doped compensation cells. Compensation semiconductor device according to claim 1, characterized in that the substrate material, the coupling layer ( 24 ), whereby the compensation cells ( 18 ) from the top ( 26 ) of the semiconductor body ( 22 ) into the substrate ( 23 ) of the same conductivity type (p) and a buried area ( 31 ) is arranged with complementary conductivity type (s) at a defined distance from the top of the substrate material. Compensation semiconductor device according to claim 18, characterized in that the buried region ( 31 ) has a layer located in the substrate ( 23 ) from the drainage area ( 21 ) towards the source region ( 20 ), but not below the source region ( 20 ) in the substrate ( 23 ) is arranged. Compensation semiconductor device according to claim 18, characterized in that the buried region ( 31 ) a structured buried layer ( 32 ) in cells ( 33 ), the space ( 34 ) of substrate material (p) between the cells ( 33 ) is dimensioned such that the substrate material (p) in the blocking case in these spaces ( 34 ) is completely cleared of charge carriers. Compensation semiconductor device according to claim 18 or claim 19, characterized in that the buried region ( 31 ) in the substrate material (p) below the drain region ( 21 ) via a connection layer ( 35 ) of the same conductivity type (s) as the drift region ( 19 ) is electrically connected. Compensation semiconductor device according to claim 18 or claim 19, characterized in that the dopant concentration in the buried region ( 31 ) varies. Compensation semiconductor device according to claim 18, characterized in that the dopant concentration in the buried region ( 31 ) in a middle area ( 30 ) between source ( 20 ) and drainage area ( 21 ) opposite to the source ( 20 ) and drainage areas ( 21 ) arranged areas is reduced. Compensation semiconductor device according to claim 18 or claim 19, characterized in that the buried region ( 31 ) in the substrate material (p) from below the drain region ( 21 ) to below the source area ( 20 ) and that the body zone ( 36 ) of the source area ( 20 ) so deeply into the semiconductor body ( 22 ) that a remaining area ( 31 ) of the Drift zone ( 21 ) is completely cleared of charge carriers in the blocking case.