DE102005022126B4 - A method of determining a drive algorithm for a counter to form a clock signal and counter and control arrangements for driving the counter - Google Patents

Abstract

Method for determining a triggering algorithm (AL) for a counter (Z) for forming a clock signal (t _A ) which is periodically synchronous with a predetermined clock signal (t _T ), wherein the clock signal (t _A ) consists of a base clock signal (t _B ) is formed,
a) in which the from the ratio of the clock periods (T _B , T _T ) of the base clock signal (t _B ) and the predetermined clock signal (t _T ) derived adjacent integer quotients a first and second counting algorithm (ZA1, ZA2) for the counter (Z represent)
b) in which the clock periods (T _B ) of the base clock signals (t _B ) according to the first and second counting algorithm (ZA1) are summed and compared with the clock period (T _T ) of the clock signal to be formed (t _T ),
c) in which each of those as the next counting algorithm (ZA1, ZA2) is determined, the summed clock periods (T _B ) is closer to the clock period (T _T ) of the clock signal to be formed (t _T ), and
d) at b) and c) are repeated until an edge of the clock signal (t _A ) with the predetermined ...

Description

In Components of digital communication networks, such as Switching or transmission equipment, are for the timely switching or transmission of the digital information clock generators intended. In these clock generators are those for the respective Facilities required clock signals generated. A possibility the generation of a digital clock signal is from a base clock signal derive a clock signal, wherein the base clock signal is compared to the Clock signal much higher Frequency has. For the synchronization of the derived clock signal with the clock signal, usually voltage-controlled oscillators are provided, their realization However, a high economic outlay mean.

In the DE 196 53 723 A1 a method and a device for frequency generation is described in which a target frequency is generated from a fundamental frequency, wherein the fundamental frequency is divided by a determined for the respective target frequency division factor. A fractional division factor is generated from an addition of two weighted integer division factors. The division factors are determined successively by mathematical operations and controlled to a divider block.

From the EP 0 471 506 A2 For example, there is known a digital phase locked loop for generating a clock signal from a reference signal in which a programmable divider is dynamically controlled by means of the reference signal and a phase error signal.

US 5,473,553 discloses a frequency divider unit in which the frequency of an input signal is divided by a parameterized number to obtain an output signal having an output frequency. In the frequency divider unit, the input signal is precisely divided by a cycle stealing method, eliminating periods of input signal for division.

The The object underlying the invention is the digital Generating a clock signal based on a base clock signal, especially with regard to an economic realization improve. The object is achieved by the independent claims 1 and 4 and 9 to 13 solved.

An essential aspect of the invention is that a Ansteueralgorithmus is determined for a single counter to which a one of a base clock signal (t _B) formed clock signal (t _A) periodically in synchronization with a predetermined clock signal (t _T) is held, wherein the maximum phase deviation of the clock signal relative to the predetermined clock signal is at most half the clock period of the base clock signal. This means that at high frequencies of the base clock signal with respect to the predetermined clock signal, the jitter of the clock signal is minimized.

One Another essential aspect of the invention is that from the determined control algorithm for the control of the counter more Control algorithms for a counter structure be determined with the counter be controlled according to the determined control algorithm can. This is for everyone another counter a further control algorithm provided, wherein a counter of the counter structure each the previous counter according to the others determined control algorithms controls.

One Advantage of the invention is the fact that from a base clock signal a clock signal which is periodically synchronous with a predetermined clock signal with almost any frequency with the least economic effort can be generated, especially when on electronic assemblies existing oscillators a basic clock signal is available, from which a clock signal of arbitrary frequency can be formed. Furthermore, the invention is for Clock signals with high frequencies circuitry and clock signals with lower frequencies programmatically in a processor-controlled Device feasible, with mixed implementations circuitry / program technology are advantageous. Both in the circuit, as well in the program implementation, already existing circuitry - for example FPGA's - or programmatic - for example Program Memory - Resources be advantageously shared. Also, with the help of the invention the clock signal formed with the least economic effort on a lead clock signal be synchronized, with a realization both circuitry as well as programmatically with the least economic effort is possible.

Further advantageous embodiments of the invention, in particular very economical implementations in counter arrangements in which the control algorithms are provided for the counter and other control algorithms for the other counters, and arrangements in which the counter and the counter lerstruktur or the counter is controlled solely by a processor-controlled device according to the determined control algorithms, can be found in the further claims.

in the The invention will be explained in more detail with reference to an embodiment. there demonstrate

1 in a flow chart the determination of the control algorithm for the counter,

2 in a flowchart, the determination of the other control algorithms for the counter structure and

3 a circuit arrangement with a counter and a counter structure according to the determined control algorithms.

For the in 1 illustrated flow diagram is assumed that a clock signal t _A is to be generated from a base clock signal t _B with a clock frequency of 100 MHz, which has minimal deviations from a predetermined clock signal t _T with a clock frequency of 8.192 MHz. For this purpose, a counter Z - see 3 - Provided, which is clocked by the base clock signal t _B , and is set to a first counting algorithm ZA1. With the aid of an enable / disable input E / D of the counter Z, the counter Z can be enabled or disabled such that a second counting algorithm ZA2 is reached.

In 1 is a flowchart for the determination of a control algorithm AL for the counter Z, in particular for the enable / disable input E / D shown, in which on the one hand the desired, ie the clock signal to be formed t _A with the desired frequency at the output A of the counter Z. is present and periodically synchronous with the predetermined clock signal t _T.

After the start of the flow chart, the two counting algorithms are AL1, AL2 for the counter Z for the given clock signal according to the embodiment _T t calculated. For this purpose, the clock period T _{T of} the predetermined clock signal t _T and the clock period T _{B of} the base clock signal t _{B is} determined, and then the clock period T _{T of} the predetermined clock signal t _{T divided} by the clock period T _{B of} the base clock signal t _B. Based on the embodiment, a quotient of 12.20703125 is calculated at a frequency of the base clock signal t _B of 100 MHz and a frequency of the predetermined clock signal t _T of 8.192 MHz. By the mathematical expression floor only the integral part of the quotient, ie the number 12 is determined as the first counting algorithm ZA1. The increase of the floor quotient by the count value 1 defines the second counting algorithm ZA2. In relation to the exemplary embodiment, this is the number 13. The count factor N is set to zero at the beginning of the sequence and indicates the number of clock periods T _{B of} the clock signal t _A. The index i indicating the number of clock periods T _{T of} the predetermined clock signal t _T is set to 0 before the start of the sequence.

With the beginning of the process, the index i is increased by 1 and the edge separation .DELTA.T between the base clock signal T _B and the clock signal T _{T determined for} both the first and the second counting algorithm ZA1, ZA2. Here, the edge distance .DELTA.T (ZA1) of the first counting algorithm ZA1 is determined by the current number N of the clock periods T _{B of} the base clock signal t _B each by the counting algorithm ZA1 - in the specific case by 12 - increased and then with the clock period T _{B of} the base clock signal t _{B is} multiplied. Of these, the i clock periods T _{T of} the clock signal T _{T to be formed are} subtracted. Analogously, the edge distance .DELTA.T for the counting algorithm ZA2 is determined. Depending on whether the absolute value of the edge spacing ΔT (ZA1) of the first counting algorithm ZA1, or the edge spacing ΔT (ZA2) of the second counting algorithm ZA2 is greater or less, either the first counting algorithm ZA1, or the second counting algorithm ZA2 in the driving algorithm AL for the counter Z stored. Furthermore, in this process step, the current number N is increased by the first or second counting algorithm ZA1, ZA2-that is, the number 12 or 13.

In the next step, it is checked whether the rising edge of the formed clock signal t _A and the predetermined clock signal t _T coincide. If this is not the case, the process is repeated until collapse of the flanks is achieved. In this case, a first or a second counting algorithm ZA1, ZA2 is determined and entered into the control algorithm AL for the counter Z as described above during each run or sequence. If the two rising edges coincide, a periodic synchronism of the clock signal t _A formed from the base clock signal t _B and the predetermined clock signal t _{T is} achieved, ie according to the sequence of the registered first and second counting algorithms ZA1, ZA2 specified in the control algorithm AL Achieved synchronism. This means that the counter Z is formed at a triggering of its enable / disable input E / D according to the determined control algorithm AL, a clock signal t _A , that after passing through the sequence specified in the control algorithm AL first and second counting algorithms ZA1, ZA2 is periodically synchronous with the predetermined clock signal t _T.

For the embodiment with the base clock t _B at 100 MHz and the predetermined clock signal t _T of 8.192 MHz, the following control algorithm AL results, it being noted that the first counting algorithm 12 by digital information 11 and the second counting algorithm 13 by the digital information 12th is represented:

The control algorithm AL has 256 individual counting algorithms ZA, wherein the counting factor ZA in each case indicates the counting factor with which the counter Z counts the base clock signals t _B until it outputs a clock signal t _A at its output. After the counting algorithms ZA 256 is from the basic clock signal t _B t _A clock signal formed with the predetermined clock signal t _T phase synchronous again. As a result, a periodic phase synchronism is achieved, which can be provided for the formation of clock signals t _T with low jitter, if the frequency of the base clock signal t _B compared to the clock signal t _{T is} much higher - for example, 1:10.

Of the determined driving algorithm AL, for example, in a memory a microprocessor-controlled device - not shown - introduced become. The microprocessor-controlled device controls the enable / disable input E / D of the meter Z according to the stored driving algorithm AL.

According to the invention, the ascertained control algorithm AL can be analyzed to this effect, further control algorithms AL1... ALx for a counter structure ZS - see also 3 - To determine, by means of which the counter Z is controlled. The inventive method for this purpose is based on the in 2 explained flowchart explained in more detail.

To the sequence start is the number N + 1 of the counting algorithms ZA in the drive algorithm AL and the values for the first and second counting algorithms ZA1, ZA2 - d. H. the values 11 and 12 are determined. In addition, the index n, the the current number of counting algorithms ZA indicates 0 and an index z indicating the successive ones same counting algorithms ZA indicates 0.

In In a first step, it is examined whether the 1st and the Nth counting algorithm ZA is the same. If equal, the Nth counting algorithm will be used ZA to the 1st counting algorithm ZA postponed until there is an inequality - ring exchange. This mechanism is necessary, otherwise the analysis would be more complicated, what an elevated one Implementation costs would mean.

To a review that the Nth counting algorithm not yet reached - im embodiment the 256th -, it is determined whether the current counting algorithm ZA [n] with the preceding counting algorithm ZA [n - 1] matches. With agreement the index z is increased by 1 and then n by 1. are the counting algorithms ZA differs from the current index z as the first another, first or second counting algorithm w1ZA1, w1ZA2, entered in the first control algorithm AL1 or saved. Subsequently z is set to 0 and n is increased by 1. According to the embodiment, the first another, first or second counting algorithm w1ZA1, w1ZA2 take the values 3 or 4.

For the exemplary embodiment, the following first triggering algorithm AL1 with the in 2 Darge established procedures:
4-4-4-4-4-3-4-4-4-4-4-3-4-4-4-4-4-3-4-4-4-4-4-3-4- 4-4-4-3-4-4-4-4-4-3-4-4-4-4-4-3-4-4-4-4-3-4-4-4-4- 4-3-

This means that the first counter Z1 of the counter structure ZS counts the clock signals t _A formed at the output A of the counter Z with the count factor 3 or 4 and controls the enable / disable input E / D of the counter Z, in each case from the count factor 0 to 3 or 0 to 4 has gone out - see also 3 ,

The determined first triggering algorithm AL1 for the first counter Z1 of the counter structure ZS is then further analyzed if a plurality of first further counting algorithms w1ZA - in the exemplary embodiment, w1ZA = 52 - are present in the first triggering algorithm AL1. Since several w1ZA are specified, the first drive algorithm AL1 is further analyzed. For this purpose, in turn, the method after 2 is used, wherein in the run a second control algorithm AL2 is determined, are entered into the second additional, first and second counting algorithms w2ZA1, w2ZA2.

For the embodiment, the following second control algorithm AL2 with the in 2 determined method determined:
5-5-5-5-5-5-5-5-4-

This means that the clock signal output at the output A1 of the first counter Z1 of the counter structure ZS is counted to 4 or 5 in the second counter Z2 in accordance with the second control algorithm AL2 and the first counter Z1 is enabled or disabled after each counting process - 5 or 4 - please refer 3 ,

The determined second triggering algorithm AL2 for the second counter Z2 of the counter structure ZS is then further analyzed if a plurality of second further counting algorithms w2ZA - in the exemplary embodiment, w2ZA = 8 - are present in the second triggering algorithm AL2. Since several second further counting algorithms w2ZA are specified, the second triggering algorithm AL2 is further analyzed. For this purpose, in turn, the method after 2 is used, wherein in the passage a third control algorithm AL3 is determined, in the third additional, first and second counting algorithms w32ZA1, w3ZA2 be entered.

For the embodiment, the following third drive algorithm AL3 with the in 2 determined method: 8

This means that the clock signal output at the output A2 of the second counter Z2 of the counter structure ZS is counted to 8 in the third counter Z3 in accordance with the third triggering algorithm AL3 and the second counter Z3 is enabled or disabled after the counting process - see 3 ,

There in the third control algorithm AL3 only one counting algorithm ZA entered is no further analysis of the third triggering algorithm AL3 required and the analysis is finished.

With Help of the analysis of the driving algorithm AL was for the embodiment a counter structure ZS determines that by three counters Z1 .. Z3 is formed, wherein the output A1 .. A2 of the respective Counter Z1 Z3 the enable / disable input E / D of the previous counter Z, Z1, Z2 controls.

This counter structure ZS and the counter Z are for the embodiment in 3 illustrated, wherein the structure is supplemented by a control device ST, with the help of which the clock signal to be formed t _{A is} to be synchronized with a guide clock signal t _F.

The output A of the counter Z is via a first AND gate U1 to the enable / disable input E / D of the first counter Z1, via a second AND gate U2 to the enable / disable input E / D of the second counter Z2 and over a third AND gate U3 is connected to the enable / disable input E / D of the third counter. The output A of the first counter Z1 is connected via the control device ST to the enable / disable input E / D of the counter Z and to a further input of the second and third AND gate U2, U3. The output A of the second counter Z2 is routed to a further input of the third AND gate U3 and the first AND gate. The output A of the third counter Z3 is coupled to a further input of the second AND gate. At the clock inputs CLK of the counter Z, Z1 .. Z3, the base clock signal t _{B is passed} at a frequency of 100 MHz, ie with each clock of the base clock signal t _B counter Z, Z1 .. Z3 count, if the count by the release - / lock input E / D is enabled. Through the enable / disable input E / D, the count for each of the counters Z, Z1 .. Z3 can be controlled according to the determined control algorithm AL, AL1 .. AL3, in each case starting from the counter Z of the following counter Z1 .. Z3 the respective preceding according to the respectively determined control algorithm AL, AL1 .. AL3 controls.

According to the embodiment, a clock signal t _{A is} generated with this counter arrangement of a base clock signal t _B with a clock frequency of 100 MHz, which has minimal deviations from a predetermined clock signal t _T with a clock frequency of 8.192 MHz, the rising edges of the two clock signals t _A. , _{T T are} synchronized after each 256 clock period T _{T of} the predetermined clock signal t _T. This means a periodic phase synchronism of the two clock signals t _A , t _T and a maximum jitter of the clock signal formed t _A , which is maximum at half the clock period of the base clock signal t _B.

In a phase measuring unit, not shown, the phase deviation between the guide clock signal t _F and the clock signal t _A formed from the base clock signal t _{B is} determined. As a predetermined clock signal t _T , the clock signal t _{T is defined} at a frequency of 8.192 MHz with the calculated clock period of 122.0703125 ns. As the comparison frequency, the largest common divisor of the two clocks t _F , t _{T is} determined. The frequency of the two clock signals t _F , t _T is divided down by respective clock dividers on comparison clocks with that same frequency, which represent a common divider with respect to the frequencies of the two clock signals t _F , t _A. The phase measurement itself - not shown - can be performed by shift register chains or time measurements of the edge distance at the same frequency of the comparison clocks. For the invention it is essential that the control device is informed whether the edge of the ge formed clock signal t _A with respect to the edge of the leading clock f _F nach- or advanced - in 3 by two designated +/- arrows and the label clock signal t _A / f _F indicated.

In the control device ST is an enable / disable unit FSE provided with the help of the incoming information "edge rushes forward" is implemented such that the counter Z is released by an additional clock period T _{B of} the base clock t _B , ie the respective clock period T _a of the to be formed clock signal t _a is shortened. Analogously, the enable / disable unit FSE is designed such that an incoming information "edge lags", the counter Z by one clock period T _B of the basic clock t _B is blocked, that is, the respective clock period T _{A of} the clock signal to be formed t _A is extended.

In order to continue to form a clock signal t _A with the previous accuracy in terms of synchronism in case of failure of the control clock signal t _F , are continuously measuring intervals - for example, multiples of the clock period of the comparison signal - provided in which detects the extensions and shortenings of the clock signal to be formed t _A. be - not shown. For each measuring interval, the recorded extensions and shortenings are summed separately and the difference between the totals is then formed. After the difference formation, shortenings or extensions - ie 0 to y - of the clock signal t _{A to be formed result} . These 0 to y truncations or extensions are stored until a result of the next measurement interval is available. If the control clock signal t _F fails, then the 0 to y extensions or shortenings of the last completely passed measurement interval are used for the further control of the clock signal t _A. This means that as long as the management clock signal t _{F has} failed, the same number 0 to y of extensions or shortenings of the clock signal t _{A is made} based on the time duration of a measurement interval. With several shortenings or extensions, these are advantageously distributed uniformly over the duration of a measurement interval.

The Invention is not on the embodiment limited and can be used in all, in particular, telecommunications equipment be used in the from a base clock signal - advantageous if already present - a Clock signal to be formed with any frequency, the Jitter of the clock signal to be formed is minimized when the frequency the base clock signal is much higher than that of the forming clock signal is.

Claims (13)

Method for determining a triggering algorithm (AL) for a counter (Z) for forming a clock signal (t _A ) which is periodically synchronous with a predetermined clock signal (t _T ), wherein the clock signal (t _A ) consists of a base clock signal (t _B ) is formed, a) in which the from the ratio of the clock periods (T _B , T _T ) of the base clock signal (t _B ) and the predetermined clock signal (t _T ) derived adjacent integer quotients a first and second counting algorithm (ZA1, ZA2) for representing the counter (Z), b) in which the clock periods (T _B ) of the base clock signals (t _B ) according to the first and second counting algorithm (ZA1) summed and compared with the clock period (T _T ) of the clock signal to be formed (t _T ) c) in which each of those as the next counting algorithm (ZA1, ZA2) is determined whose summed Taktpe ( _b ) is closer to the clock period (T _T ) of the clock signal (t _T ) to be formed, and d) are repeated at b) and c) until an edge of the clock signal (t _A ) with the predetermined clock signal (t _T ) is synchronous, wherein the periodic sequence of the first and second counting algorithms (AL1, AL2) represents the driving algorithm (AL) for the counter (Z). A method according to claim 1, characterized in that the clock periods (T _B , T _T ) of the base clock signal (t _B ) and the clock signal (t _T ) have a common multiple. A method according to claim 1 or 2, characterized in that the rising edges for the beginning of a clock period (T _T ) of the predetermined clock signal (t _T ) and of the base clock signal (t _B ) formed clock signal (t _A ) and for determining the Synchronism of the clock signal (t _A ) with the predetermined clock signal (t _T ) are used. A method of analyzing according to any one of claims 1 to 3 determined control algorithm (AL) for controlling a counter (Z) through an additional counter structure (ZS), a) in the case of equality of the first and last counting algorithm (ZA (0), ZA (N)) of the control algorithm (AL), the respective last counting algorithm (ZA (N)) to the first counting algorithm (ZA (0)) until the counting algorithms (ZA) are different are, b) starting with the first counting algorithm (ZA (0) of the driving algorithm (AL) in each case the number (z) of the successive same, until a change to the other counting algorithm (ZA2) occurs counting algorithms (w1ZA1, w1ZA2) is determined, whereby by the different Number (z) of one of the other two counting algorithms (w1ZA1, w1ZA2) is determined and after evaluation of the control algorithm (AL) the periodic sequence of each currently determined, further counting algorithms (w1ZA1, w1ZA2) another driving algorithm (AL1) for a first counter (Z1) of the counter structure (ZS) represents, and c) in the case of b) as long as Further control algorithms (AL2 .. ALx), based on the previous one determined, further control algorithms (AL1 .. ALx - 1) determined until a one-digit number of other counting algorithms (wxZAx) is reached, whereby each further control algorithm (AL2 .. ALx) for another counter (Z2 .. Zx) of the counter structure (ZS) is provided and the respective further counter (Z2 .. Zx) the previous counter (Z1 .. Zx - 1) controls. Method according to claim 4, characterized in that that the equality of successive, until the change to other counting algorithm (ZA) occurring counting algorithms (ZA) by comparing the current (ZA (n)) with the previous one counting algorithm (ZA (n - 1)) is determined. Method according to one of claims 1 to 5, characterized in that in a synchronization of a control clock signal (t _F ) with the clock signal (t _A ), a common mode signal from the clock signal t _A and the guide clock signal t _{F is} derived that the phase comparison at a frequency of Lead clock signal (t _F ) and predetermined clock signal t _T , which corresponds to a common divisor of the frequencies of the two clock signals t _T , T _F , and that according to the phase comparison result of the enable / disable input EID of the counter (Z) taking into account the driving algorithm (AL ) is enabled or disabled, causing a shortening or an extension of the clock period (T _A ) of the clock signal (t _A ) is effected. A method according to claim 6, characterized in that within a predetermined measurement interval, each shortening or lengthening of the clock period (T _A ) of the clock signal (t _A ) detected, and the extensions and the shortenings are summed in each case and the difference of the sums is formed, and that in case of failure of the management clock signal t _F , the shortening or extensions of the last measurement interval are performed in accordance with the difference formed in the rhythm of the measurement interval. A method according to claim 7, characterized in that in case of failure of the management clock signal t _F according to the difference formed in several shortenings or extensions of the clock period (T _A ) of the clock signal (t _A ), they are evenly distributed within a measurement interval. Control arrangement for one according to one of the claims 1 to 3 formed algorithm (AL), characterized in that an enable / disable input E / D and the output (A) of the counter (Z) is connected to a processor-controlled device, wherein in the processor-controlled device the drive algorithm (AL) for the counter (Z) is realized programmatically. Counter arrangement for further algorithms (AL1 .. AL3) formed according to claim 4 or 5 for a counter structure (ZS), characterized in that the output (A) of a counter (Z) and further counters (Z1 .. Z3) of the counter chain-oriented counter structure (ZS) are respectively connected via AND gates (U1 .. U3) to an enable / disable input (E / D) of the respective the following further counter (Z1 .. Z3) of the counter structure (ZS) is connected, that in each case the output (A) of the further counter (Z1 .. Z3) via the respectively existing AND gate (U1 .. U3) with the release / Block input (E / D) of each preceding counter (Z .. Z2) of the counter structure (ZS) is connected, wherein for each further control algorithm (AL1 .. AL3) another counter (Z1 .. Z3) in the counter structure (ZS ) and the set first counting algorithm (ZA1) of the respective further counter (Z1 .. Z3) in the second counting algorithm (ZA2 ) is controlled. Control arrangement for according to claim 4 or 5 formed Further algorithms (AL1 .. AL3) for a counter structure (ZS), thereby characterized in that the enable / disable inputs (E / D) of the counter (Z) and the other counter (Z1 .. Z3) of the counter structure (ZS) are connected to a processor-controlled device, wherein in the processor-controlled device the drive algorithm (AL) for the counter (Z) and the other control algorithms AL1 .. A3 for the counters (Z1 .. Z3) of the counter structure (ZS) are implemented in the program. Control arrangement according to Claim 11, characterized that in the processor-controlled device additionally the method for analysis of the determined according to claim 1 Ansteueralgorithmus (AL) for a control a counter (Z) by an additional counter structure (ZS) is realized by programming, and that an input unit is provided for inputting the drive algorithm (AL) for the counter (Z). Control arrangement according to claim 9 or 12, characterized in that in the processor-controlled device, the method for determining the control algorithm (AL) programmatically realized and input units are provided, with the aid of which the frequencies of the base clock signal (t _B ) and the predetermined clock signal (t _T ) are input and stored, with the frequency of the base clock signal (t _B ) and the predetermined clock signal (t _T ) of the control algorithm (AL) is determined.