DE102005020075A1 - Manufacturing method for ditch structure semiconductor device involves forming neighboring ditch structures simultaneously in common process block - Google Patents

Abstract

A method is proposed for producing a trench structure semiconductor device (10). In this case, a first and a second trench structure (30, 40) are formed in a semiconductor material region (20) at the same time or in a common process block in close temporal proximity, so as to achieve a particularly good alignment of the first and second trench structures (30, 40). inherently to achieve in relation to each other.

Description

The The present invention relates to a method for producing a Trench structure semiconductor device and in particular also a method for the production of optimally adjusted trench structures, trenches or Trenches using combined trench etching.

at the production and further development of modern semiconductor technologies are increasingly semiconductor devices with or based on so-called trench structures, trenches or trenches used and used. These trenches are lost, starting from a surface area, e.g. a semiconductor material region, perpendicular in the material region, in which the semiconductor device is formed or formed shall be. To provide various functionalities or also a plurality of semiconductor devices in a common Material range is often the provision of a plurality with regard to different on their geometry and / or on their functionality Trench structures necessary. The different ones have to do this trench structures often to be provided in a decidedly geometric Relationship with each other to the functional integrity of the whole Ensure semiconductor device to be able to. This means that different trench structures are related to each other adjusted arranged and trained must be.

traditionally, Different trench structures are also based different manufacturing processes in one underlying Material formed, and therefore it requires a considerable Effort to adjust the different trench structures to each other, so the desired geometric relationships of the different trench structures in relation to each other to be able to.

Of the Invention is based on the object, a method for forming to provide a semiconductor device in which an adjustment different trench structures in relation to each other on particular simple and reliable Way can be realized.

Is solved the object underlying the invention in a method for producing a semiconductor device having the features of the independent patent claim 1. Preferred embodiments of the inventive method for Producing a semiconductor device are the subject of the dependent subclaims.

proposed a method for producing a trench structure semiconductor device, in which according to the invention in one Semiconductor material region having a surface area at least one first trench structure of a first type and outside the first trench structure at least one second trench structure of a second and of the first Type of different types are formed, wherein the first trench structure of the first type or a part thereof and the second trench structure of the second type or part of it at the same time, essentially simultaneously and / or in a common process block in time be formed adjacent.

It is an idea of the present invention, trainees different Trench structures simultaneously, substantially simultaneously and / or in a common process block with a temporal neighborhood form to each other, thereby inherently an adjustment of the different trench structures inherent in relation to each other to ensure. It comes thus in particular on the temporal proximity derjeni conditions operations which are carried out to form the respective trench structures have to. It may be within the meaning of the invention to a strict simultaneity or a very close temporal proximity act on the respective processes, so this as essentially can be understood at the same time. Furthermore, the invention relates to the trench structures all or parts of it. This can e.g. mean that only one initial Forming the trench structures, ie part of the complete trench structures at the same time, so that - are once parts of the trench structures each formed simultaneously and adjusted to each other - then subsequent parts of the independent Trench structures also independent spaced from each other and in time also in different Process sequences can be further structured. Thus, an initial adjustment e.g. through an initial Partial recess, also e.g. in the sense of a mark, realized be what then after the adjustment by forming the Markings in the surface area of the underlying material area in the desired spatial relationship then the further manufacturing process connects.

It is an idea of the invention that the relative position of the two trench structures determined by a photographic technique and structuring of the etching mask or hard mask becomes, so that the adjustment error is eliminated. Then be the two trenches at the same time, partly simultaneously or sequentially with corresponding auxiliary masks etched. In this sense, it is a common process block.

at a preferred embodiment the method for producing a trench structure semiconductor device according to the present Invention, the first trench structure and the second trench structure be formed with different geometries.

at another preferred embodiment the method for producing a trench structure semiconductor device according to the present invention For example, the first trench structure and the second trench structure become alternative or additionally differently formed in terms of a size or a plurality of sizes the group, which consists of a trench width, a trench depth, a trench form and a trenching.

alternative or additionally For example, the first trench structure and the second trench structure will be according to one Another embodiment of the method for producing a trench structure semiconductor device according to the present Invention designed with different functionalities.

Of Further, it is alternatively or additionally in another embodiment the method for producing a trench structure semiconductor device according to the present Invention conceivable that the first trench structure with a or is formed as an active trench.

It is further alternatively or additionally in a further embodiment the method for producing a trench structure semiconductor device according to the present Invention preferred that the first trench structure is formed for one and with an electrode assembly.

In In this case, it may be of particular advantage if the electrode arrangement according to a Development of the method for producing a trench structure semiconductor device according to the present Invention with one or a gate electrode inside the first trench structure is formed.

at another development of the method for producing a Trench structure semiconductor device according to the vorlie invention It may be additional or alternatively be provided that outside the first trench structure Doping be formed.

there it is preferred that the doping regions according to another embodiment the method for producing a trench structure semiconductor device according to the present Invention in the surface area be formed of the semiconductor material region.

there can a source region and a body region are formed as doping regions become.

The second trench structure may in another preferred embodiment the method for producing a trench structure semiconductor device according to the present Invention as with or with a contact trench for or with a contact terminal for the Doping be formed.

The first trench structure or a part thereof and the second trench structure or part of it according to a Another advantageous embodiment of the method for manufacturing a trench structure semiconductor device according to the present invention via a common and simultaneous etching process using a common etch mask on the surface area be formed of the semiconductor material region.

there In particular, it can be advantageously provided that a mask material for the etching mask on the surface area is formed of the semiconductor material region that first recesses for the first trench structure at first positions and second recesses for the second Trench structure at second positions of the structure previously obtained are formed, through which the Oberflächenbe rich of the semiconductor material region exposed locally and so the etching mask is completed, and then that an etchant on the thus obtained Structure applied, below the first and second recesses the etching mask Material of the semiconductor material region removed and thereby the first trench structure or parts thereof and the second trench structure or parts thereof are generated.

Also conceivable is another variant of the inventive method for producing a trench structure semiconductor device, in which a mask material for the etching mask is formed on the surface region of the semiconductor material region, wherein first recesses for the first trench structure at first positions and second recesses for the second trench structure at second positions the previously obtained structure are formed by which the surface region of the semiconductor material region is exposed locally and thus the etching mask is completed, in which then a first protective layer covering the first recess of the etching mask and exposing the second recess of the etching mask and not covering it is formed as first auxiliary masking in which then applies a first etchant to the structure thus obtained, below the second recesses of the etching mask material of the semiconductor material region removed and thereby the two th Trench structure or parts thereof are generated, in which then removes the first protective layer and thereby the first recess of the etching mask is exposed, in which then the second recess of the etching mask and the second trench structure covering and / or filling and the first recess of the etching mask exposed and not covering second protective layer is formed as a second auxiliary mask, in which then applied a second etchant to the structure thus obtained, removed below the first recess of the etching mask material of the semiconductor material region and thereby the first trench structure or parts thereof are produced and at wel chem then the second Protective layer removed and thereby the first trench structure is exposed.

alternative It is also conceivable that different etching depths with respect to the areas below the first and second recesses of the etching mask by selecting the lateral dimensions of the first and second recesses controlled by the etching mask be achieved, with the same process time a larger lateral Expansion of a recess with a larger etching depth below the recess and a smaller lateral extent of a recess with a lower etch depth correspond below the recess.

Further is it alternatively possible that different etching depths with respect to the areas below the first and second recesses the etching mask be controlled by the fact that after expiration of the common Process time span for the application of the etchant the resulting recess for the trainee second trench structure in the semiconductor material area below the second recess of the etching mask, the resulting second trench structure covered by and / or with a protective agent and / or filled and so protected and then for that a second process period on the structure thus obtained, an etchant is applied and thereby below the first recess of the etching mask resulting recess in the semiconductor material region as the first section the first trench structure to be formed around a second section extended and so the first trench structure is completed.

Conceivable is as an application that as a trench structure semiconductor device a DMOS power transistor is formed.

These and further aspects of the present invention will be discussed below further explained: The invention in particular relates to a process for the preparation of optimal adjusted trenches using combined trench etching.

at The development of new generations of DMOS power transistors is an important one Aim to reduce the specific on-resistance Ron · A. In order to on the one hand the static power dissipation can be minimized, On the other hand, higher ones are possible Reach current densities. To achieve this goal is a very good opportunity, to reduce the cell pitch. This means in the specific case at Trench power transistors that the trenches and the intervening lying contact trenches possible should be performed closely spaced from each other. This idea beats a procedure as one as possible dense spacing can be achieved.

So far common Initiate procedures first the active trenches. In the further process sequence the insulation layers become and the electrodes formed in the active trenches are followed from an intermediate oxide deposition. Now the contact trench is between the active trenches are adjusted, with the CD dimensional variations here and the misalignment tolerances are relatively large. As a consequence, that the cell pitch is not in the desired Extent reduced can be. In case of too small spacing of the contact trench or the above adjusted corresponding doping regions for contacting - in particular of body contact - can channel doping and thus the threshold voltage can be influenced. This is through the associated with the misalignment fluctuations problematic. in the further course so the contact trench is etched, with corresponding doping regions and conductive materials filled and ultimately to the entire surface of the cell field contacted sourced metallization.

The Among other things, the present invention provides, inter alia, for in a common photographic technique or in a common process block to generate both the active trenches and the contact trenches.

there sees a preferred variant, the simultaneous etching of the active trenches and contact trenches. By different Trench widths in the hard mask can the two different types of grave in one process step at the same time are generated, because wide trenches tend to be etched deeper compared to very narrow trenches.

A modified process control plans to apply the common hard mask and then with a or two backup masks first the one kind of trenches to produce cover with paint or the like and right after the other kind of trenches manufacture. Here, the simultaneity in terms of temporal Close within a belonging together Process block to understand.

These Method of simultaneously producing two or more fundamentally different ones Trench types with fundamentally different functions in the power transistor have the advantage that the misalignment tolerances compared to State of the art are significantly lower or not available. Of the Profit in the cell pitch is e.g. up to 150 nm with a misalignment of 150 nm. At a typical pitch of approx. 1.5 μm this is up to 10% in Ron · A. Thereby, that the CD dimensional variations of trench and contact trench are no longer independent (a photographic technique → linear Addition of CD dimensional variations), but you lose over the previous method (separate photographic techniques → square Addition of CD dimensional variations) again something of this advantage. At e.g. each 100 nm CD-Maßschwankung and 150 nm misalignment tolerance, however, is the advantage after all still around 66 nm.

One Aspect is that in the proposed process flow trenches with different geometries - possible parameters are width, depth, growth, bulbous appearance etc. - and / or different functions - e.g. active MOS trenches, Contact ditches etc. - in a common process block are made simultaneously.

foregoing and subsequently, instead of the commonly used Specialist photography, field oxide, gate oxide, intermediate oxide and contact hole synonymous synonymous, the usual Abbreviations FT, FOX, GOX, ZWOX and KL respectively.

• (A) Body (Bor) + Source, (vorzugsweise As, da es weniger diffundiert als Phosphor) Implantionen blanket, anschließendes RTP-Ausheilen.
• (B) Gemeinsames Herstellen der aktiven Trenches und der Kontaktgräben mittels Hardmask-FT und Trenchätzung.
• (C) Feldoxidation, beinhaltet Bodydrive, Kontaktgraben dabei möglicherweise zuoxidiert.
• (D) FT FOX/GOX und nasschemische Feldplattenätzung, Kontaktgraben wieder frei von FOX.
• (E) Gateoxidation und Gatepolyabscheidung, FT und anschließender Polyrecess, Kontaktgraben wieder frei von Poly.
• (F) TEOS/ZWOX Abscheidung.
• (G) KL-Maske FT mit reichlichen Toleranzen zur Abdeckung der aktiven Trenches, KL-Oxid-Ätzung, Kontaktgraben wieder frei von Oxid; hierzu kann mit einem anisotropen Ätzverfahren deutlich überätzt werden.
• (H) ganzflächige niederenergetische Bor oder BF₂ Implantation für guten p-Typ-Kontakt im Kontaktgrabenboden, insbesondere dann nur im Boden, wenn Kontaktgraben bauchig geätzt wird, Source an der Kontaktgrabenseitenwand und an der Mesaoberfläche wird nicht umdotiert.
• (I) Metallisierung, FT zur Fertigstellung des Leistungstransistors.

Sequence of the preferred method (eg for an n-channel DMOS; in the case of contact trenching, it is advantageous for the recess etches to be carried out slightly bulbous):

• (A) Body (boron) + source, (preferably As, because it diffuses less than phosphorus) implants blanket, followed by RTP annealing.
• (B) Joint production of active trenches and contact trenches by hardmask FT and trench etching.
• (C) field oxidation involving bodydrive, contact trench may be too oxidized.
• (D) FT FOX / GOX and wet chemical field plate etching, contact trench again free from FOX.
• (E) gate oxidation and gate poly deposition, FT and subsequent polyrecess, contact trench again free of poly.
• (F) TEOS / ZWOX deposition.
• (G) KL mask FT with ample tolerances to cover the active trenches, KL oxide etch, contact trench again free of oxide; This can be significantly over-etched with an anisotropic etching process.
• (H) Full-surface low-energy boron or BF ₂ implantation for good p-type contact in the contact trench bottom, especially only in the ground when contact trench is bulbous etched, source at the contact trench sidewall and at the mesa surface is not re-doped.
• (I) metallization, FT to complete the power transistor.

To (B): Here the common trench etching can also be divided into two steps be split. The first sub-step would be a trench etching until in the desired Contact grave depth. Before the second step, the contact trenches with Photographic technology protected. In the second step, the active trenches are then into the desired Etched depth.

These and further aspects of the present invention will be discussed below with the attached Figures explained, which exemplary embodiments of the invention show:

1 - 6 show in schematic and sectional side view intermediate stages of embodiments of the manufacturing method according to the invention for trench structure semiconductor devices.

7 shows a schematic and sectional side view of a conventionally prepared trench structure semiconductor device.

8th shows a trench structure semiconductor device, which was formed in accordance with a preferred embodiment of the inventive manufacturing process Ausfüh.

following become structurally and / or functionally similar or equivalent Structures or method steps denoted by the same reference numerals. Not in every case of their appearance is a detailed description the structural elements or process steps repeated.

The sequence of 1 to 6 in each case shows in sectional side view and in schematic form intermediate states, which in two different procedures according to preferred embodiments of the inventive method for producing a trench structure semiconductor device 10 can be achieved.

In the in 1 shown intermediate state is first a semiconductor material region 20 with a surface area 20a provided.

In the transition to the in 2 intermediate state shown is then on the surface area 20a a layer of mask material 70 ' with a surface area 70a educated.

In the transition to the in 3 shown intermediate state are then at first and second locations or positions X1 and X2 first and second recesses 71 and 72 with first and second lateral extensions or widths W1 and W2, respectively, in the mask material 70 ' , starting from the surface area 70a of the mask material 70 ' , designed so that thereby parts of the surface 20a in the region of the first and second positions X1 and X2, respectively, or under the first and second recesses 71 respectively. 72 of the mask material 70 ' be exposed.

With respect to the structure thus obtained, an etchant then becomes 90 or etching medium 90 over the surface areas 70a and 20a of the mask material 70 ' or the semiconductor material region 20 applied. The recesses 71 . 72 can be etched simultaneously with the usual methods.

The sequence of 4A and 4B shows a first variant of the method according to the invention for producing a trench structure semiconductor device 10 ,

Accordingly, the sequence of the 5A to 5F A second variant of the method according to the invention for producing a trench structure semiconductor device 10 ,

According to the first described variant of the method according to the invention for producing a trench structure semiconductor device 10 is in transition from the intermediate state of 3 to the intermediate state of 4A the etchant 90 in terms of the recesses 71 and 72 of the mask material area 70 ' and with respect to underlying exposed portions of the surface area 20a of the semiconductor material region 20 applied. From the in 4A shown intermediate state of this first variant of the method according to the invention for producing a trench structure semiconductor device 10 shows that only due to the different chosen widths W1 and W2 for the first and second recesses 71 respectively. 72 in the mask material area 70 ' and, correspondingly, due to the different widths W1 and W2 of the laterally exposed surface portions of the surface portion 20a of the semiconductor material region, the corresponding etching depth D1 or D2 is controlled. This is due to the fact that in a diffusion-limited etching process openings with a lower aspect ratio are more strongly etched. Accordingly, after completion of the etching process, the in 4B shown structure in which by applying the etchant 90 on the structure 3 in the area below the first recess 71 of the mask material 70 ' a first recess 31 with a width W1 and a depth D1 is created, creating the first trench structure 30 is defined. Accordingly arises below the second recess 72 in the mask material 70 ' a second recess 41 having a lateral width W2 and a depth D2, thereby forming the second trench structure 40 is defined. As the first lateral width W1 for the first recess 71 in the mask material 70 ' is greater than the second lateral width W2 for the second recess 72 in the mask material 70 ' - W1> W2 - results for the first trench structure 30 a greater depth D1 of the first trench 31 or first recess 31 for the first trench structure 30 as the second depth D2 for the second recess 41 or for the second ditch 41 for the second trench structure 40 ie D1> D2.

Now to the second variant of the method according to the invention for producing a trench structure semiconductor device 10 ,

In the transition from the in 3 shown intermediate state to the in 5A shown intermediate state is first a first etchant 90 or etching medium 90 on the in 3 shown applied structure, so that over the first and second recesses 71 respectively. 72 of the mask material 70 ' the mask 70 the surface area 20a of the semiconductor material region 20 under the first and second recesses 71 and 72 is attacked and exempted, leaving below the first recesses 71 of the mask material 70 ' the mask 70 a first section 30-1 or a first recess 30-1 for the first trench structure 30 arises and that below the second recess 72 of the mask material 70 ' the mask 70 a recess 41 for the second trench structure 40 arises.

in the Generally, depending on the size of the opening in the etching mask always a difference in the etched Give depth. However, it is not necessary that the depth of the both trench structures after the first etching step is the same. On the other hand can It certainly wanted be that the two trench structures have the same lateral width, then the same depth results by itself.

In the transition to the in 5C shown intermediate state is first the finished second trench structure 40 with her recess 41 or with her ditch 41 in the semiconductor material sector 20 by a means of protection 80 , eg by an appropriate protective layer 80 completely covered but with the recess 30-1 for the first trench structure 30 as the first section 30-1 the trainee first trench structure 30 remains free. It is sufficient to cover the second trench structure, for example with a resist mask, which is produced by a non-critical photographic technique.

In the transition to the in 5D intermediate state then becomes a second etchant 90 ' or etching medium 90 ' for a second period Δt 'to the in 5C Applied structure applied.

Due to the protective mechanism of the protective agent 80 or the protective layer 80 in the recess 41 for the second trench structure 40 becomes the second trench structure 40 through the second etchant 90 ' not attacked, but the first section 30-1 for the first trench structure 30 , starting from the first depth D, after completion of the application of the second etchant 90 ' with the second application time Δt 'around a second section 30-2 in the semiconductor material area 20 and expanded by an additional depth ΔD, as in 5E is shown.

In this way arises according to 5F the recess 31 for the first trench structure 30 as a superposition of the first and second sections 30-1 and 30-2 from the application of a first etchant 90 for a first period Δt and by the subsequent application of a second etchant 90 ' for a second period Δt '.

In a third variant, in the 5G to 5L is shown, the openings in the hard mask for the two trench structures are mutually covered with two auxiliary masks and etched the two trench structures separately. In this way, the two trench etches can be optimized separately. In the third variant, as already described and in the 5G to 5L is sketched, two auxiliary masks used. The advantage over the prior art is the same as in the other two methods, because these auxiliary maskings can be or are non-critical photographic techniques. This means that the adjustment does not matter. The advantage over the first two variants is that the two trench etches can be optimized independently of each other.

First, a mask material 70 ' for the etching mask 70 on the surface area 20a of the semiconductor material region 20 trained, in which case in the mask material 70 ' for the etching mask 70 in this structure first recesses 71 for the first trench structure 30 at first positions X1 and second recesses 72 for the second trench structure 40 be formed at second positions X2, through which the surface area 20a of the semiconductor material region 20 locally exposed in the area X1, X2 and so the etching mask 70 is finished. Then one becomes the first recess 71 the etching mask 70 covering and the second recess 72 the etching mask exposed and not covering first protective layer 80 formed as a first auxiliary masking, as in 5G is shown.

According to 5H then becomes a first etchant 90 applied to the structure thus obtained, below the second recesses 72 the etching mask 70 Material of Halbleiterermaterialbe rich 20 removed and thereby the second trench structure 40 or parts thereof are generated.

Then according to 5I the first protective layer 80 removed and thereby the first recess 71 the etching mask 70 exposed.

Then according to 5J a second recess 72 the etching mask 70 and the second trench structure 40 covering and / or filling and the first recess 71 the etching mask exposed and not covering second protective layer 80 ' is formed as a second Hilfsmaskierung.

Then according to 5K a second etchant 90 ' applied to the structure thus obtained, below the first recess 71 the etching mask 70 Material of the semiconductor material region 20 removed and thereby the first trench structure 30 or parts of it generated.

Then the second protective layer 80 removed and thereby the first trench structure 30 uncovered so that the in 5L shown structure arises.

In the transition to the in 6 The intermediate state shown then becomes the mask material 70 ' removed, leaving the entire surface 20a of the semiconductor material region 20 and the recesses 31 and 41 the first and second trench structures 30 and 40 exposed. On the in 6 The structure shown can then be the usual processes for finalizing the corresponding semiconductor devices 10 followed, for example, by forming corresponding doping regions, connections, passivations or the like. As described in the process sequence, however, body and source regions must be created prior to the second trench etch, otherwise one would implant into the bottom of the second trench.

In the 7 and 8th are a conventionally produced trench structure semiconductor device 10 ' and a trench structure semiconductor device produced according to the invention 10 shown in comparison. The structural elements are the same:
The structure according to the conventional method and the structure according to the method of the invention do not differ, the difference lies in the method, ie in the manner of producing the respective structure. It is essential that - in contrast to the method according to the invention - in the conventional procedure, two photo techniques are necessary, one of which is critical with respect to the adjustment.

In an underlying semiconductor ma terialbereich 20 with a surface area 20a is a first trench structure 30 with first recesses 31 or first ditches 31 intended. Between the first ditches 31 the first trench structure 30 is in each case a second recess 41 as a contact trench for the second trench structure 40 educated. The first and second trenches 31 and 41 each extend, starting from the surface area 20a of the underlying semiconductor material region 20 , perpendicular to the semiconductor material region 20 into it. The first trenches 31 have a larger width W1 and a greater depth D1 than the width W2 of the second trenches 41 or as the depth D2 of the second trenches 41 , Although this preferred variant makes use of this, this is not necessary for the principle of the invention. Nestled in the first trenches 31 the first trench structure 30 is an electrode assembly having a gate electrode formed by respective gate insulating materials in the trench 31 the first trench structure 30 is embedded in isolation.

In this way are the first trenches 31 the first trench structure 30 as so-called active trenches or active trenches 31 educated. Between the trenches 31 and 41 are in the semiconductor material sector 20 from its surface 20a Doping regions are formed, namely in the sense of a source region S and a body region B. The formation of the first and second trench structures 30 and 40 takes place in an epitaxial region EPI as a semiconductor material region 20 , Directly between adjacent first ditches 31 the first trench structure 30 is a second trench structure 40 with a second ditch 41 formed and filled with conductive material P, to realize a connection of the source regions S and the body regions B, thereby forming the second trench structure 40 as a contact trench structure or contact trench can be understood. Below the second trench 41 for the second trench structure 40 and in direct contact with this is the so-called body contact area Bk.

The 7 shows that due to the first and second photo techniques, which independently of each other to form the first trench structure 30 or the second trench structure 40 also have to be applied, also fluctuation ranges or adjustment errors 1 respectively. 2 for the respective photo techniques for the active trench 31 and the contact trench 41 arise, which overlap each other, but also a fluctuation of the so-called critical dimension, ie in terms of structure size, according to the reference numeral 3 come in addition.

This is especially the case and is in 7 shown when the photographic techniques for the two trench structures are each adjusted to a third structure, such as an alignment mark. However, if the second trench structure is adjusted to the first, then the adjustment error occurs only once.

In 8th however, there are relative to the relative location of the first and second trenches 31 respectively. 41 to each other no fluctuations, because they are produced in the context of a common process and thus inherently with solid geometric Bezie hung are formed to each other. The only fluctuation remains the fluctuation range 3 in terms of structure size or critical dimension. This is in 8th shown.

1

adjustment errors of photo technology for the production of

first trench structure 30

2

adjustment errors of photo technology for the production of

second trench structure 40

3, 3 '

fluctuation for the Structure Size / Critical

dimension

10

Trench structure semiconductor device according to the invention

10 '

conventionally manufactured Grave structure semiconductor device

20

Semiconductor material region

20a

surface area

30

first grave structure

30-1

first trench section for the first trench structure 30

30-2

second trench section for the first trench structure 30

31

first Recess, first ditch

40

second grave structure

41

second Recess, second trench

70

etching mask

70 '

Material / material region for the etching mask

70a

surface area

71

first recess

72

Second recess

80

Retardants, Protective material, first protective layer,

first auxiliary masking

80 '

Retardants, Protective material, second protective layer, second auxiliary masking

90

(first) etchant, (first) etching medium

90 '

second etchant, second etching medium

B

Body area

Bk

Body contact area

D1

first depth

D2

second depth

EPI

epitaxial region

G

Gate electrode, gate area

M

source metallization

P

Terminal area, contact area

S

source region

Claims (17)

Method for producing a trench structure semiconductor device ( 10 ), In which in a semiconductor material region ( 20 ) with a surface area ( 20a ) at least one first trench structure ( 30 ) of a first type and outside the first trench structure ( 30 ) at least one second trench structure ( 40 ) of a second type different from the first type, the first trench structure ( 30 ) of the first type or part ( 30-1 ) thereof and the second trench structure ( 40 ) of the second type or a part thereof at the same time, substantially simultaneously and / or temporally adjacent to each other in a common process block. Method according to claim 1, wherein the first trench structure ( 30 ) and the second trench structure ( 40 ) are formed with different geometries. Method according to one of the preceding claims, in which the first trench structure ( 30 ) and the second trench structure ( 40 ) are formed differently with respect to a size or a plurality of sizes from the group, which consists of a trench width, a trench depth, a trench shape and a trench trench. Method according to one of the preceding claims, in which the first trench structure ( 30 ) and the second trench structure ( 40 ) are formed with different functionalities. Method according to one of the preceding claims, in which the first trench structure ( 30 ) with or as an active trench ( 31 ) is formed. Method according to one of the preceding claims, in which the first trench structure ( 30 ) is formed for and with an electrode assembly (G). Method according to Claim 6, in which the electrode arrangement is connected to or from a gate electrode (G) in the interior of the first trench structure ( 30 ) is formed. Method according to one of the preceding claims, wherein outside the first trench structure ( 30 ) Doping regions (S, B) are formed. Method according to Claim 8, in which the doping regions (S, B) are present in the surface region ( 20a ) of the semiconductor material region ( 20 ) be formed. Method according to one of the preceding claims 8 or 9, in which a source region (S) and a body region (B) as doping regions (S, B) are formed. Method according to one of the preceding claims 8 to 10, wherein the second trench structure ( 40 ) as one or a contact trench ( 41 ) is formed for or with a contact terminal (P) for the doping regions (S, B). Method according to one of the preceding claims, in which the first trench structure ( 30 ) or a part ( 30-1 ) thereof and the second trench structure ( 40 ) or a part thereof via a common and simultaneous etching process using a common etching mask ( 70 ) on the surface area ( 20a ) of the semiconductor material region ( 20 ) be formed. Method according to Claim 12, - in which a mask material ( 70 ' ) for the etching mask ( 70 ) on the surface area ( 20a ) of the semiconductor material region ( 20 ) is formed, - in which first recesses ( 71 ) for the first trench structure ( 70 ) at first positions (X1) and second recesses ( 72 ) for the second trench structure ( 40 ) are formed at second positions (X2) of the previously obtained structure through which the surface area (X2) 20a ) of the semiconductor material region ( 20 ) exposed locally and so the etching mask ( 70 ) is completed, and - in which then an etchant ( 90 . 90 ' ) applied to the structure thus obtained, below the first and second recesses ( 71 . 72 ) of the etching mask ( 70 ) Material of the semiconductor material region ( 20 ) and thereby the first trench structure ( 30 ) or parts ( 30-1 ) thereof and the second trench structure ( 40 ) or parts thereof. Method according to claim 13, - in which different etch depths (D1, D2) with respect to the areas below the first and second recesses ( 71 . 72 ) of the etching mask ( 70 ) by selecting the lateral expansions (W1, W2) of the first and second recesses ( 71 . 72 ) of the etching mask ( 70 ), wherein - a larger lateral extent (W1) of a recess ( 71 ) with a larger etching depth (D1) below the recess ( 71 ) and a smaller lateral extent (W2) of a recess ( 72 ) with a smaller etch depth (D2) below the recess ( 72 ) correspond. Method according to claim 13, - in which different etch depths (D1, D2) with respect to the regions below the first and second recesses ( 71 . 72 ) of the etching mask ( 70 ) can be achieved thereby controlled, - that after expiration of the common process time span (Δt) for the application of the etchant ( 90 ) the resulting recess ( 41 ) for the second trench structure to be formed ( 40 ) in the semiconductor material sector ( 20 ) below the second recess ( 72 ) of the etching mask ( 70 ) as the resulting second trench structure ( 40 ) by or with a protective agent ( 80 ) and / or filled and thus protected and - that then for a second process time period (Δt ') on the structure thus obtained, an etchant ( 90 ' ) is applied and thereby the below the first recess ( 71 ) of the etching mask ( 70 ) resulting recess ( 30-1 ) in the semiconductor material sector ( 20 ) as the first section ( 30-1 ) of the first trench structure to be formed ( 30 ) to a second section ( 30-2 ) and thus the first trench structure ( 30 ) is completed. Method according to one of the preceding claims 1 to 11, - in which a mask material ( 70 ' ) for the etching mask ( 70 ) on the surface area ( 20a ) of the semiconductor material region ( 20 ) is formed, - in which first recesses ( 71 ) for the first trench structure ( 70 ) at first positions (X1) and second recesses ( 72 ) for the second trench structure ( 40 ) are formed at second positions (X2) of the previously obtained structure through which the surface area (X2) 20a ) of the semiconductor material region ( 20 ) exposed locally and so the etching mask ( 70 ) is completed, - in which then a first recess ( 71 ) of the etching mask ( 70 ) covering and the second recess ( 72 ) of the etch mask leaving free and not covering first protective layer ( 80 ) is formed as the first auxiliary masking, in which case a first etchant ( 90 ) applied to the structure thus obtained, below the second recesses ( 72 ) of the etching mask ( 70 ) Material of the semiconductor material region ( 20 ) and thereby the second trench structure ( 40 ) or parts thereof are generated, - in which then the first protective layer ( 80 ) and thereby the first recess ( 71 ) of the etching mask ( 70 ) is exposed, - in which then a second recess ( 72 ) of the etching mask ( 70 ) and the second trench structure ( 40 ) covering and / or filling and the first recess ( 71 ) of the etch mask releasing and not covering second protective layer ( 80 ' ) is formed as a second auxiliary masking, in which case a second etchant ( 90 ' ) applied to the structure thus obtained, below the first recess ( 71 ) of the etching mask ( 70 ) Material of the semiconductor material region ( 20 ) and thereby the first trench structure ( 30 ) or parts thereof are generated and - in which then the second protective layer ( 80 ) and thereby the first trench structure ( 30 ) is exposed. Method according to one of the preceding claims, in which as trench structure semiconductor device ( 10 ) a DMOS power transistor is formed.