DE102005015828A1 - Hub for memory module e.g. fully buffered dual-in-line memory module, has controller which ignores memory identification information in response to southbound packet from memory controller when writing packet data during test mode - Google Patents

Abstract

The invention relates to a hub, a memory module, a memory system and associated writing and reading methods. In a test mode, identifying information for a memory module, a memory device, or a memory device may be ignored so that all memory modules, memory devices, or memory devices may be test-written or read. Ignoring the memory identifying information may allow all memory modules, memory devices or memory units to be written to or read simultaneously, thereby reducing test time.

Description

declaration of priority

These Application claims the priority of the Korean patent application Nos. 2004-0043022, filed on Jun. 11, 2004, and No. 2004-0075773, filed September 22, 2004, according to 35 U.S.C. Section 119 (a), the contents of the application herein being fully incorporated by reference become.

BACKGROUND THE INVENTION

1 Figure 12 shows various types of conventional memory modules including "single in-line memory modules (SIMM)" and "dual in-line memory modules (DIMM)". SIMMs have memory chips on one side of the memory module, with DIMMs having memory chips on both sides of the memory module. DIMMs can also be defined as registered DIMMs (R-DIMM) and fully buffered DIMMs (FBDIMM).

In an R-DIMM, signals, with the exception of data signals, are communicated from a memory controller to the memory chips via one or more registers. In a FBDIMM, all signals are transferred from a memory device to the memory chips via a hub or advanced memory buffer (AMB) 1 As shown, FBDIMMs are more advantageous for higher speed and / or higher density applications.

2 shows a conventional FBDIMM containing a hub and a plurality of memory chips. A hub may receive a southbound packet (SB) from a memory controller or an adjacent FBDIMM at the receiver R and transmit the SB packet to an adjacent FBDIMM via a transmitter T. The hub may also be northbound from the opposite direction Receive a packet (NB, "northbound packet") from an adjacent FBDIMM and transmit it to the memory controller or to an adjacent FBDIMM using a receiver R and transmitter T. A hub may provide clock signals (CLK), control signals (CON), and / or address signals (ADDR) for the plurality of memory chips. A hub may exchange data (DATA) forward and backward between the plurality of memory chips.

3 shows a conventional memory system having a host (eg, a memory controller) and a plurality of memory modules. CLK signals, southbound signals (STx, "southbound signals") and northbound signals (NRx, "northbound signals") are in agreement with 2 shown. A conventional memory system, for example the memory system which in 3 may include FBDIMMs.

4 For example, a conventional storage system displays the conventional storage system 3 from a different perspective. The eight (8) memory modules (eg FBDIMMs) of 4 are connected in a chain connection, wherein the plurality of memory modules are connected in series by a chain bus. In such an arrangement, signals from and to the memory controller are communicated to each adjacent memory module in series.

5 shows a conventional storage system in more detail. As in 5 As shown, the host (eg a memory controller) includes a transmitter STx which transmits southbound packets (eg southbound high speed packets) to a first FBDIMM MM1 and a receiver NRx which receives northbound packets from the first FBDIMM MM1. A southbound packet may include FBDIMM select bits, rank select bits, control signals, address signals, and / or data to be written. The northbound packet may include data read from the plurality of FBDIMMs MM1 - MMn. Each of the plurality of FBDIMMs (MM1 - MMn) may include a hub, as in the 2 to 4 shown. In addition to a hub, each of the FBDIMMs (MM1-MMn) of the plurality of FBDIMMs may also include a plurality of memory devices M1-Mn which receive memory information and execute read or write operations in accordance with the memory information.

As in 5 1, a hub may further include a southbound receiver SRx, a southbound transmitter STx, a northbound receiver NRx, a northbound transmitter NTx, and a control circuit. A southbound receiver (STx) receives a southbound packet from a first (or memory device) or adjacent FBDIMM. A southbound transmitter STx transmits the southbound packet to a neighboring FBDIMM (with the exception of the last hub in the chain).

The Control circuit can be a southbound package decode into memory information, such as FBDIMM select bits, Rank selection bits, control signals, address signals and / or data signals can contain. The control signals can For example, include / CS, / RAS, / CAS, and / WE.

The control circuit may store the memory information to a memory interface, a memory register, or a memory interface register, such as the DRAM interface DRAM IF shown in FIG 5 is shown (if the memory chips M1 - Mn are DRAM memory). The memory interface, the memory register, or the memory interface register, for example the DRAM interface DRAM IF, receive the memory information and transmit the memory information to the plurality of memory devices M1 - Mn.

The Control circuit may also read data from a plurality of memory devices M1 - M2 over the Memory interface, the memory register, or the memory interface register encode into the package format.

Of the northbound receivers NRx of each stroke (except the last stroke in the chain) can receive northbound packets from an adjacent FBDIMM and the northbound transmitter NTx can receive the northbound ones Packets to the host (or storage controller) or adjacent ones Submit FBDIMMs.

6A shows an example of a conventional southbound (SB) packet format. As in 5 As shown, the southbound packet is transferred in one direction away from the host. The SB packet may have 10 bits, and each bit may toggle 12 times in one cycle of a memory clock, as in FIG 6A shown. The first 4 switches, represented by "A" in 6A may include a cyclic redundancy check (CRC) and a command (CMD) / address (ADDR) code A CRC code is a signal that can be used to detect an error in the transmitted signals The remaining switches represented by "B" may include data to be written or other commands (CMD).

6B shows an example of a conventional northbound (NB) packet format. As in 5 a northbound packet is transmitted in one direction towards the host. As in 6B can be a northbound package 14 Bits, each switching 12 times in a memory clock cycle. The northbound packet may be in one or more read frames, for example a read frame 1 (RDF1) and read frame 2 (RDF2) shared as in 6B shown.

6C shows an exemplary relationship between a reference clock signal (CLK_REF), a memory clock (CLK_MEM), and a packet transmission. As in the example of 6 As shown, the frequency of CLK_MEM is twice the frequency of CLK_REF, and during a cycle of CLK_MEM there are 12 packet transfers.

6D Figure 11 shows an exemplary FBDIMM southbound instruction decode system having various example instructions that may be used to control a DRAM. As shown, presents 6D Memory information that has been decoded by a southbound packet. As in 6D For example, a southbound packet may include module select bits, command bits, one or more rank select bits, and address information.

As in the example of 6D For example, bits 21-23 may be used to select one FBDIMM from the plurality of FBDIMMs and may be defined as module selection bits. As noted above, conventional memory systems 8th FBDIMMs include. As a result, 3 bits (bits 21-23) are necessary to identify a particular FBDIMM.

As in the example of 6D For example, bits 20-18 may be used to identify the desired CMD command that must be used to control the FBDIMM.

As in the previous example of 6D For example, a single bit (bit 17) can be used to select the rank of the selected FBDIMM. The rank defines on which side of the FBDIMM the desired FBDIMM is.

As in the example of 6D For example, bits 16-0 can be used to identify the bank and the address of the desired memory.

7 FIG. 13 is a timing diagram illustrating the read and write operations of a southbound (SB) packet in a conventional system as described in FIG 5 is shown represents. 7 shows the reference clock CLK_REF, the memory clock CLK_MEM, SB packets, memory modules MM1-MMn, and northbound packets.

In the in 7 2, for a write operation, the reference clock CLK_REF is transmitted from a clock transfer line to the hub. As related to above 6C For example, CLK_MEM may be twice the frequency of the frequency of CLK_REF and may be generated by a phase locked loop (PLL) in the hub.

The Southbound SB packet to be written may be communicated to all FBDIMMs by the southbound transmitters STx and southbound receivers SRx during one cycle of the CLK_MEM. The received write SB packet can be decoded into memory information from every hub. As in 6D As shown, the memory information may include module selection bits that may be decoded by the hub to indicate that a particular memory module (eg, memory module MM 1) has been selected. The memory devices of the memory module MM 1 execute a write operation in accordance with the memory information. All other memory modules MM2-MMn do not execute the write operations because they were not identified by the module selection bits.

As in 7 For a read operation, a read SB packet may also be transmitted to all FBDIMMs during one cycle of the CLK_MEM by the southbound transmitters STx and southbound receivers SRx. The received read SB packet may also be decoded into memory information by each hub. As in 6D The memory information may include module selection bits that may be decoded by the hub to indicate that a particular memory module, such as memory module MM1, has been selected. The storage devices of the storage module MM1 perform a read operation in accordance with the storage information. In particular, read data is transferred from the memory devices of the memory module MM1 to the hub of the memory module MM1. The hub of the memory module MM1 may then encode this read data into northbound packets and transmit the northbound packets to the host or storage device via the northbound transmitters NTx and northbound NRx receivers.

In conventional memory systems, for example, the above in connection or in conjunction with 1 to 7 described, it may be advantageous to be able to recognize whether each memory module MM1 - MMn (eg each FBDIMM) is working properly or not. In the conventional memory systems described above, which include eight (8) FBDIMMs, testing each FBDIMM requires that the system perform eight (8) write operations and eight (8) read operations. In addition, as the memories become more and more dense, they contain more and more FBDIMMs, and therefore more read and write operations are needed.

SUMMARY THE INVENTION

exemplary embodiment in the present invention relate to a hub, a memory module, a storage system and associated Reading and writing.

at exemplary embodiments be while of a test mode memory module, memory device or memory unit identifying Ignore information, so all memory modules, storage devices or Memory units are read or written for test purposes can. Ignoring the memory identifying information allows all memory modules, memory devices or memory units simultaneously read or write, reducing the test time is reduced.

at an exemplary embodiment relates The present invention relates to a hub for a memory module, which a control device to store identification information in a south-facing Packet from a memory controller in a memory test mode to ignore.

at an exemplary embodiment the present invention relates to a hub for a memory module with a Control device for receiving a first output information from Memory units of the memory module and to compare the first Output information with second output information from one reshaped memory module in a test mode and for output a comparison result.

at an exemplary embodiment the present invention relates to a hub, with a receiving and transmitting part for receiving a first data packet from one first receiver over one first receive bus and transfer of the first data packet via a transmission bus, and for receiving a second data packet from a second one Receiver over one second receive bus and transmit the second data packet via a second transmission bus, a first interface part for receiving a test mode and Sending a result of the test mode to and from a memory controller via a third bus, a second interface part for sending memory data from the first data packet and receive data to and from a plurality of storage units, as well as a packet transfer part to the storage information unconditionally to the plurality of storage units by the second Interface part in response to the test mode, and around the second packet with the data output of the plurality of storage units to compare.

at an exemplary embodiment relates the present invention relates to a memory module, the plurality of storage units and a hub, wherein the hub in a test mode memory identification information in response on a south-facing Package ignored by a storage controller and data which with the south-facing Package are connected to each of the plurality of storage units of the memory module writes.

at an exemplary embodiment the present invention is directed to a memory system, which is a memory control device and a plurality of memory modules contains which ones connected to the memory controller by a chain, wherein each of the plurality of memory modules includes a hub, wherein each hub in a test mode memory identification information in response to a southward Package ignored by the storage controller, and data which with the south-facing Package are connected to each of a plurality of storage units the majority of memory modules writes.

at an exemplary embodiment the present invention is directed to a method of writing in directed to a memory system comprising a host and N memory modules (where N is an integer> 1 is), with the following steps: Setting a test mode in the N memory modules, transmit a write packet to the N memory modules, decoding the write packet in memory identification information and memory information in each of the N memory modules, as well as providing the memory information for storage units in each of the N memory modules after the memory identification information be ignored in response to the test mode, writing data, contained in the storage information in the storage units of each of the N memory modules.

at an exemplary embodiment For example, the present invention is directed to a memory module that includes a plurality of storage units and a hub, wherein the hub a first output information from the plurality of storage units the corresponding memory module and a second output information from a plurality of memory units of another memory module receives the first output information with the second output information in a test mode and outputs a comparison result.

at an exemplary embodiment the present invention is directed to a memory system, which is a memory control device and a plurality of memory modules contains, where each having a hub, each hub having output information receives from memory units of the corresponding memory module and the Output information for each of the memory units of the corresponding memory module with output information another of the memory modules in the test mode compares and outputs a comparison result.

at an exemplary embodiment the present invention is directed to a method for reading a Memory system directed, which has a host and a plurality of modules, with the following steps: outputting first Data to a first hub from a first storage unit of the first Memory module in response to a read packet, outputting second Data to a second hub from a second memory unit of the second memory module in response to the read packet, transmitting of the second record to the first hub and comparing the first data with the second data and storing a comparison result in the first stroke.

at an exemplary embodiment the present invention is directed to a method for testing a Memory system directed, which is a memory control device and a plurality of memory modules, wherein the plurality of memory modules are connected to the host by a chain and each of the plural of memory modules contains a module selection code, with the following steps: Setting a test mode in the memory modules, simultaneous Write test data to each memory unit in the memory modules in the test mode in response to a write packet, reading the test data from each memory unit of the plurality of memory modules in response to a read packet, and compare the test data from the same memory module with the test data from an adjacent memory module.

SHORT DESCRIPTION THE DRAWINGS

The The present invention will be explained in more detail with reference to the following a detailed description and the accompanying drawings, which exclusively serve for demonstration purposes and therefore do not limit the invention.

1 shows various types of conventional memory modules including "single in-line memory modules (SIMM)" and "dual in-line memory modules (DIMM)";

2 shows a conventional FBDIMM comprising a hub and a plurality of memory chips;

3 shows a conventional storage system;

4 shows the conventional storage system of 3 from another perspective;

5 shows a conventional memory system in a more detailed representation;

6A shows an example of a conventional southbound (SB) packet format;

6B shows an example of a conventional northbound (NB) packet format;

6C shows an example of a relationship of a reference clock, a memory clock, and a packet transmission;

6D shows an exemplary southbound FBDIMM command decoding system;

7 FIG. 12 is a timing diagram illustrating read and write functions of a southbound (SB) packet in a conventional system as shown in FIG 5 is shown, shows;

8th shows a memory system in accordance with an exemplary embodiment of the present invention;

9 shows a hub in accordance with an exemplary embodiment of the present invention;

10 shows a hub in accordance with an exemplary embodiment of the present invention;

10A FIG. 10 is a timing diagram for writing in a test mode in accordance with an exemplary embodiment of the present invention; FIG.

10B FIG. 12 is a flow chart for writing in a test mode in an exemplary embodiment of the present invention; FIG.

11A FIG. 10 is a timing diagram for reading in a test mode in accordance with an exemplary embodiment of the present invention; FIG.

11B FIG. 10 is a flowchart for reading in a test mode in an exemplary embodiment of the present invention; FIG.

12 shows a hub comparing first own data and second data from an adjacent memory module in an exemplary embodiment of the present invention;

It It should be noted that this Figures are intended to illustrate the essential features of the method and devices of exemplary embodiments of this invention to show such exemplary embodiments thereby be to write. However, these drawings are not to scale and may not be construed Not accurately reproduce features of each illustrated embodiment, and are also not intended to define or limit the range of values or the characteristics of the exemplary embodiments within the Scope of this invention are interpreted.

DETAILED DESCRIPTION EXEMPLARY EMBODIMENTS THE PRESENT INVENTION.

8th shows a memory system in accordance with an exemplary embodiment of the present invention. As in 8th represented, the storage system 100 a storage control device 600 , a clock source 610 , as well as a plurality of memory modules 500 exhibit. Each memory module 500 In addition, a plurality of memories, for example DRAMs 520 and one or more hubs 510 contain.

The memory control device 600 may be a southbound packet containing data, control and / or address information 10 contains, in a downstream direction to a plurality of memory modules 500 submit, and can be a northbound packet of data 14 in a downstream direction on a plurality of memory modules 500 receive. The memory control device 600 can also work with the majority of memory modules 500 communicate via an SMBus. The clock source 610 may be clock signals for the memory controller 600 and / or the majority of the memory modules 500 provide, for example, ECLK1.

In the exemplary embodiment shown in FIG 8th can be shown, the plurality of memory modules 500 consist of fully buffered DIMMs (FBDIMMs).

Moreover, in the exemplary embodiment of FIG 8th the majority of memory modules 500 chain-like (daisy chain fashion) with the memory control device 600 be connected. In the exemplary embodiment illustrated in FIG 8th , the memory system contains eight (8) memory modules 500 (or eight FBDIMMs).

As shown, signals become 10 and 14 between the memory controller 6 and the hubs 510 replaced. In an exemplary embodiment, each of the signals 10 . 14 be a pair of low voltage differential signals.

9 For example, an exemplary embodiment illustrates a hub, such as a hub 510 in accordance with an exemplary embodiment of the present invention. As in 9 shown, every stroke 510 a transmitter / receiver 10, as well as a plurality of transmitters and receivers SRx, STx, NRx, NTx, such as those described above in connection with 2 - 3 and 5 have been described.

Every stroke 510 can also be an interface 20 , a storage interface 30 , as well as a control circuit 40 contain. The control circuit 40 may also include a comparator COM, a packet transfer part (PTP) and a multiplexer (MUX).

The transmitter / receiver 10 can send and / or receive packets. The transmitter / receiver 10 can host packets from a host, for example the host 3 - 5 , a memory control device, for example, the memory control device 8th , or transmit from a neighboring FBDIMM in both directions.

the interface 20 may include a mode register RG1 to set a test mode and an error detection register RG2. the interface 20 can receive system management information from the storage controller and send it to it via the SMBus. In particular, the mode register RG1 may store a test mode signal and transmit the test mode signal to the PTP. The error identifier register RG2 may receive an error flag from the comparator COM and transmit the error flag to the memory controller via the SMBus.

The storage interface 30 may receive storage information having instructions, addresses and data information for writing from the PTP, and may transfer the storage information to the plurality of storage devices 520 to transfer. The storage interface 30 can also read data from the majority of storage devices 520 to the PTP of the control circuit 40 to transfer.

Of the PTP can be the southbound one Decode packages from package format into a storage information format, which module select bits, command bits, one or more rank select bits, Command information and / or address information.

In a normal mode, a PTP can detect if the module select bits indicate the FBDIMM of which the PTP is a part. If the module select bit indicates the FBDIMM of which the PTP is a part, the PTP may issue a command as well as address information to the memory interface 30 send. Otherwise, the PTP can ignore the memory information. When the command is a write operation, write data is also sent to the memory interface 30 transmitted.

In a test mode, the PTP can send commands and address information to the memory interface 30 regardless of whether or not the particular FBDIMM was identified (eg by the module selection bits).

Especially forms the multiplexer MUX, which is between the PTP and the MUX is located, a first path and a second path. In normal mode transmitted the mux passes an NB packet to the NTx the first path in response to a first control signal C1 from the PTP.

In transmitted a test mode the MUX sends an NB packet to the comparator COM via the second path, which is on a first control signal C1 from the PTP responds. The comparator COM has two inputs, where one of these is connected to the NRx and the other one is with connected to the second path of the multiplexer MUX. The comparator is activated by a second control signal C2 from the PTP. An exit of the comparator COM is with the RG2 for storing a result connected to a comparison operation.

10A FIG. 12 shows a timing diagram for writing in a test mode in accordance with an exemplary embodiment of the present invention. FIG. The embodiment of 10A shows a write operation in test mode. At the beginning, during or during a first writing period 1 , the mode register RG1 is set by the SMBus. In test mode, the module select bits, rank select bits, and memory information can be ignored. In a second writing period 2 , transmits a memory control device 600 active SB packets to the first memory module 500 and the first memory module 500 transmits the active self-service packet to an adjacent, downstream storage module 500 , In this way, all memory modules receive 500 the active SB packet in one cycle of the CLK_MEM clock.

In a third writing period 3 the active SB packet is written into memory information in a PTP in each memory module 500 decoded. In a fourth period of writing 4 the memory information is sent to the memory interface 30 in every stroke 510 transmitted. At a fifth writing period 5 lead the storage devices 520 in every memory module 500 the active operation in accordance with the Spei at the same time. At a sixth writing period 6 will write a SB packet to all memory modules 500 from the memory controller 600 transmitted in the same way as the active SB packet.

In particular, the write SB packet in the PTP becomes in each memory module 500 is decoded into memory information containing module select bits, rank select bits, command bits, address bits, and data. The module select bits and rank select bits are ignored in each PTP in each memory module in response to the test mode. The memory information except the module select bits and rank select bits are sent to the memory interface 30 in every stroke 510 transmitted. At a seventh writing period 7 lead all memory modules 500 the write operation.

10B FIG. 10 is a flow chart for writing in a test mode in an exemplary embodiment of the present invention. FIG. In the in 10B It is assumed that an active operation is performed before a write SB packet can be written.

As in step 1000 shown, the mode is set in the mode register, for. B, the mode is set to a test mode. In step 1002 becomes a write SB packet for each memory module 500 provided for writing. In step 1004 The write SB packet is stored in memory information in a hub of each memory module 500 decoded. In step 1006 For example, the module select bits and rank select bits in the memory information are ignored in response to the test mode, and the remaining memory information is applied to each of the memory devices 520 transmitted. In step 1008 becomes the write operation in the storage devices 520 in every memory module 500 executed.

11A FIG. 12 is an exemplary timing diagram for a read operation in a test mode in accordance with an exemplary embodiment of the present invention. FIG. As in the first reading period 1' is shown, the mode register is set by the SMBus. By setting the mode to a test mode, the module select bits and memory information are ignored. In the second reading period 2 ' An active SB packet is provided and all memory modules perform an active operation. In a third reading period 3 ' becomes a read SB packet for reading in the storage devices 520 in the majority of memory modules 500 provided for all memory modules. The read SB packet will be in the PTP in every hub of all memory modules 500 decoded in memory information. Module select bits integrated into the memory information are ignored in test mode. The remaining memory information is sent to the memory interface 30 in every stroke 510 transmitted. The storage devices 520 in all memory modules 500 perform a read operation based on the remaining memory information simultaneously and in a fourth read period 4 ' For example, read data from the storage devices is encoded into packet information from the PTP in each hub 510 were received.

In a fifth reading period 5 ' transmits the last memory module 520 , MMn the packet data to the NRx port of an adjacent upstream memory module 520 , MMn-1. In this way, the packet data from the last memory module 520 , MMn to the memory controller 600 during a clock cycle of the CLK_MEM.

In a sixth reading period 6 ' the hub receives 510 in each of the memory modules 520 , M1-MMn-1, except the last memory module 520 , MMn, the packet data from a downstream memory module 520 , MMn-1. Each comparator COM in each memory module 520 , MMn-1, except the last memory module 520 , MMn, compares the received packet data and packet data from the memory module 520 , MMn-1 itself. In a seventh reading period 7 ' If the result of the comparison indicates that the data is the same, the comparator COM sends a pass signal to the RG2. If the data is not the same, the comparator COM outputs an error flag to the RG2.

In an eighth reading period 8th' the memory controller reads all the RG2s to determine if each memory module 520 , MMn is working properly or not.

11B FIG. 10 is a flowchart for reading in test mode in an exemplary embodiment of the present invention. FIG.

As in step 1100 For example, the mode is set in the mode register, for example, the mode is set to a test mode. In step 1102 becomes a read SB packet for all memory modules 500 made available. In step 1104 The read-SB packet is put into memory information in a hub 510 of each memory module 500 decoded. In step 1106 the module select bits and / or rank select bits in the memory information are ignored and command and address information is sent to each of the memory devices 520 transmitted. In step 1108 becomes the read operation in the storage devices 520 in every memory module 500 executed.

In step 1100 submit a last Spei submodule 500 , MMn NB packet information to an adjacent, upstream memory module 500 , MMn-1. The NB packet becomes the memory controller 600 transferred in one clock cycle of the CLK_MEM. In step 1112 Each comparator compares COM in each stroke 510 of each memory module 520 , MMn-1 except the comparator COM in hub 510 the last memory module 520 , MMn, the received NB packet and a self-generated NB packet. The result of the comparison is stored in the RG2 register. In step 1114 reads the memory controller 600 the RG2 register to see if any memory module 500 , MMn works correctly.

12 shows a comparison of first own data and second data from an adjacent memory module 500 , MMn in a hub, as in 9 shown. 12 is similar to 9 , except that in 9 Package information in the comparator COM are compared, whereas in 12 Memory information to be compared in the comparator COM.

As in 12 shown, every stroke 510 turn a receiver / transmitter 10 and a plurality of transmitters and receivers SRx, STx, NRx, NTx, such as those described above in connection with 2 - 3 . 5 and 9 have been described.

Every stroke 510 can also be an interface 20 , a storage interface 30 and a control circuit 40 contain. The control circuit 40 can also, similar to

9 , a comparator COM, a packet transfer part (PTP) and a multiplexer (MUX).

The transmitter / receiver 10 can send and / or receive packets. The transmitter / receiver 10 can host packets from a host, for example the host 3 - 5 and 9 a memory control device, for example, the memory control device of 8th or transmitted from an adjacent FBDIMM in both directions.

the interface 20 may include a mode register RG1 for setting a test mode and an error detection register RG2. the interface 20 may transmit system management information to and receive from a memory controller via an SMBus. In particular, the mode register RG1 may store a test mode signal and may transmit the test mode signal to the PTP. The error detection register RG2 may receive an error flag from the comparator COM and may transmit the error flag to the memory controller via the SMBus.

The storage interface 30 may receive memory information from the MUX, which includes command, address and data information for writing, and may supply the memory information to the plurality of memory devices 520 to transfer. The storage interface 30 can also read data from the majority of storage devices 520 to the MUX of the control circuit 40 to transfer.

Of the PTP can be the southbound one Decode packages from package format into a storage information format, which module select bits, command bits, one or more rank select bits, Can contain command information and / or address information, and can send packet information in a northbound direction and receive.

In a normal mode, a PTP can detect if the module select bits indicate the FBDIMM of which the PTP is a part. When the module select bit indicates the FBDIMM of which the PTP is a part, the PTP can decode packet information into memory information and command and address information to the memory interface 30 via the MUX. Otherwise, the PTP can ignore the memory information. In addition, when the command is a write operation, write data from the PTP becomes the memory interface 30 transferred via the MUX.

In a test mode, the PTP can send command and address information to the memory interface 30 regardless of whether the particular FBDIMM has been identified (for example, by the module selection bits).

In particular, the multiplexer MUX forms between the PTP and the memory interface 30 is located, a first path and a second path. In normal mode, the MUX transmits an NB packet to the PTP and to the NTx via the first path in response to a first control signal C1 from the PTP.

In transmitted a test mode the MUX sends an NB packet to the comparator COM via the second path, which is on a first control signal C1 from the PTP responds. The comparator COM has two entrances, one with the PTP and the other with the second path of the multiplexer MUX is connected. The comparator will go through second control signal C2 activated by the PTP. An output of the comparator COM is connected to the RG2 to be a result of the comparison operation save.

As in 12 As shown, an NB packet may come from an adjacent downstream storage module 500 MMn be entered in the PTP. The PTP can decode NB packets in memory information. The PTP can store information from an instantaneous store 520 and memory information from other neighboring memories 520 and compare the memory information in the comparator COM.

Although One or more exemplary embodiments of the present invention Invention have been described in connection with FBDIMMs are the Teachings of the present invention suitable for other memory modules, for example, R-DIMMs or SIMMs. In addition, the teachings although one or more exemplary embodiments of the present invention Invention have been described with DRAMs, also suitable for other types of memory.

Although One or more exemplary embodiments of the present invention Invention with reference or in conjunction with a host or of a memory controller are the teachings of the present invention further for other types of controllers suitable. About that in addition, although one or more exemplary embodiments of the present invention Invention in connection with module select bits and / or rank select bits All memory identifying information which has been described Memory modules, storage devices or identify storage units.

For the expert is obvious that others changes and modifications to the exemplary ones described above embodiments can be made without departing from the scope of the invention described herein, and it is intended that the entire material included in the above description is merely descriptive and not restrictive should.

Claims (32)

Hub for a memory module comprising: a controller to store identification information in a south-facing Package from a storage control device in a test mode too to ignore. The hub of claim 1, wherein the southbound packet is for an active one Operation, a write, or a read. Hub according to claim 2, wherein the control device includes: one receiver to receive the southward Package from a hub of an upstream storage module or the memory controller; such as a transmitter to send of the south-facing Packet to a hub of a downstream memory module. Hub according to claim 3, wherein the control device also contains: one Register for storing the test mode; a PTP to receive and decoding the southbound Packet in memory information containing at least the memory identification information; such as a memory unit interface for connection to at least a memory unit, wherein the PTP with the memory information Exception of the storage identification information to the storage unit interface without reference to the memory identification information due the test mode, the storage unit interface sends the storage information to the at least one storage unit. Hub for a memory module comprising: a control device for receiving first output information from memory units of the memory module and comparing the first output information with second output information from a downstream memory module in a test mode and for outputting a comparison result. Hub according to claim 5, wherein the control device includes: one receiver for receiving the second output information from the downstream located memory module; such as a transmitter for sending the first output information or the second output information to an upstream memory module or memory controller. Hub according to claim 6, wherein the control device also contains: one first mode register for storing the test mode; a PTP for converting data of the storage units of the corresponding Memory module in the first output information; a mux for receiving the first output information and output of the first one Output information to a hub of an upstream memory module in a normal mode and output the first output information to a comparator in test mode, a comparator for comparison the first output information with the second output information and outputting a comparison result; such as a second one Register for saving the comparison result. The hub of claim 7, wherein the first output information and the second output information on packets that include read data. The hub of claim 1, wherein the memory identification information contains at least one module selection bit. Hub according to claim 4, wherein the storage information contains a command, addresses and / or data for writing. Hub, comprising: a transmitting and receiving part, for receiving a first packet from a first recipient via a first receive bus and transfer of the first particle over a first send bus, and for receiving a second packet from a second receiver via a second receive bus and transmit of the second package a second send bus; a first interface part, for Receive a test mode and send a result of the test mode to and from a memory controller through a third bus; one second interface part, for sending memory information from the first data packet to a plurality of memory units and for receiving data from the plurality of storage units; such as a packet transfer part, unconditionally to the storage information to the plurality of storage units via the second interface part in response to the test mode, and the second packet with the data output of the plurality of storage units to compare. Memory module, comprising: a plurality of Storage units; such as a hub that is the majority of Memory units is connected, the hub in a test mode Memory identification information in response to a southbound Packet ignored by a storage controller, and data, which with the south-facing Packet in each memory unit of the memory module writes. The memory module of claim 12, wherein the hub comprises: one first receiver for receiving a southward package; a first transmitter for transmitting the southbound packet; one Mode register for storing a test mode; a packet transfer part for decoding the received southbound Package in a memory identification information and memory information and outputting the memory information without reference to the Memory identification in response to the test mode; and a Memory interface for writing the memory information into the Plurality of storage units. The memory module of claim 13, wherein the hub continues includes: one second receiver for receiving a first northbound packet containing first Dates; a second transmitter for transmitting the first northbound package; such as a comparator for comparing the first one northbound packet with a second northbound packet which is output from the plurality of storage units, in response to a read package containing a read command and addresses. The memory module of claim 14, wherein the hub further comprising: one second register for storing a result of the comparator, wherein the comparator is activated in response to the test mode. Storage system comprising: a memory controller; such as a plurality of memory modules, which with the help of Memory control device are connected in a chain, each the memory modules of the plurality of memory modules a hub contains; in which each hub in a test mode memory identification information in response to a southward The package is ignored by the storage controller and data which with the south-facing Packet into each of a plurality of storage devices the majority of memory modules writes. The storage system of claim 16, each hub includes: one first receiver; one first transmitter; a mode register for storing a test mode; one Packet transmission part for decoding the received southbound packet into memory identification information and storage information, as well as for outputting the storage information without reference to the memory identification in response to the test mode; such as a memory interface for writing the storage information into a plurality of storage units. The storage system of claim 17, wherein the hub further comprises: a second receiver for receiving a first northbound packet having first data; a second transmitter for transmitting the first northbound packet; a comparator for comparing the first northbound packet with a second northbound packet output from the plurality of memory units in response to a read packet, which contains a read command as well as addresses. The storage system of claim 18, wherein the hub further having: a second register for storing a comparator result, wherein the comparator is activated in response to the test mode. The storage system of claim 19, wherein the first Register and the second register via a system management bus connected to the host. Method for writing to a storage system which a host and N memory modules (where N is an integer ≥ 1 is), comprising: Setting a test mode in the N-memory modules; To transfer a write packet to the N-memory modules; Decoding the Write packet in memory identification information and memory information in each of the N memory modules; such as Providing the memory information for the Memory units in each of the N memory modules after the memory identification information in response to the Test mode is ignored; Write data representing the storage information contained in the memory units on each of the N memory modules. The method of claim 21, wherein the host and the N memory modules are connected by means of a chain. The method of claim 22, wherein the adjustment of the test mode a system management bus takes place. Memory module, comprising: a plurality of Storage units; such as a hub, where the hub is a first Output information from the plurality of memory units of the corresponding one Memory module and a second output information of the plurality from memory units of another memory module that receives first output information with the second output information in Test mode compares and outputs a comparison result. The memory module of claim 24, wherein the output information is packet information or memory information. The memory module of claim 25, wherein the other Memory module either an adjacent downstream memory module or a last memory module. Storage system, comprising: a memory controller; such as a plurality of memory modules, each comprising one Hub, where each hub output information from storage units of the corresponding memory module receives and the output information for every the memory units of the corresponding memory module with output information from other memory modules in test mode and a comparison result outputs. The memory system of claim 27, wherein the output information either packet information or storage information. The storage system of claim 28, wherein the other Memory module either an adjacent memory module or a last Memory module is. Method for reading a memory system with a Host and a plurality of modules, comprising: Spend first Data to a first hub from a first memory unit on the first memory module in response to a read packet; Output second data to a second hub from a second memory unit on the second memory module in response to the read packet; To transfer the second data to the first hub; such as Compare the first data with the second data and storing a comparison result in the first stroke. The method of claim 30, wherein the second module is adjacent to the first module or a last module in the storage system is. Method for testing a memory system with a Memory control device and a plurality of memory modules, wherein the plurality of memory modules communicate with the host via a Chain is connected, and each of the majority of memory modules contains a module selection code, comprising: Setting a test mode in the plurality of memory modules; simultaneous Writing test data to each of the plurality of storage units memory modules in response to a write packet in test mode; Read the test data from each of the memory units of the plurality of memory modules in response to a reading packet; such as Compare the test data from the own memory module with the test data from a neighboring one Memory module.