DE102005002675B4 - Method for producing a planar spin-on layer on a semiconductor structure - Google Patents

Abstract

method for producing a plane spin-on layer (3) (SOG, SOD) on one Substrate (1) having on its surface a semiconductor structure in particular on a semiconductor wafer, wherein the semiconductor structure pretreated before applying a spin-on layer (3), around a flat surface (6) the spin-on layer (3), wherein in the pretreatment a liner layer (5) is applied to the semiconductor structure having a planar Applying the spin-on layer (3) supported on the semiconductor structure, characterized that as a liner layer (5) after deposition partially reoxidized silicon nitride layer is applied.

Description

The The invention relates to a method for producing a planar spin-on layer on a semiconductor structure according to claim 1.

Semiconductor structures, in particular integrated circuits, are increasing in size due to the decreasing size of the individual devices in the precision required to fabricate the structure. For example, the aspect ratio of trenches in the semiconductor substrate such as STI trenches (STI = trench trench isolation) increases more and more and the width of the trenches more and more. This requires high quality and good filling properties of the materials filled into the trenches, such as dielectrics, to provide the desired electrical properties. During deposition, cavities or seam seams often form in the trenches, which lead to an influence on the electrical properties of the trenches. Corresponding structures such as the trenches are for example filled with HDP (HDP = High Density Plasma) SiO ₂ deposition or a spin-on dielectric such as a silicate glass. The spin-on technique is cost-effective to perform, but in terms of planarity, especially in large-area semiconductor substrates, still disadvantages. As the semiconductor wafers used in the fabrication of semiconductor structures increase in size, there is a need to improve the quality of the spin-on layer in terms of planarity and planarization properties for different feature sizes.

To For example, it is known to spin-on a layer during thermal Heating up with a flat surface to lay be and thus a plane surface to reach. However, this method is relatively expensive.

Out US 6,479,405 B2 For example, a method is known in which a semiconductor structure having structures on its surface is pretreated before applying a spin-on layer. In the pre-treatment, a liner layer is applied to the semiconductor structure, which supports a planar application of a spin-on layer.

Out Japanese Abstract JP 2000 058 646 A, it is also known a planar application of the spin-on layer on a semiconductor structure by to support a liner layer.

From the US patent US Pat. No. 6,437,441 B1 Furthermore, a liner layer is known which consists of silicon oxide. A spin-on layer is applied to the liner layer and improved adhesion of the spin-on layer is achieved.

From the US patent US 6,187,662 B1 It is also known to use silicon oxynitride (SiON) for a liner layer.

Furthermore, from the US patent US 6,417,073 B2 A method is known in which a pad nitride layer is provided on a semiconductor structure, the trenches and in the edge region adjacent to the trenches, a liner layer of silicon oxide being applied in the trenches and on the pad nitride layer, followed by the application of a planar spin on. Layer connects. In this case, an oxide layer is applied to the semiconductor structure before the application of the liner layer.

From the US patent US 5,994,200 It is known to use as the liner layer a silicon oxide layer, a silicon nitride layer, a laminate layer of silicon nitride and silicon oxide, or a silicon oxynitride layer. Furthermore, it is from the US patent US 6,225,171 B1 It is known to provide for a liner layer in a trench of a semiconductor substrate a Si-ON layer whose composition is to be adjusted so that stresses with the substrate are avoided.

From the US patent US 6,669,974 B1 It is known to form a trench for producing a trench capacitor and to deposit a nitride layer in the trench. The nitride layer is reoxidized by a wet oxidation process to improve the quality. The reoxidation reduces the defects in the nitride layer by filling the holes with oxide and thereby improves the electrical property of the nitride layer.

The The object of the invention is a method for a substrate with a semiconductor structure at the surface on the semiconductor structure a spin-on layer with a largely planar surface can be generated.

The The object of the invention is solved by the features of claim 1.

Further advantageous embodiments of the invention are in the dependent claims specified.

An advantage of the described method and apparatus is that, prior to application of the spin-on layer, a liner layer is applied to the semiconductor structure which assists in improving the planarity of the surface of the spin-on layer. As a result, for example, in subsequent processes, chemical-mechanical polishing processes are supported with respect to the achievable planarization quality, and shortened in time.

In the embodiment of the invention is As a liner, a partially reoxidized silicon nitride layer which also contributes to a good surface planarity of the spin-on layer leads.

With the described method becomes different feature sizes a substrate with good planarity leveled.

Quality Results regarding the planarity The spin-on layer will be about a thickness of the liner layer Reached 2.0 nm.

Farther will be good results too the planarity the spin-on layer at a thickness of the liner layer of greater than 5 nm achieved.

In a further embodiment of the described method, the semiconductor structure has trenches, those in the edge area adjacent to the trenches with a pad nitride layer is provided. In this embodiment It has proved to be advantageous, the liner also on the pad nitride layer applied.

The Invention will be explained in more detail with reference to FIGS. Show it:

1 a cross section through a semiconductor structure in the form of a semiconductor wafer;

2 a partial section of the semiconductor structure with a trench;

3 the trench filled with a liner layer and a spin-on layer; and

4 a further embodiment of a partial section of a semiconductor structure with a trench filled with a spin-on layer and a further liner layer.

1 shows a schematic representation of a cross section through a semiconductor structure, which is represented in particular by a semiconductor wafer. In the production of integrated circuits, semiconductor wafers, which consist for example of silicon, are provided with a variety of structures from the surface. The structures represent, for example, deep trenches that are used to insulate areas of the semiconductor structure. However, the method described is independent of the shape of the structure and can be applied to a wide variety of semiconductor structures. During further processing the trenches become 2 of the substrate 1 Depending on the embodiment filled with a variety of materials, such as a dielectric.

To fill the trenches 2 For example, a spin-on technique is employed in which a liquid material, such as a glass or SiLK dielectric, is applied to the surface of the semiconductor structure. The spinon process is a rotational casting process in which the liquid spin-on material is deposited in the center of the wafer and then the spin-on material is evenly distributed over the surface of the wafer via rotation of the wafer about the center axis. The deposited material is distributed with a relatively planar surface on the semiconductor structure. This will create a spin-on layer 3 ( 3 ) on the substrate 1 produced. For the further processing of the semiconductor structure, it is often necessary that the spin-on layer 3 has a precisely planar surface, which could not be achieved with the previous application of the prior art. Thus, chemical-mechanical polishing processes are used to form the surface of the spin-on layer 3 to planarize.

2 shows a partial section of the substrate 1 of the 1 with a ditch 2 in the upper opening area to the side of a pad nitride layer 4 is limited on the substrate 1 is applied. To fill the trench 2 now becomes the surface of the substrate 1 subjected to a pretreatment. This pretreatment becomes a liner layer 5 in the trenches 2 and on the surface of the substrate 1 ie on the pad nitride layer 4 , applied. As a liner layer 5 For example, an oxide layer (SiO ₂ ) or a silicon nitride layer (Si ₃ N ₄ ) is applied. Furthermore, silicon oxynitride (SiON) is suitable as a liner layer. After applying the liner layer 5 the spin-on material is deposited on the substrate 1 applied, with the trenches 2 be filled. Subsequently, a thermal annealing process is carried out, in which the spin-on material is converted, for example, by chemical conversion of the liquid to the solid state. As a spinon material, for example, liquid glass such as polysilazane is used. By applying the liner layer, it is possible to achieve the planarity of a surface 6 the spinon layer 3 to improve. For the formation of the liner layer, thicknesses greater than 2.0 nm have been shown to be advantageous. A good planarity of the surface 6 the spin-on layer is achieved at a liner layer thickness greater than 5 nm.

In a simple embodiment, it is also possible to dispense with the surfaces of the pad nitride layer 4 to be covered with the liner layer. However, experiments have shown that in particular in the inventive use of partially reoxidized after the deposition of silicon nitride as a liner layer covering the surface of the pad nitride layer 4 leads to a further improvement of the planarity of the surface of the semiconductor structure.

4 shows a further embodiment in which the liner layer 5 from a first and a second partial liner layer 7 . 8th is formed. The first and second sub-liner layers are made of materials above for the liner layer 5 of the 3 have been described. Good results are achieved with a second part of a film 8th reached in the ditch 2 on the substrate 1 rests and is formed of silicon oxide. In this embodiment, the first part-liner is 7 preferably formed from silicon oxynitride and is located on the second part of the layer. However, other combinations of materials may also be used for the first and second sub-layers 7 . 8th be used.

In the further processing, the semiconductor structure according to 4 if the planarity of the surface 6 the spinon layer 3 is not sufficient for the desired application, subjected to a planarization process, such as a CMP process.

The described method, in particular with respect to with spin-on material coated semiconductor structures have improved planarity with respect to Center to edge uniformity the deposited on the semiconductor wafer spin-on layer. Consequently the method described offers great potential in the further Magnification of the for the production semiconductor wafers used by integrated circuits.

1

substratum

2

dig

3

Spin-on layer

4

Pad nitride layer

5

liner layer

6

surface

7

First Part liner layer

8th

Second Part liner layer

Claims (5)

Method for producing a plane spin-on layer ( 3 ) (SOG, SOD) on a substrate ( 1 ), which has on its surface a semiconductor structure, in particular on a semiconductor wafer, wherein the semiconductor structure prior to the application of a spin-on layer ( 3 ) is pretreated to a flat surface ( 6 ) of the spin-on layer ( 3 ), wherein in the pretreatment a liner layer ( 5 ) is applied to the semiconductor structure, which is a planar application of the spin-on layer ( 3 ) supported on the semiconductor structure, characterized in that as a liner layer ( 5 ) a partially reoxidized after the deposition of silicon nitride layer is applied. Method according to claim 1, characterized in that the liner layer ( 5 ) has a thickness greater than 2.0 nm. Method according to one of claims 1 or 2, characterized in that the liner layer ( 5 ) has a thickness greater than 5 nm. Method according to one of claims 1 to 3, characterized in that the semiconductor structure trenches ( 2 ), which in the edge region adjacent to the trenches ( 2 ) a pad nitride layer ( 4 ), that the liner layer ( 5 ) into the trenches ( 2 ) and on the pad nitride layer ( 4 ) is applied. Method according to one of claims 1 to 4, characterized in that in front of the liner layer ( 5 ) An oxide layer is applied to the semiconductor structure.