DE102005001590B4 - BOC Package - Google Patents

Abstract

BOC Package with a silicon chip, with its active side on one Chip side is attached to a substrate and with at least one central Series of bond pads is provided, via wire bridges with contacts and interconnects are electrically connected, which are located on and in the substrate and on the chip opposite lying side of the substrate, the ball side, with contact balls are provided, and wherein the wire bridges through a bonding channel extend in the substrate, characterized in that the substrate made a substrate assembly (14) having a substrate core (12), provided on both sides with copper layers / Cu wiring levels (15) is, on each of which symmetrically further construction levels (16, 17, 26, 27) each having a further copper layer / Cu wiring plane (17), wherein the bonding channel (13) is a multi-stage symmetrical Structure such that this on the ball and the chip side each starting from the substrate core (12) in opposite directions with increasing opening cross-section graded, with a maximum of one level per construction level is.

Description

The The invention relates to a BOC package (Board on Chip Package) with a Silicon chip, with its active side on a chip side attached to a substrate and having at least one central Series of bond pads is provided, via wire bridges with contacts and interconnects are electrically connected, which are located on and in the substrate and on the chip opposite lying side of the substrate, the ball side, with contact balls are provided, and wherein the jumper by a on or extend multi-stage slot in the substrate.

It has been shown to be the frequency with which memory products operate at least doubled with each architecture change. For example, the maximum clock frequency of the DDR2 was 400 MHz, the DDR3 800 MHz and the DDR4, the clock frequency at 1.6 GHz and possibly even at 3.2 GHz. Connected with it are significant rising demands to a stable power supply around the signal noise of the power supply (Supply Noise) to keep low.

By the growing number of supply pads (connection contacts for supply voltages) and by the increase in functionality and also by the need to if necessary to transfer to differential signals, grows the number of necessary pads (connectors) to be connected have to.

preferred Package technology (packaging and assembly technology) is behind as before the wirebond-based BOC-BSP technology (board on chip with backside Protection (back protection)), since these are for centrally arranged bond pads on the silicon chip most favorable and cheaper is and no changes of the chip design, e.g. the flip-chip technology.

Indeed In conventional BOC-BSP, only one copper plane can be wire-bonded be contacted, which is basically also for them Four-layer BOC-BSP technology applies. This technology offers in addition to Cu layer for Soldering balls (Solder Balls), wire bonding and their interconnections three more Cu layers for Ground and supply potential and signal connections used can be.

There With this technology, only the highest signal layer is bonded can, must Also, the supply signals only a distance at this level back and through a via (coated with a conductive material Hole) until they reach the level of care with least resistance and inductors guided can be.

These Distance causes an additional supply inductance, which increases the noise on the supply potential. A further restriction BOC-BSP technology lies in the wedge-pad pitch (Bondpadpitch (Distance of the bond contacts to each other) on the substrate side). On reason technological needs (bonding process, substrate structuring) can this pitch in the future not to the required extent be reduced, as required by the shrink roadmap of memory chips.

Part of these disadvantages is due to the US 6 049 129 A eliminates, in which a CSP package for high-frequency IC's is described that on the one hand has a flat profile and on the other hand, small dimensions. In this package, a thin chip having a central bond pad row is bonded via an adhesive layer to a multi-layered substrate provided with a multi-stepped bonding channel. Each of the levels has contact pads which are connected via wire bridges to the bond pads of the central bond pad row. In this case, the lower level, which is closest to the chip, bus lines and the top level have a Cu wiring, which is provided with solder balls.

A similar memory arrangement also goes from the US Pat. No. 6,278,616 B1 shows, in which the chip has a single or multi-row arrangement of central bond pads and also a multi-level substrate is provided, the planes are each connected by a stepped bonding channel via wire bridges with the bond pads.

From the EP 1 460 687 A1 shows a multilayer semiconductor substrate for a package. The partially symmetrical substrate structure is interrupted in each case next to the mounted on this chip. These breaks are technically conditioned to allow wirebonding contacts to be made in the appropriate planes. The production of such a substrate is demanding in terms of manufacturing technology. The bond pads and the wire bridges are arranged peripherally here and extend into windows in the substrate. With such a structure structure BOC modules can not be realized.

Finally, that describes US Pat. No. 6,423,622 B1 a package with a multi-level substrate with improved mechanical strength. The substrate has a substrate core, which is provided on both sides with a respective wiring level, on which further wiring levels are arranged. With such a substrate, an improved mechanical strength is to be achieved.

Of the Invention is now based on the object to provide a BOC package, in which the problem of warpage is substantially eliminated is and with the significantly improved properties in terms of reliability be achieved.

The The object underlying the invention is achieved in that the substrate consists of a substrate structure with a substrate core, which is provided on both sides with copper layers / wiring levels, on each of which symmetrically further construction levels, each with a further copper layer / wiring level, wherein the Bonding channel has a multi-stage symmetrical structure, so, that this on the ball and the chip side starting from the substrate core opposite with increasing opening cross-section graded, with a maximum of one level per construction level is.

In In a first embodiment of the invention, the construction plane is through Pressure or re-etching process structured on the ball side so that the copper layer on the Substrate core (core surface) in later Bonding area (bonding channel) for the wirebonden directly accessible is.

The individual wiring levels are through with metal or a conductive material filled Vias interconnected.

In a particular embodiment of the invention are immediately adjacent Wiring levels through blind vias made with metal or a conductive material filled are interconnected.

In Another embodiment of the invention are internal wiring levels through buried vias made with metal or a conductive material filled are interconnected.

A special continuation the invention is characterized in that one of the inner Wiring levels is extended by galvanization in the bonding channel, so that another wire bonding level is available.

advantages The invention can be seen in that a direct Drahtbondverbindung to the individual supply levels is possible and thus a lower supply inductance associated with less noise on the supply line possible becomes. The costs of the inventive build-up technology are considerably cheaper as laminating two substrate cores (circuit board material). About that In addition, the symmetrical structure significantly reduces the substrate warpage.

With Help the build-up technology, the distance of each copper layers adjusted to each other, so that an impedance control is possible and a predetermined value can be set. Finally reduced the presence of several copper layers the thermal resistance quite considerably, which can be further improved by a suitable distribution of the vias can.

Finally leave In a bond channel based package, wedge pads are used for wire bonding provide different substrate levels.

The Invention will be explained in more detail below using an exemplary embodiment. In the associated Drawings show:

1 a standard BOC package of the prior art;

2 a four-layer BOC package of the prior art;

3 a BOC package with a dual bond channel substrate made according to the symmetrical construction of build-up planes on both sides of the substrate;

4 : a schematic detail of a BOC package after 3 with back protection and potted bond channel;

5 a variant of the BOC package according to the invention with a plurality of build-up planes symmetrically formed on both sides of the substrate and wire bridges from the silicon chip to different planes; and

6 A further variant of the BOC package according to the invention, in which a chip-side inner wiring plane is extended by galvanization into the bonding channel.

In 1 is a standard BOC package 1 (Prior art) with a chip 2 by means of a tap 3 or chip gluing on a circuit board 4 is glued, pictured. This circuit board 4 is with a central bond channel 5 provided by the wire bridges 6 pulled, the bond pads on the chip 2 with contacts 7 on the circuit board 4 connect electrically. The contacts 7 are over a wiring 8th with contact balls 9 (Solder Balls) connected. To protect the chip 2 and the wire bridges 6 are the back of the chip 2 and the bond channel 5 wrapped or sealed with a potting compound. A control of the impedance is not possible here and in addition here is a high signal noise of the supply voltage recorded.

2 shows a 4-layer BOC package (prior art) with similar structure as 1 with the difference that here is a 4-layer PCB 11 is used. Although the impedance can be controlled here, it is not the inductance of the power supply, which is limited by the wire bonds and the Viakonzept.

3 shows a BOC package according to the invention with a substrate 12 with dual or two-stage bonding channel 13 , which is based on the symmetrical structure of substrate constructions 14 on both sides of the substrate 12 has been produced. The construction levels 14 consist of the substrate (core) 12 , on both sides with a copper wiring 15.1 . 15.2 is provided on the one building level 16.1 . 16.2 is formed, each in turn with a Cu wiring 17.1 . 17.2 Is provided. The outer Cu wiring 17.1 . 17.2 is at least partially by a solder mask 18.1 . 18.2 covered.

The attachment of the chip 2 on the substrate structure 14 done by an adhesive 19 (printed or dispensten adhesive, or even a tape). The electrical connection between bonding pads 20 . 21 and the Cu wiring 15.2 respectively. 17.2 done with the help of wire bridges 22 , so that different metallization levels are achieved. The electrical connection between the individual Cu wirings 15.1 and 17.1 respectively. 15.2 and 17.2 and also 17.1 and 17.2 is done by filled with a conductive material vias 23 ,

It is essential that the substrate structure 14 before making the bond channel 13 by punching or other mechanical processing, which allows the production of a BOC package with a multi-level bonding channel structure. Furthermore, a symmetrical substrate structure 14 be realized by adding additional recesses 24 on the chip side of the substrate structure 14 be generated. Such a substrate structure reduces the thermal distortion (Warpage) and can be produced with a very simple method. In this case, the chip-side recesses 24 larger than those on the opposite side of the substrate 14 ,

By changing the thickness of the build-up levels 16.1 . 16.2 can be the impedance between the copper wiring 15.2 . 17.2 and 15.1 . 17.1 adjust or check.

4 shows a schematic detail of a BOC package after 3 with back protection (mold cap) from a potting compound 10 and with the potting compound 10 potted Bondkanal 13 ,

By the substrate structure according to the invention 14 can supply power to multiple levels 15.2 (Feed level A), 15.1 (Feed level B), 17.1 (Feed level C) are distributed and the Cu wiring 17.2 as a signal level. The at the construction level 16.2 located solder balls 25 stand over the vias 23 with different levels in electrical connection.

In 5 is a variant of the BOC package according to the invention with several symmetrical on both sides of the substrate 12 trained construction levels and wire bridges 22 from the silicon chip 2 to different levels. The bond channel 13 Here is graded into different gap widths (shown here are, for example, 3 levels), by adding additional construction levels 26.1 . 26.1 and Cu wirings 27.1 . 27.2 have been added. The other structure corresponds to the structure according to 3 . 4 ,

6 shows a variant of the BOC package according to the invention 3 , Here is a chip-side inner Cu wiring layer 15.1 by galvanization 28 in the bond channel 13 extended. The rest of the construction corresponds 3 including the associated description. This can also be the inner Cu wiring 15.1 directly with wire bridges 22 be contacted.

1

Standard Package

2

chip

3

Tape

4

circuit board

5

Bond channel

6

jumper

7

Contact

8th

wiring

9

Contact ball

10

potting compound

11

4-layer printed circuit board

12

substratum (Core)

13

Bond channel

14

substrate assembly

15.1

Cu wiring

15.2

Cu wiring

16.1

construction level

16.2

construction level

17.1

Cu wiring

17.2

Cu wiring

18.1

solder mask

18.2

solder mask

19

adhesive

20

bonding pad

21

bonding pad

22

jumper

23

Via

24

recess

25

Solder ball (Solder Ball)

26.1

construction level

26.2

construction level

27.1

Cu wiring

27.2

Cu wiring

28

galvanization

Claims (6)

A BOC package having a silicon chip attached to a substrate with its active side on a chip side and provided with at least one central row of bond pads electrically connected via wire bridges to contacts and interconnects located on and in the substrate and on the chip-side of the substrate, the ball side, are provided with contact balls, and wherein the wire bridges extend through a bonding channel in the substrate, characterized in that the substrate of a substrate structure ( 14 ) with a substrate core ( 12 ), which is provided on both sides with copper layers / Cu wiring planes ( 15 ), on each of which symmetrically further construction levels ( 16 . 17 . 26 . 27 ) each having a further copper layer / Cu wiring plane ( 17 ), the bonding channel ( 13 ) has a multi-stage symmetrical structure, such that this on the ball and the chip side respectively from the substrate core ( 12 ) is stepped in opposite directions with increasing opening cross-section, wherein a maximum level is provided per construction level. BOC package according to claim 1, characterized in that the build-up plane is structured by pressure or Rückätzverfahren on the ball side such that the copper layer on the substrate core ( 12 ) in the later bond channel ( 13 ) is directly accessible to the wirebonding. BOC package according to claim 1 of 2, characterized in that the individual wiring levels are filled by vias filled with metal or a conductive material ( 23 ) are interconnected. BOC package according to one of claims 1 to 3, characterized in that immediately adjacent wiring levels by blind vias ( 23 ), which are filled with metal or a conductive material, are interconnected. BOC package according to one of claims 1 to 4, characterized in that inner wiring levels by buried vias ( 23 ), which are filled with metal or a conductive material, are interconnected. BOC package according to one of claims 1 to 5, characterized in that one of the inner wiring levels by galvanization in the bonding channel ( 13 ), so that another wire bonding level is available.