DE102005001484A1 - Switching arrangement for data processing system, has p-channel transistors provided for generation of potential equilibrium condition, in which potential at complementary data output nodes are same - Google Patents

Abstract

The The invention relates to a circuit arrangement for processing a Dual rail signal with complementary Data input node (a, aq) for receiving a dual-rail data signal and complementary Data output node (z, zq) for outputting a dual-rail data signal. The circuit arrangement according to the invention is characterized in that Means (P1, P2, P2q) for generating a potential equalization state are provided, in which the potentials at the complementary data output node (z, zq) are the same and in an intermediate area between a High signal level and a low signal level.

Description

The The invention relates to a circuit arrangement for processing a Dual rail signal with complementary Data input node for receiving a dual-rail data signal and complementary Data output node for outputting a dual-rail data signal.

at The so-called dual-rail circuit technology is about a safety-enhanced structure of circuit arrangements, in particular of data processing devices. Usually are circuits in the so-called "single-rail circuit technology" running Switching networks are microelectronics designed so that every bit the information to be processed physically by exactly one electrical node is shown. Such switching networks are relatively uncertain across from the so-called differential current profile analysis, often at Attempt of unauthorized third party access to classified information is applied. The differential power profile analysis, English referred to as Differential Power Analysis (DPA), is one of the most important Methods of attacking, for example, smart cards for security applications. For a given program or a given algorithm Current profiles of the chip card measured with statistical methods or their over evaluated one or more cycles calculated charge integrals, being - for a variety of Program executions - from the Correlation of systematic data variation and respective charge integral Conclusions on the ones to be protected Information can be pulled.

A Possibility, At least significantly complicating DPA attacks is to Data between subsystems of an integrated circuit so far as possible only encrypted exchange or transfer. A suitable for this Cryptosystem is the so-called one-time-pad encryption. From random sequences won keys become bitwise over an XOR link with to be transferred Linked texts. For decryption In turn, an XOR operation is performed. For the One-time pad cryptosystem, it is important that every key sequence only once to connect and decipher otherwise, statistical methods can be used information about Plain texts are determined.

This "encrypted calculation" in single-rail circuitry However, requires a very high Schaltungs- and thereby area overhead, as well one increased in consequence Energy demand. To avoid the requirement of encryption will used the dual-rail circuit technology. From the above to the differential Power profile analysis said that follows on an integrated Circuit existing circuit components against DPA attacks ideally should be designed to be independent of always provide the same power profile to the data to be processed. For the single-rail implementation However, this is certainly not the case, because the time course the states A charge integral associated with a circuit is a function of those Node or electrical capacitances that are electrically recharged be, thus has a strong dependence on the temporal changes the data to be processed.

at The dual rail circuit technology is in contrast to the conventional one Single-rail circuit technology each bit through two nodes k and kq, wherein a transmitted Bit a valid logical Value if k corresponds to the true logical value b of this bit and kq the negated value bn = not (b).

If So the value b = 1 transferred is to be done, this is done by a "1" in the Knot k. At the same time, however, the value "0" on Transmit node kq, so that a total of both a "1" as also a "0" is transmitted. If the value b = 0 to transmit is, there is a simultaneous transfer of the value "1" at node kq. In both cases will So a "1" and a "0" transferred. Physical equivalence assuming the nodes k and kq is now by means of a differential Power profile analysis no longer recognizable, whether as date a "1" or a "0" transmitted has been.

Known dual rail circuits, which are also referred to as differential logic, however, have some disadvantages. This is the case in particular when additionally a so-called pass-gate logic is used. In this, a circuit input is connected to a circuit output through a switch, implementing logic functions. In the signal flow direction behind the transistor of the full high signal level is not achieved, but the voltage rises only to approximately _a U-VTN, where U is _a voltage of the signal at the circuit input and VTN is the threshold voltage of the transistor used. At the output of the circuitry, therefore, signal refresh is often required to output a logic "1" at the full supply voltage level, and a signal change may result in a contention at the involved nodes, such as a node that was initially high-level This is usually done by one or more series-connected n-channel transistors, but at the same time is a circuit present to pull a node potential for signal refresh to the full supply voltage potential. These transistors work against each other at a signal change, which leads to the flow of cross currents. These cause a significant increase in energy expenditure in the circuit. From a functional point of view is also problematic that it can lead to an uncontrolled switching behavior of transistors, especially when the discharge path has several series-connected transistors. This can lead to switching delays, in the worst case, it comes to a complete malfunction of the circuit.

task The invention is a circuit arrangement for processing specify a dual-rail signal that works to save power and doing a reliable operability ensures.

These The object is achieved by a Circuit arrangement of the type mentioned, which characterized in that means for generating a potential equalization state provided in which the potentials at the complementary data output nodes are the same are and in an intermediate range between a high signal level and a low signal level.

By the approximation of the signal levels, so that these in the mentioned Intermediate area are equal, several effects are achieved. The Potential at the data output node is in an area in also the switching thresholds of the transistors for signal refreshment lie. By a small lowering of the potential at one of the Data output node can cause a tilting of the switching state so that there is no more temptation, the tension on an upper one To draw supply voltage potential. The initially described Contention occurs between a discharge transistor and a voltage refresh transistor no more or only very briefly. Cross currents are avoided in this way so that it comes to an effective energy saving. simultaneously prevents transistors from switching unreliable, so as a result also the functionality the circuit is improved. The intermediate area is at one Supply voltage of 1.5 V, preferably between 0.9 V and 1.1 V. The upper limit is determined by the supply voltage minus the Threshold voltage of the transistors used, for example Determined 0.5V. At a supply voltage of 1.2 V is the Intermediate region preferably between 0.6 V and 0.8 V.

One additional Advantage results from the fact that the switching of the transistors can be done much faster because less cargo is transported must become. This results in a speed advantage in the data processing.

Of the Potential equalization is advantageously carried out by a connection transistor, the between the complementary Data output node is arranged and controlled by a control signal is. With appropriate control of the connection transistor the complementary ones Data output node in the equipotential state of low impedance connected.

to Setting the potential of the complementary data output nodes in the said intermediate region are preferably two cross-coupled P-channel transistors are provided, whose source terminals respectively are connected to a supply voltage terminal, the on an upper supply voltage potential, while drain terminals respectively with one of the complementary Data output nodes are connected, and their gate terminals respectively with the drain connection the other transistor are connected to realize the cross-coupling. On the one hand, this advantageously results in the potential equalization state determines the determination of the potential of the data output nodes in the intermediate area and at the same time in an evaluation phase ensures that a High signal is "refreshed", that is on the full supply voltage potential is drawn.

In an advantageous embodiment of the invention are between the Data input node and the connection transistor further signal processing units such as XOR gates or multiplexer switched. These can also be controlled by dual-rail control signals be controllable. In a cheap execution can optional precharge phases are inserted in the control signals, so that the entire circuit is optional also in a safety mode operating mode can be operated. The precharge phases are temporally merged with the equipotential bonding state, so that outward the same functionality is given, the power consumption of the circuit, however, regardless of the processed data is. If a multiplexer is used, It is advantageous if the control signals used there, ie the selection signals while of the equipotential state have the same signal level. Although this is an invalid control signal, because it would select all data sources, which However, it is irrelevant, because anyway because of the low-resistance connection the data output node at the output an invalid signal is output.

In a power saving mode named Be In contrast, it is not necessary to provide drive mode with precharge phases for the control signals. This is at most necessary if the function of the circuit is determined by. For example, this is the case if instead of a connection transistor, as proposed above in an advantageous embodiment of the invention, a data processing node upstream of the data output node is configured so that in this also a low-resistance connection between the data output node can be made. In this case, it may be necessary to drive this signal processing unit with a precharge signal in order to generate the equipotential state in which the low-impedance connection is necessary for adaptation of the potentials at the complementary data output node.

Further advantageous embodiments of the invention are specified in the subclaims.

The The invention will be explained in more detail with reference to embodiments. It shows:

1 a first, simple embodiment of a circuit arrangement according to the invention,

2 an extended embodiment of a circuit arrangement according to the invention,

3 an expanded, more detailed representation of the circuit arrangement of 2 and

4 a signal diagram with the time course of signals of the circuit of 3 ,

1 shows a circuit arrangement according to the invention, in which the complementary data input nodes a and aq and complementary data output nodes z and zq are provided. The reference symbols for the nodes within the circuit arrangement are also used below for the signals applied to this node. This serves for the clarity of the presentation. The statement "data signal <a, aq>" is therefore called "data signal at the nodes a and aq".

The Data output nodes z and zq are through a connection transistor P1 connectable to each other. This transistor is around a p-channel transistor, which can be controlled by a control signal eqq is. When the control signal eqq is at "0", the transistor P1 is low-ohmic, so that also the nodes z and zq are connected to each other with low resistance are. If the control signal eqq "1", the transistor P1 and the locks Nodes z and zq are separated. Furthermore, transistors P2 and P2q provided their load connections in each case between one of the data output nodes z and zq and one Supply voltage terminal VDD are connected, the upper one Supply voltage potential VDD leads. For both transistors these are also p-channel transistors. The gate terminal of the Transistor P2, which is connected between the data output nodes z and VDD is connected to the drain of the other transistor P2q, simultaneously connected to the second data output node zq is. In contrast, the gate terminal of the transistor P2q is connected to the drain terminal of the transistor P2 and the data output node z. On In this way, a cross-coupling is realized, whose operation is below explained becomes. Between the data input nodes a and aq and the connection transistor P1, two pass-gate transistors are connected to the data input nodes to disconnect from the rest of the circuit. These are around n-channel transistors N3 and N3q, which are controlled by a control signal s.

First, will assumed, the transistors N3 and N3q are controlled low resistance. Due to the voltage drop over the pass-gate transistors N3 and N3q, the potential is the output side actually lower than at the input-side nodes a and aq. The cross-coupled transistors P2 and P2q become the potential however, raised to the supply voltage potential VDD, wherein this of course only for the node with a high signal level applies. This results from the other data input node carries a low signal level. It is for the purpose of explanation assume the data input node a is at high signal level and the node aq is at low signal level. The gate of the transistor P2 is therefore driven with a low signal level, so that the transistor P2 is low impedance. This is the connection between VDD and the data output node z low, resulting in a potential increase at the node z leads. On the other hand, the gate terminal of the transistor P2q becomes one High signal level applied, so that the transistor P2q high impedance and therefore has no influence on the potentials of the data output nodes.

To generate a potential equalization state, the data input nodes a and aq are separated from the data output nodes z and zq by controlling the transistors N3 and N3q in a high-impedance manner. Then, the connection transistor P1 is low-resistance controlled by the signal eqq, so that the data output nodes z and zq are conductively connected to each other in a low-impedance manner. After a transitional phase, therefore, the nodes z and zq will assume the same potential. Through the doors When the node zq of the node aq is approached, the node zq is no longer pulled to the reference potential corresponding to a low signal level. Due to the low-resistance connection via the transistor P1, the potential at node zq increases. As a result, the transistor P2 becomes higher-impedance, so that the potential at node z drops. At the same time, the potential at the node zq continues to rise, since charge equalization takes place between the nodes z and zq via the transistor P1. First, a current can flow through the transistor P2, which results in that the potential at the nodes z and zq does not settle in the middle between the earlier potentials of the nodes z and zq, but reaches a value in the steady state, although is above the mean of the potentials of z and zq, but below the supply voltage potential VDD. Because when the voltage VDD minus the threshold voltage VTP of the transistor P2 is reached, it completely blocks, so that no further current flow from VDD to z can take place. The transistor P2q plays no role in this process because it does not go into the conductive state.

In a subsequent Evaluation phase, the connection between z and zq is separated again, by controlling the connection transistor P1 with high resistance. moreover For example, the transistors N3 and N3q are turned on. It is assumed that which is at the data input node aq continues to low signal level, so transistor P2 becomes conductive again and node z goes high raised the potential VDD.

In in the event that node a is at low signal level, it will the node z is pulled to low signal level, which causes that the transistor P2q becomes conductive and thus the node zq with VDD combines.

The 2 shows an expanded embodiment of a circuit arrangement according to the invention. The arrangement of the transistors P1, P2 and P2q is an arrangement of a first signal processing unit 11 , a multiplexer 13 and a second signal processing unit 12 upstream. By the first signal processing unit 11 a first processing of a data input signal takes place. In the exemplary embodiment shown, this is a combination with a dual-rail signal <k0, k0q>, which is referred to below as a control signal. But you could also see it as a data signal, as well as data to be processed can be used to control. At the outputs of the first signal processing unit 11 an intermediate signal <x0, x0q> is output.

Below is the multiplexer 13 arranged. In addition, further intermediate signals <xr, xrq> and <xl, xlq> are supplied to this. A selection signal s0, sl, sr selects which one at the inputs of the multiplexer 13 adjacent dual-rail data signals at the output is forwarded. As a further intermediate signal <y, yq> thus one of the signals <x0, x0q>, <xr, xrq> or <xl, xlq> is available. The multiplexer 13 is another signal processing unit 12 downstream. This has further inputs for a signal <k1, k1q>, which is linked to the signal <y, yq>. That at the output of the second signal processing unit 12 output signal is now provided to the data output nodes z and zq. Between the outputs of the second signal processing unit 12 and the data output nodes are still the connection transistor P1 and the cross-coupled transistors P2 and P2q provided to generate a potential equalization state as described above and to accomplish a signal refresh.

Like from the 2 It can be seen that many of the signals are dual-rail signals. This applies both to the actual data signals <a, aq>, <xr, xrq>, <xl, xlq> as well as to the control signals / data signals <k0, k0q> and <k1, k1q>. As was explained above, in the case of dual rail signal processing, assuming physical equivalence of two nodes k and kq, it is no longer possible by means of a differential current profile analysis to determine whether a "1" or a "0" has been transmitted as the date. However, this only fully applies if a signal change actually takes place with each transmitted date, ie the information "1" and the information "0" alternate. If several identical data are transmitted consecutively, the vulnerability characteristics of the differential power profile analysis deteriorate.

In circuit arrangements for processing dual-rail signals, the security can be increased by the dual-rail signals are equipped with a so-called precharge phase. The desired invariance of the charge integrals is now achieved by inserting between each two states with valid logic values (b, bn) = (1,0) or (0,1) a so-called precharge state, also called precharge Both k and kq are charged to the same electrical potential, thus assuming logically invalid values (1,1) or (0,0). For the precharge state (1,1), a state sequence could look like this:
(1.1) → (0.1) → (1.1) → (1.0) → (1.1) → (1.0) → (1.1) → (0.1) → .. ,

For any such strings, for each transition (1,1) → (b, bn) exactly one node is reloaded from "1" to "0", and for all (b, bn) → (1,1) exactly one node from "0" to "1", regardless of the logical valid value b in question standing status bits. The same applies to state sequences with the precharge state (0,0) or for intermediate states, which under certain circumstances can not be unambiguously assigned to one of the two logic levels.

from that it follows that the charge integrals corresponding to these state sequences independent of the sequence (b, bn) of the logically valid values are, if necessary is carried that the nodes k and kq have the same electrical capacity. The Current profile of a data path thus implemented depends so not from temporal variations of the data to be processed and is thus resistant to differential current profile analysis.

According to the embodiment 2 For example, an invalid signal state can be generated between two data to be transmitted in that the dual-rail signal assumes the state (0,0) or (1,1). This applies to both the control signals and the data signals. The control signals are from a control unit 14 generates the flexible generation of control signals depending on the intended result. This can be exploited in a development of the invention to operate the circuit arrangement in different operating modes. In a safety mode, all dual-rail signals are generated or processed with precharge. This results in a current profile to the outside that is independent of the type of data to be processed, even with sequential transmission of the same data.

One The disadvantage of operating in safety mode is that relatively much Energy is implemented. It is therefore convenient to power the circuit in a power-saving mode operate if no security critical data to process are. In this power-saving mode, the dual-rail signals without precharge processed. A complete Unloading or complete Recharge a node, although this is due to the values of the transferred Data is not required, can be omitted. Nevertheless, equipotential states, such as as described above, both in the data path and in the Control signal paths are used.

The 3 shows a more detailed representation of the embodiment of 2 , wherein the control unit 14 has been omitted for clarity. Of course, it is available and also for the production of the below and in the 3 set up shown further control signals. From the 3 It can be seen that the first signal processing unit 11 is an XOR gate. This is constructed in a known manner by transistors N1, N1q, N2 and N2q. The second signal processing unit 12 is also an XOR gate composed of transistors N6, N6q, N7 and N7q. The multiplexer 13 is composed of six transistors in pass-gate logic, wherein one of the transistor pairs, namely consisting of the transistors N3 and N3q for the coupling of the data signal <x0, x0q> from the first signal processing unit 11 is provided. The further transistor pairs with the transistors <N4, N4q> and <N5, N5q> are used for coupling data signals from adjacent circuit parts. It is in the circuit after 3 The term "pass-transistor logic" is commonly used synonymously with the term "pass-gate logic." A bit-slice technique refers to a circuit design, such as "bit-slice" -pass transistor logic. in which all the circuit parts for processing a bit are arranged in a "track", wherein the tracks for processing a plurality of bits are arranged parallel to one another The control signals are transversely led to This technique enables a systematic, clear and yet space-saving design of a circuit arrangement. In addition, it is ensured that the same boundary conditions apply to the processing of all bits, which is advantageous in view of the current profile considerations as presented above.

Through the multiplexer 13 Thus, data signals <xr, xrq> and <xl, xlq> of the adjacent bit slices are coupled in, concretely it can be a carry. The multiplexer is controlled by three control signals s0, sl and sr, each of the control signals being responsible for the selection of a data input signal. The adjacent bit slices are supplied with data signals <ar, arq> or <al, alq>. These are XOR-linked with control signals <kr, krq> or <kl, klq>.

The operating behavior of the circuit arrangement of 3 is in the diagram of 4 shown. The time course is divided into five phases Z1 ... Z5. In phases Z1 and Z2, the circuit is operated in the safety mode. As can be seen in the first half of phase Z1, all data and control signals are in a precharge phase. The control signal eqq is at a low signal level, so that the transistor P1 has a low resistance and connects the data output node z and zq in a good manner. Although the data output nodes z and zq are not separated from the input nodes a and aq in the illustrated section of the circuit arrangement, the voltage drop between the potentials is due to the chain of n-channel transistors N1, N3, N6 and N1q, N3q and N6q the inputs a and aq and the outputs z and zq so large that the potential would be at the data output node z and zq without the potential setting by the transistors P2 and P2q below the upper potentials, who determined by the transistors P2 and P2q who the.

In the subsequent evaluation phase within the period Z1 valid on the input side Dual Rail Signals <a, aq>, <ar, arq> and <al, alq>. Also the control signals <k0, k0q>, <kr, kr>, <kl, klq>, sr, s0, sl are valid. Corresponding The circuit logic outputs a signal <z, zq> = <1,0> at the outputs. The potentials at the nodes z and zq are through the transistors P2 and P2q in the manner described above to VDD or reference potential drawn. This is a signal refresh with clean signal levels given. In the period Z2 also finds a data processing in safety mode, as based on the precharge phases in the first half of the period is recognizable. Compared to the period Z1 will be other control signals <kr, krq>, <k1, k1q> and sr, s0, sl are processed.

To At the end of period Z2, the circuit enters the power save mode switched, which shows that at the beginning of the period Z3 not all dual-rail signals a precharge phase is inserted. Only the data signals <ar, arq>, <a, aq> and <al, alq> have a precharge phase. This shows that even in power-saving mode, dual-rail signals are processed with precharge can be. As in the safety mode, equipotential bonding states are set to Output nodes z and zq. In period Z4, the data signals have no precharge phase, but with the control signals <kr, krq>, <k0, k0q> and <kl, klq> a precharge phase is planned. This shows that processing of dual-rail signals without precharge can also be done with control signals, which is a precharge phase exhibit. The generation of the potential equalization state takes place as well as in the period Z3 by the driving of the transistor P1, so that it becomes low impedance.

As can be seen from the waveforms in the period Z5, a potential equalization state can also be generated without using the transistor P1. The control signal eqq for the transistor P1 remains at high signal level, so that the transistor P1 is high-impedance. However, the control signal is <k1, k1q> = <1.1>, whereby the transistors N6 and N6q as well as N7 and N7q are controlled low-ohmic. Via the transistors N6 and N7 or N6q and N7q, a low-resistance connection between the data output nodes z and zq is given so that a potential equalization between the nodes z and zq can be established. If through the control unit 14 it is ensured that via the second signal processing unit 12 a low-resistance connection between the data output nodes z and zq is established, the transistor P1 can be omitted in the circuit arrangement.

Of course, alternative embodiments of circuit arrangements according to the invention are given to those skilled in the art, so that the invention is not limited to the described specific embodiments. In particular, the functions of the signal processing units 11 and 12 freely selectable. As has been shown, the possibility of connecting the nodes z and zq is not limited to a p-channel connection transistor P1. In general, the use of transistors of other types is at the discretion of a person skilled in the art.

11

first Signal processing unit

12

second Signal processing unit

13

multiplexer

14

control unit

N1 ... N22

n-channel transistors

N1q ... N22q

n-channel transistors

P1, P2, P2q

p-channel transistors

s0, Sr, sl

control signals for the multiplexer

<k0, k0q>

control signal

<kr, krq>

control signal

<kl, klq>

control signal

<k1, k1q>

control signal

<a, aq>

data signal

<ar, arq>

data signal

<al, alq>

data signal

<x0, x0q>

intermediate signal

<xr, xrq>

intermediate signal

<xl, xlq>

intermediate signal

<y, yq>

data signal

<z, zq>

data signal

Claims (17)

Circuit arrangement for processing a dual rail signal with - complementary data input node (a, aq) for receiving a dual rail data signal and - complementary data output node (z, zq) for outputting a dual rail data signal, characterized in that means ( P1, P2, P2q, 12, P2, P2q) are provided for generating an equipotential state in which the potentials at the complementary data output nodes (z, zq) are equal and - in an intermediate range between a high signal level and a low signal level lie. Circuit arrangement according to Claim 1, characterized the upper limit of the intermediate region is at least one p-channel transistor threshold voltage (VTP) below an upper supply voltage potential (VDD) lies. Circuit arrangement according to claim 1 or 2, characterized in that the lower limit of the intermediate region is at least one n-channel transistor threshold voltage (VTN) above a lower supply voltage potential (0). Circuit arrangement according to one of claims 1 to 3, characterized in that a connection transistor (P1) is provided is whose load connections each with one of the complementary data output nodes (z, zq) are connected and by a control signal (eqq) controllable is, wherein by the connection transistor (P1) the complementary data output node (z, zq) are connected in low impedance in the equipotential state. Circuit arrangement according to one of claims 1 to 4, characterized in that two cross-coupled p-channel transistors (P2, P2q) are provided, - whose Source terminals each connected to a supply voltage terminal (VDD) are, - whose Drain terminals each with one of the complementary Data output node (z, zq) are connected, and - whose Gate terminals each with the drain terminal of the other transistor (P2q, P2) are connected. Circuit arrangement according to one of claims 1 to 5, characterized in that between the complementary data input nodes (a, aq) and the complementary ones Data output node (z, zq) each have a pass-gate transistor (N3, N3q) is connected to separate the complementary data input nodes (a, aq). Circuit arrangement according to claim 6, characterized in that between the complementary data input nodes (a, q) and the pass-gate transistors (N3, N3q) a first signal processing unit ( 11 ) is connected for processing a signal applied to the data input node (a, aq) dual rail signal. Circuit arrangement according to claim 6 or 7, characterized in that between the pass-gate transistors (N3, N3q) and the complementary data output nodes (z, zq) a second signal processing unit ( 12 ) is switched. Circuit arrangement according to one of Claims 6 to 8, characterized in that the pass-gate transistors (N3, N3q) are part of a multiplexer ( 13 ) are, by the dual-rail signals (<xr, xrq>, <xl, xlq>) of other pairs of complementary data input nodes (ar, arq, al, alq) are coupled. Circuit arrangement according to claim 4 and 5, characterized characterized in that in an evaluation phase of the connection transistor (P1) is controlled high impedance and at a low signal level at a the complementary one Data output node (z, zq) of the other data output node (zq, z) over the with this connected cross-coupled transistor (P2q, P2) with the supply voltage terminal (VDD) at which the upper supply voltage potential is connected, is connected. Circuit arrangement according to claim 7, characterized in that a for driving the first signal processing unit ( 11 ) provided control signal (<k0, k0q>) is a dual-rail signal. Circuit arrangement according to claim 8 or 11, characterized in that a for controlling the second signal processing unit ( 12 ) provided control signal (<k1, k1q>) is a dual-rail signal. Circuit arrangement according to claim 11, characterized in that the circuit arrangement is adapted to be operated in different operating modes, one operating mode is a power saving mode and another operating mode is a safety mode, wherein in the safety mode in the control signal (<k0, k0q>) for Actuation of the first signal processing unit ( 11 ) is provided between two valid dual-rail signal states, a precharge phase in which the dual-rail signal assumes one of the invalid states (<1,1>) or (<0,0>). Circuit arrangement according to claim 12, characterized in that the circuit arrangement is adapted to be operated in different operating modes, one operating mode is a power saving mode and another operating mode is a safety mode, wherein in the safety mode in the control signal (<k1, k1q>) for Actuation of the second signal processing unit ( 12 ) is provided between two valid dual-rail signal states, a precharge phase in which the dual-rail signal assumes one of the invalid states (<1,1>) or (<0,0>). Circuit arrangement according to Claim 9, characterized in that - for driving the multiplexer ( 13 ) a plurality of control signals (s0, sr, sl) are provided and - the circuit arrangement is adapted to be operated in different operating modes, one operating mode is a power saving mode and another operating mode is a safety mode, wherein in the safety mode between the control with valid control signals a control with invalid control signals takes place, all of which have the same signal level. Circuit arrangement according to Claims 13 and 14 and 15, characterized in that the precharge phases in the control signals (<k0, k0q>, <k1, k1q>) for the first and second signal processing unit ( 11 . 12 ) and the invalid control signals (s0, sr, sl) for the multiplexer ( 13 ) temporally overlapping, preferably at the same time. Circuit arrangement according to one of the preceding Claims, characterized in that for generating the control signals (<k0, k01>, <k1, k1q>, s0, sr, sl, eqq) a control unit is provided.