DE102004040505A1 - Semiconductor circuit arrangement and method for its production - Google Patents

Abstract

proposed are a semiconductor circuit arrangement (10) and a method for their manufacture, in which material separation of a first circuit area (30) and a second circuit area (40) a protective material region (50) of poly (para-xylene) is formed is or will be.

Description

The The present invention relates to a semiconductor circuit arrangement and a process for their preparation.

The In particular, the invention also relates to a method of integration organic field effect transistors with other electrical components.

at the advancement of modern semiconductor circuit technologies is increasingly on a combination of circuit areas with different Basic technologies are used. Often it is z. B. desirable, Circuit areas based on common semiconductor materials, such as As silicon or germanium, with circuit areas on the Combining the basis of novel material combinations z. B. with circuit areas based on so-called organic Semiconductor devices.

at such semiconductor circuit arrangements in which different Circuit technologies are combined, and in particular in their production can Problems occur when z. B. the different circuit areas based on very different material combinations accordingly also have to be exposed to different process conditions with respect to adjacent circuit areas with other materials are harmful.

Of the Invention is based on the object, a semiconductor circuit arrangement and to provide a method for their production, in which at the manufacture and / or operation of the reciprocal harmful ones influences under different circuit areas of the semiconductor circuit arrangement can be reduced or prevented.

Is solved the task in a semiconductor circuit arrangement according to the invention with the characterizing Characteristics of the independent Patent claim 1. Furthermore, the object is achieved in a method for Producing a semiconductor circuit arrangement according to the invention with the characterizing Characteristics of the independent Claim 11. Advantageous developments of the semiconductor circuit arrangement according to the invention and the method according to the invention for producing a semiconductor circuit arrangement are respectively Subject of the dependent Dependent claims.

at the semiconductor circuit arrangement according to the invention it is envisaged that a first circuit area and a second Circuit area are formed, that the first circuit area with or from one or more organic semiconductor devices is formed, that a protective material area is formed, that through the protective material area of the first circuit area and the second circuit area spatially and materially from each other are formed separately and that the protective material area or with a parylene or a poly (para-xylene) is formed.

It is thus a core idea of the present invention, that at least one of the circuit areas with or of one or more organic Semiconductor devices is formed and that a spatial and material separation of the circuit areas provided protective material area is formed from or with a parylene.

The Organic semiconductor devices are in particular diodes and / or Field effect transistors based on organic semiconductor materials.

It It is preferred that the first circuit area and / or the second Circuit area on a common substrate or on the basis a common substrate having a surface area are formed.

there is particularly preferred that the first circuit area in Substantially formed directly on the surface region of the substrate is.

alternative or additionally it can be provided that the second circuit area substantially directly on the surface area of the substrate is formed.

at another embodiment it is envisaged that the protective material area as an embedding area for the first circuit area is formed and that through the protective material area the first circuit area is formed embedded.

at another alternative or additional embodiment it is envisaged that the protective material area as an embedding area for the second circuit region is formed and that by the protective material area the second circuit area is formed embedded.

Of the first circuit area and the second circuit area can also stacked on top of each other be formed lying.

Advantageously, as an alternative or additional measure an encapsulation material area may be formed for embedding or Encapsulation of the semiconductor circuit arrangement.

to electrical connection of the first circuit area and the second Circuit area can each other a through contact or a plurality of vias be formed, in particular in the protective material area penetrating Way.

Of the Protective material area can be used as a layer with a thickness of about 100 nm or above be formed, preferably with a thickness of about 200 nm or more and / or up to a strength of about 2 microns or below.

Also according to the invention a method for manufacturing a semiconductor circuit arrangement ready in which a first circuit area and a second Circuit area are formed, in which the first circuit area with or one or more organic semiconductor devices is formed, in which a protective material area formed in which the first circuit area is covered by the protective material area and the second circuit area spatially and materially from each other be formed separately and in which the protective material area made of or with a parylene or a poly (para-xylene) becomes.

Conceivable is also a procedure in which additionally or alternatively the first circuit area and / or the second circuit area on a common substrate or based on a common substrate with a surface area be formed.

there It is also conceivable that the first circuit area substantially directly on the surface area of the substrate is formed.

alternative or additionally it can be provided that the second circuit area substantially directly on the surface area of the substrate is formed.

at another alternative or additional embodiment the method according to the invention it is envisaged that the protective material area as an embedding area for the first circuit area is formed and that by the protective material area the first circuit area is formed embedded.

at another alternative or additional embodiment the method according to the invention it is envisaged that the protective material area as an embedding area for the second circuit area is formed and that through the protective material area the second circuit area is formed embedded.

alternative or additionally can the first circuit area and the second circuit area also stacked on top of each other be formed lying.

It It is also conceivable for an encapsulation material region to be formed becomes the embedding or encapsulation of the semiconductor circuitry.

to electrical connection of the first circuit area and the second Circuit area can each other a via or a plurality of vias be formed, in particular in the protective material area penetrating Way.

Of the Protective material area can be used as a layer with a thickness of about 100 nm or above be formed, preferably with a thickness of about 200 nm or more and / or up to a strength of about 2 microns or below.

It It is conceivable that a protective material area of a parylene in Formed by an evaporation pyrolysis polymerization process or is deposited.

It is also an embodiment of the method in which the substrate is at room temperature is held, especially during forming the protective material area and / or during the Forming the encapsulation material area.

It is also another embodiment of the Provided method in which the formation of the vias by means of photolithography by means of an etching mask, in particular of photoresist, Recesses for the tracer vias in the protective material area be formed and at which then the recesses formed in the protective material area with a conductive via material filled in particular using metals and / or conductive polymers.

These and other aspects of the present invention are further explained below:
In particular, the invention relates to a method for integrating organic field effect transistors with other electrical components.

Potential products based on organic field-effect transistors (OFET) and circuits are both "pure" circuit products te such as "radio frequency identification tags" RF-ID transponder as well as "combination products" in which organic circuits or transistors in combination with other functional elements (diodes, light-emitting diodes, photodiodes, memory cells, etc.) result in a functional unit. The organic transistors usually take over the control and evaluation of the other components, with an integration of the various components with the OFETs to a device is necessary.

Problematic In the integration is often the sensitivity of both the OFETs as well as the other functional elements compared to processing steps (Use of organic solvents, aqueous etching solutions, etc.) of each other's technology, or the general sensitivity of a the functional elements opposite environmental influences (Humidity, atmospheric oxygen, etc.). Here are especially the Sensitivity of organic semiconductor layers (e.g., pentacene, Polythiophene, oligothiophene, Cu-phthalocyanine, etc.) compared to o. effects to call. Likewise, different electrode materials (Al, Ca, Mg, etc.) are sensitive to Contamination.

at the production of combination components must therefore be guaranteed be that integration on the one hand with a technologically justifiable Effort takes place and the functional properties of the individual functions unlimited stay or improve if necessary through the whole process to let.

aim The invention is the description of a method for integration various functional elements with OFETs to combination components, wherein the step according to the invention in the introduction a suitable structurable intermediate layer (insulation layer) exists, which separates the individual functional elements, without affecting their function, but contacting each other allows. This intermediate layer consists of parylene, which has excellent barrier properties across from Water, humidity, organic solvents and gases and deposited by a plasma pyrolysis process.

The Options, to provide organic semiconductor layers with a protective layer, by the semiconductor layers from environmental influences, in particular protected against moisture, ge are limited. The reason for this is the sensitivity of the semiconductor layers across from organic solvents, from which appropriate polymeric protective layers are deposited could as well as the sensitivity of the semiconductor layers to thermal Stress, as in the deposition of high-grade inorganic Gaseous phase protective layers (e.g., silicon oxide, silicon nitride, Alumina) necessarily occurs.

Only a variant for applying a polymeric protective layer on a Organic semiconductors have been described so far. This system was originally developed and is used to organic semiconductor layers to structure, i. Single transistors in integrated circuits isolate each other to leakage currents between the transistors to avoid [1]. This photostructurable polymer formulation is based on the system polyvinyl alcohol / ammonium dichromate (PVA / ADC) and becomes neutral aqueous solution applied. Most organic semiconductors tolerate this aqueous system thanks to their strong hydrophobic character, d. H. the organic ones Transistors remain functional after treatment, in the Contrary to treatment with organic solvents [2]. You watch however, immediately after treatment with this system the same Effects (displacement of the threshold voltage, deterioration of the Sub-threshold rise ("subthreshold swing"), reduction of the On / OFF ratio and enlargement of the Hysteresis of the transistors) as they are under the action of moisture a comparable, untreated substrate over time occur.

The Use of parylene or parylenes as a protective layer in combination with classic semiconductor devices (circuit boards, ICs, etc.) is known, but not in connection with direct integration in components or for Applications in or with OFET devices.

A Method or method for protecting an organic semiconductor layer and for integration into combination components, preserving the original Transistor properties, according to our knowledge is not yet known.

Due to the aforementioned problem of the sensitivity of many organic functional materials and inorganic electrode materials to solvents, etc., the application of a suitable protective layer is difficult. The solvent-free deposition of a polymer layer is possible by means of pyrolysis and polymerization in the gas phase of dipara-xylene to poly (para-xylene) ( 1 - [3]). Poly (para-xylene or parylene) is an excellent barrier material to water, organic solvents and various gases, deposition on the surface of the substrate takes place at room temperature, and the realizable layer thicknesses on the substrate range from about 100 nm to several micrometers, with the desired barrier properties a layer thickness of about 200 nm are given

In principle, four integration schemes are suitable mata for the realization of such combination components, see 2a to 2d In all cases, it must be ensured that the individual functions 30 , A and 40 Although B may be isolated from each other (avoiding interfering interactions) they must still be in electrical contact (ie they must be connected by vias).

For variants according to 2a . 2 B and 2d are the respective individual functions 30 , A and 40 , B stacked on top of each other, taking in the case of 2a and 2 B through an insulation layer 50 and in the case of 2c through the substrate 20 are isolated from each other and each by corresponding vias 70 be interconnected miteinender. In the variants according to 2a and 2 B is a protective layer according to the invention 50 necessary for integration. This structure (stack) represents the technologically most sensible option since processing can be done "position by position" and no masking of subregions of the substrate and, for example, of 30 , A during the processing of 40 , B is necessary. This would be in variant according to 2c necessary. Furthermore, the variants according to the 2a and 2 B the area-optimized arrangements in comparison to variant of 2c represents.

Variant according to 2d does not necessarily require the use of such a protective layer 50 as in the variant according to 2c because the spatial separation of individual functions 30 , A and 40 , B through the arrangement above and below the substrate 20 he follows. A disadvantage of variant according to 2d is the difficult realization of contacting 70 (Definition and filling of contact holes) due to the relative thickness of most substrates (> 10 mm).

A final protective layer 60 for protection against environmental influences (encapsulation) is however in all variants of the 2a - 2d helpful

In 3 a detailed and schematic representation of a result of the method according to the invention is shown. After the production of OFETs as 30 , A, OF on any substrate 20 z. B. according to [4] is the protective layer of the invention 50 from parylene on the substrate surface 20a deposited. This is done a "seal" of the surface 20a against negative-acting contaminants. In addition to the protective effect of the parylene layer, this is at the same time a substrate for the functional elements to be processed thereon 40 , B. Before these can be made, a contacting 70 to a metal layer of the OFET structures by photolithographically defining a via, opening it by an etch process, and filling it with a metal or conductive polymer. Optionally, a final sealing of the combined structural element with the sliding surfaces of the parylene process can take place, in order to protect the overhead functional element, if necessary, from contamination.

A The core idea of the invention is the creation of a method for integration of organic and inorganic devices with organic field effect transistors. The individual components are using parylene as Interlayer disposed, with parylene as a protective layer for the lower Component and insulating substrate for the upper component functions.

The Production of the lower component (OFET) on any one Substrate is z. B. according to the literature [4,5].

Subsequently, will the parylene layer according to the invention (Parylene N, Parylene C, Parylene D) in a corresponding evaporation pyrolysis polymerization plant deposited. Advantageous layer thicknesses of the parylene protective layer are> 200 nm and <2 mm. The Substrate becomes during the deposition of the parylene tempered to room temperature.

The Production of vias in the parylene protective layer takes place by definition of the Viastrukturen by photolithography, subsequent plasma etching of Parylene layer (the photoresist acts as an etching mask) and filling the Vias with conductive Materials (Metals - Evaporation, sputtering; conductive Polymers - PDOT: PSS, PANI). It can fill up the vias before or after removing the photoresist etch mask respectively.

Finally, it will the next Functional element (diode, etc.) processed on the parylene surface. A parylene sealant layer may optionally be as described above Process in layer thicknesses> 200 nm to <10 mm respectively.

These and further aspects of the present invention will be discussed below with the attached Figures explained, which exemplary embodiments of the invention show:

1 is a schematic representation of the so-called parylene process, ie a manufacturing method for parylene.

2a to 2d FIG. 4 are cross-sectional cross-sectional views of various embodiments of semiconductor circuitry according to the invention and of the prior art, respectively.

3 shows a particularly preferred embodiment of a semiconductor circuit arrangement according to the invention.

following become structurally and / or functionally similar or equivalent Structures or method steps denoted by the same reference numerals. Not in every case of their appearance is a detailed description the structural elements or process steps repeated.

1 shows in schematic form a parylene process based on evaporation, pyrolysis and subsequent deposition.

The 2a to 2d are sectional side views showing schematically semiconductor circuit arrangements according to the invention 10 ( 2a and 2 B ) or semiconductor circuit arrangements 10 ' from the prior art ( 2c and 2d ).

All embodiments of the 2a to 2d there is one substrate each 20 with a surface area 20a or a top 20a as well as a bottom 20b based.

Further, a first circuit area 30 , A with or from one or more organic semiconductor devices and a second circuit area 40 , B provided. The second circuit area 40 , B may be the same technology as the first circuit 30 , A is used. It may be at the second circuit area 40 , B underlying technology also act to another technology, such as For example, a conventional silicon or germanium technology. For an electrical contacting of the first circuit area 30 , A with the second circuit area 40 , B is a via 70 or a via 70 from a via material 70 ' intended. Optionally, several such vias 70 be educated.

In the conventional circuit arrangement 10 ' from the prior art according to the 2c are the first circuit area 30 , A and the second circuit area 40 , B on the surface 20a of the common substrate 20 educated. The first circuit area 30 , A and the second circuit area 40 , B are different from each other on the surface area 20a of the substrate 20 laterally spaced, with only the contact between them 70 from the contacting material 70 ' is provided. In this conventional arrangement, the process conditions for one of the circuit areas 30 , A or 40 , B also directly access the spatial area for the other circuit area 40 , B or 30 , A, so that in the arrangement of 2c the mutual influence and in particular the harmful effects, which can occur alternately, are not prevented here.

In the embodiment for a conventional semiconductor circuit arrangement 10 ' according to the 2d is the first circuit area 30 , A on the bottom 20b of the common substrate 20 provided, whereas the second circuit area 40 , B on the top 20a of the common substrate 20 is trained. The via 70 from the contacting material 70 ' measures the thickness of the substrate 20 to the first circuit area 30 , A with the second circuit area 40 , B through the substrate 20 through electrically contact. Although the embodiment provides the conventional semiconductor circuit arrangement 10 ' according to the 2d some protection, because the first circuit area 30 A also material from the second circuit area 40 , B is disconnected. However, in many cases, this material separation is that of the circuit areas 30 , A and 40 , B associated half spaces not sufficient.

The invention thus remedy the embodiments that in the 2a and 2 B are shown. In the embodiment of the 2a is on the substrate 20 on its surface 20a the first circuit area 30 , A formed with or on one or more organic semiconductor devices. The first circuit area 30 , A is in a designated protective material area 50 from a protective material 50 ' with a surface area 50a embedded. The second circuit area 40 , B is directly on the surface area 50a of the protective material area 50 designed so that a spatial and physical separation of the first circuit area 30 , A from the second circuit area 40 , B, where the material separation in the form of the protective material area 50 is formed from or with a parylene. The first circuit area 30 , A and the second circuit area 40 , B are via a via 70 from a contacting material 70 ' contacted with each other electrically, but it does not lead to a direct material contact between the first circuit area 30 , A and the second circuit area 40 B comes.

The embodiment of the 2 B differs from the embodiment for the semiconductor circuit arrangement according to the invention 10 of the 2a exclusively in that at the 2 B the second circuit area 40 , B in the protective material area 50 is embedded from or with a parylene, whereas the first circuit area 30 , A with or from one or more organic semiconductor devices on the surface region 50a of the protective material area 50 is designed and arranged.

The 3 shows in cut pages View in schematic form another embodiment of a semiconductor circuit arrangement according to the invention 10 , Again, there is a substrate 20 with a surface area 20a based. The first circuit area 30 , A is formed here by a single organic field effect transistor OF. This organic field effect transistor OF is located directly on the surface area 20a of the substrate and is provided in the protective material area 50 embedded or embedded with a parylene. The organic field effect transistor OF is formed by a gate electrode G, a gate insulation region GOX, and source and drain regions S and D, respectively. An organic semiconductor material O is provided as the material for the channel region. On the surface area 50a of the protective material area 50 is the second circuit arrangement 40 B, which is indicated here by a top electrode TE, a bottom electrode BE and an active layer A provided therebetween. An electrical contact between the organic field effect transistor OF and the second circuit area 40 B is through the via 70 from the via material 70 ' realized.

Quoted literature

• [1] C.D. Sheraw, L.Zhou, J.R. Huang, D. J. Gundlach, T.N. Jackson, M.G. Kane, I.G. Hill, M.S. Hammond, J. Campi, B.K. Greening, J. Francl, and J. West, "Organic thin-film transistor-driven polymer-dispersed liquid crystal displays on flexible polymeric substrates, "Appl. Phys. Lett., Vol. 80, p. 1088 (2002).
• [2] D.G. Gundlach, T.N. Jackson, D.G. Schlom, and S.F. Nelson "Solvent-induced phase transition in thermally evaporated pentacene films, "Appl. Phys. Lett. p. 3302 (1999).
• [3] http://www.paratronix.com/apps/processus.asp.
• [4] H. Klauk, M. Halik, U. Zschieschang, F. Eder, G. Schmid, and C. Dehm, "Pentacenes organic transistors and ring oscillators on glass and on flexible polymeric substrates, "Appl. Phys. Lett., Vol. 82, p. 4175 (2003).
• [5] M. Halik, H. Klauk, U. Zschieschang, G. Schmidt, W. Radik, W. Weber "Polymer gate dielectrics and conducting polymer contacts for high-performance organic thin film transistor "- Adv. Mater. 14 (2002) 1717-1722.

10

inventive semiconductor circuit arrangement

10 '

conventional Semiconductor circuitry

20

substratum

20a

Surface area, top

20b

bottom

30

first circuit area

30a

surface area

40

second circuit area

40a

surface area

50

Protective material area (especially with or out

one parylene)

50a

surface area

60

encapsulation, seal area

70

via, Via

70 '

contacting material

A

active layer

A

first circuit area

B

second circuit area

BE

bottom electrode

D

drain region

G

gate electrode

GOX

Gate insulating region

0

organic Semiconductor material

OF

organic Field Effect Transistor

S

source region

TE

top electrode

Claims (23)

Semiconductor circuit arrangement, - in which a first circuit area ( 30 ) and a second circuit area ( 40 ) are formed, - in which the first circuit area ( 30 ) is formed with or from one or more organic semiconductor components, - in which a protective material region ( 50 ) is formed, - in which by the protective material area ( 50 ) the first circuit area ( 30 ) and the second circuit area ( 40 ) are spatially and materially separated from each other and - in which the protective material area ( 50 ) is formed from or with parylene or poly (para-xylene). Semiconductor circuit arrangement according to Claim 1, in which the first circuit region ( 30 ) and / or the second circuit area ( 40 ) on a common substrate ( 20 ) or based on a common substrate ( 20 ) with a surface area ( 20a ) are formed. Semiconductor circuit arrangement according to one of the preceding claims, in which the first circuit area ( 30 ) substantially directly on the surface area ( 20a ) of the substrate ( 20 ) is trained. Semiconductor circuit arrangement according to one of the preceding claims, in which the second circuit region ( 40 ) substantially directly on the surface area ( 20a ) of the substrate ( 20 ) is trained. Semiconductor circuit arrangement according to one of the preceding claims, - in which the protective material region ( 50 ) as embedding area for the first circuit area ( 30 ) is formed and - in which by the protective material area ( 50 ) the first circuit area ( 30 ) is formed embedded. Semiconductor circuit arrangement according to one of the preceding claims, - in which the protective material region ( 50 ) as embedding area for the second circuit area ( 40 ) is formed and - in which by the protective material area ( 50 ) the second circuit area ( 40 ) is formed embedded. Semiconductor circuit arrangement according to one of the preceding claims, in which the first circuit area ( 30 ) and the second circuit area ( 40 ) are formed stacked one above the other. Semiconductor circuit arrangement according to one of the preceding claims, in which an encapsulation material region ( 60 ) is designed for embedding or encapsulation of the semiconductor circuit arrangement. Semiconductor circuit arrangement according to one of the preceding claims, in which for the electrical connection of the first circuit area ( 30 ) and the second circuit area ( 40 ) with each other a via ( 70 ) or a plurality of plated-through holes ( 70 ) is or are, in particular in the protective material area ( 50 ) penetrating way. Semiconductor circuit arrangement according to one of the preceding claims, in which the protective material region ( 50 ) is formed as a layer having a thickness of about 100 nm or above, preferably with a thickness of about 200 nm or above and / or up to a thickness of about 2 μm or below. Method for producing a semiconductor circuit arrangement, in which a first circuit area ( 30 ) and a second circuit area ( 40 ), in which the first circuit area ( 30 ) is formed with or from one or more organic semiconductor components, - in which a protective material region ( 50 ) is formed, - in which by the protective material area ( 50 ) the first circuit area ( 30 ) and the second circuit area ( 40 ) are spatially and materially separated from each other and - in which the protective material area ( 50 ) is formed from or with parylene or poly (para-xylene). Method according to Claim 11, in which the first circuit area ( 30 ) and / or the second circuit area ( 40 ) on a common substrate ( 20 ) or based on a common substrate ( 20 ) with a surface area ( 20a ) be formed. Method according to one of the preceding claims 11 or 12, wherein the first circuit area ( 30 ) substantially directly on the surface area ( 20a ) of the substrate ( 20 ) is formed. Method according to one of the preceding claims 11 to 13, wherein the second circuit area ( 40 ) substantially directly on the surface area ( 20a ) of the substrate ( 20 ) is formed. Method according to one of the preceding claims 11 to 14, - in which the protective material area ( 50 ) as embedding area for the first circuit area ( 30 ) is formed and - in which by the protective material area ( 50 ) the first circuit area ( 30 ) is formed embedded. Method according to one of the preceding claims 11 to 15, - in which the protective material area ( 50 ) as embedding area for the second circuit area ( 40 ) is formed and - in which by the protective material area ( 50 ) the second circuit area ( 40 ) is formed embedded. Method according to one of the preceding claims 11 to 16, wherein the first circuit area ( 30 ) and the second circuit area ( 40 ) are formed stacked one above the other. Method according to one of the preceding claims 11 to 17, wherein an encapsulation material area ( 60 ) is formed for embedding or encapsulation of the semiconductor circuit arrangement. Method according to one of the preceding claims 11 to 18, in which for the electrical connection of the first circuit area ( 3O ) and the second circuit area ( 40 ) with each other a via or a plurality of vias ( 70 ) is or will be trained especially in the protective material area ( 50 ) penetrating way. Method according to one of the preceding claims 11 to 19, wherein the protective material area ( 50 ) is formed as a layer having a thickness of about 100 nm or above, preferably with a thickness of about 200 nm or above and / or up to a thickness of about 2 μm or below. Method according to one of the preceding claims 11 to 20, wherein a protective material area ( 50 ) is formed or deposited from parylene in an evaporative pyrolysis polymerization process. Method according to one of the preceding claims 11 to 21, wherein the substrate ( 20 ) is kept at room temperature, in particular during the formation of the protective material area ( 50 ) and / or during the formation of the encapsulating material region ( 60 ). Method according to one of the preceding claims 11 to 22, - in which for the formation of the plated-through holes ( 70 ) by means of photolithography by means of an etching mask, in particular of photoresist, recesses ( 52 ) for the trainees to be formed ( 70 ) in the protective material area ( 50 ) are formed and - in which then the recesses formed ( 52 ) in the protective material area ( 50 ) with a conductive contacting material ( 70 ' ), in particular using metals and / or conductive polymers.