DE102004021228A1 - Process for introduction of a trench into a specific conduction type semiconductor body by etching useful in semiconductor production - Google Patents

Abstract

The invention relates to a method for introducing a trench into a silicon body (1), in which initially at least two p-conductive regions (6) are preferably produced by thermomigration of aluminum, and in which then a limited region (7) of the semiconductor body (1 ) between the at least two regions (6) is subjected to anodic oxidation and then to etching by means of an HF-containing solution.

Description

The The present invention relates to a method for introducing a Trench in a semiconductor body by etching.

generally known is the blocking ability from real pn transitions in Semiconductor bodies across from the so-called volume-blocking capacity plane-parallel pn junctions drastically reduced. This is due to the fact that real pn junctions preferably curved in their peripheral areas are. Such bends in the course of pn transitions clear field strength increases, so that in the range of curvatures a critical field strength, at the blocking ability of the pn junction ends much sooner than a straight course of the pn transition is reached. In other words, the critical field strength becomes as a result of the bends in the course of the pn junction achieved much earlier than in a theoretical course without curvatures the case would be. For this reason, the blocking ability of the Randabschlusses of particular importance.

When concrete example of this be a silicon body considered. This is a pn junction for a device of the so-called 600-V class with a 4 μm deep p-type Tray formed in otherwise n-type silicon body, so is the blocking capability this pn junction less than 25% of the volume barrier capacity. Usual measures to reduce field strength peaks curvatures of otherwise planar pn junctions floating field rings, single or multistage field plates, one example p-type well preceded and weakly doped p-type zones ("JTE", Junction Terminal Extension), a laterally varied doping concentration of the p-doping in the example of p-type Tub or combinations thereof. By taking this measure can increase the blocking capability up to values of about 90% of the volume-blocking capacity can be achieved.

disadvantage at the above measures are to be seen in that elaborate Simulations to determine a suitable course of the pn junction at its edge, ie to determine the correct design of the edge termination, necessary are that continue the manufacturing process for a component by additional necessary steps becomes more complicated, and that finally through the measures, such as in particular, for example, by floating field rings, etc. not insignificant proportions of the total available area of the The semiconductor body, So on the entire chip area, needed become.

Farther It should be noted that especially with bipolar devices or even with MOS transistors, which are subjected to a reverse current, a charge stored in the edge area is detrimental because it is the turn-off losses elevated, without substantially contributing to the passage, and because they become one high recovery current in the edge region of the device and thus too Can cause problems in switching robustness.

ground margins, as used in thyristors and disc diodes have very narrow edges, so that here reduces the proportion of edge termination of the entire chip area is. Such ground edges but are unsuitable for small-scale semiconductor chips for manufacturing reasons.

vertical margins of semiconductor devices trenches or trenches whose depth is about 1/10 of the rated voltage of the device in μm. As an example, assume a device of the 600 V class. For 600V will so a Trenchtiefe of about 55 to 60 microns needed. Such trenches can with usual Plasma process by etching can only be produced with an extremely high cost. Instead of of plasma processes also anisotropic alkaline etching media, such as etching media based on KOH. In these, the etching stops (111) -Kristallebenen, so that a relatively large margin width is needed because of the (100) basic material orientation which is customary with MOS components Angle of 54.74 ° to surface of the silicon material forming the base material is formed. It should be noted that comparably much space also from the usual isotropic etching media needed becomes.

Finally also often deep trenches needed filled with metal become (reference 1).

It The object of the present invention is a method for introducing of a trench in a semiconductor body by etching, with which such a ditch without big Effort can be generated with relatively little space.

• (a) Einbringen von Gebieten des anderen, zum einen Leitungstyp des Halbleiterkörpers entgegengesetzten Leitungstyps in den Halbleiterkörper derart, dass zwischen wenigstens zwei Gebieten des anderen Leitungstyps ein von diesen Gebieten im Wesentlichen begrenzter Bereich des einen Leitungstyps im Halbleiterkörper entsteht,
• (b) Aufoxidieren des begrenzten Bereiches durch Anlegen einer Spannung zwischen dem begrenzten Bereich und den Gebieten des anderen Leitungstyps und
• (c) Ätzen des begrenzten Bereiches.

This object is achieved in a method of the type mentioned in particular by the following steps according to the invention:

• (a) introduction of regions of the other conductivity type of the semiconductor body of the opposite conductivity type into the semiconductor body such that between at least two regions of the other conductivity type a region of the one conductivity type in the semiconductor body substantially delimited by these regions arises,
• (b) oxidizing the confined region by applying a voltage between the confined region and the regions of the other conductive type and
• (c) etching the limited area.

Preferably the one conductivity type is the n-type conductivity and the overoxidation takes place in particular by anodic oxidation. For the etching can in an appropriate manner used an HF-containing solution become.

The inventive method is in a particularly advantageous manner for the production of Kompensationsbauelementen and especially for whose edge termination can be used. There it solves the problem of an anisotropic etching Exploiting the specific manufacturing process for compensating p-type columns in an otherwise n-type region of the semiconductor body. Here are the masks for the compensating p-type columns just to change that that at the edge of a chip, a circulating p-type region at the transition to Scratch frame is created. It should be noted, however, that in the circumferential p-type area adjacent areas compensation essentially maintained between n-charge and p-charge becomes. This circulating p-type region becomes an n-type limited area formed in the scribe frame. By anodic oxidation is then the limited n-type region, ie the area of the scribe frame, oxidized. Then, the oxide in the aufoxidierten area by for example, an HF-containing solution etched but pure semiconductor material of the semiconductor body, such as in particular pure silicon of the silicon chip and in particular electrochemically protected p-conducting columns or an applied passivation layer of the etching solution is not to be attacked.

If, for example, an n ^- -type epitaxial layer in which the p-type columns are introduced and which is located on an n-type substrate is etched, the etching stops upon reaching the substrate. The end point of the etching can also be detected via the current flowing through the electrolyte or the etching medium and its temporal evolution.

In addition to etching the Edge area after anodic oxidation can be used for adjustment the degree of compensation still be required, from the circulating p-type region still a part of the doping by means of an isotropic etching process to remove.

Preferably should the doping concentration in a circulating p-type Area and its width so chosen be that this area at full voltage applied to the semiconductor device voltage largely cleared of free charge carriers. As a compensation structure usually is generated by several epitaxial processes, can by a corresponding Selection of the implantation dose and width of the circulating p-type In the different epitaxial levels also a slight gradient the effective dose or an inhomogeneous dopant concentration be realized in the vertical direction. This can be done the maximum blocking ability increase, and the sensitivity to surface charges can be greatly reduced become.

The method of the invention can also be readily used to pattern a vertical edge MOSFET. In this case, one is too 4 similar structure, but then no compensation areas 5a . 5b . 5c and 5d available. Even with such a MOSFET can by a variation of the p-type doping in the field 6 be provided for an effective suppression of field peaks in the edge area.

The inventive method It is also suitable for particularly deep trenches with steep flanks generate, for what so far the relatively expensive plasma etching is used. In a known method. (Reference 2) for the creation of deep trenches in silicon, lateral variations of the etch depth occur in the trenches produced.

For the generation such deep trenches The electromigration is exploited by the local deep into the Semiconductor body into reaching, highly p-doped layers are generated, which then by means of the anodic oxidation of the interposed limited n-type Area in combination with an etching of the silicon dioxide thus formed with the help of an HF-containing solution be removed.

The regions in which such p-doped layers are to be produced are preferably defined by first depositing a metallization layer of, in particular, aluminum of sufficient thickness, and subsequently this metallization layer in the regions of the semiconductor body where the p-doping with subsequent etching does not take place is to be removed again by means of an aluminum etching process. Instead of aluminum, it is also possible to use another suitable material which effects a p-doping and which provides anisotropic doping via a migration effect. Thereafter, the process of thermomigration is carried out. For this purpose, the semiconductor body, so for example a silicon wafer, preferably by means of an RTA system (RTA = Rapid Thermal Annealing) or by rapid thermal annealing (reference 3) or else by means of irradiation with high-energy part chen, such as high-energy protons, heated, with a defined temperature gradient over the depth of the semiconductor body or over the slice thickness is set. A typical temperature difference over the slice thickness of 300-700 μm, in particular 500-650 μm, is a few ° C, for example 5 to 10 ° C. Now, in order to facilitate the process of thermomigration, the higher temperature is set on the side of the disc opposite the side covered with the structured aluminum layer, since experiments have shown that thermomigration is initiated from the cooler side.

The Depth of the p-doped regions then over the height the temperature gradient, the mean temperature and the time duration, while This temperature treatment is performed control. suitable Values at the above-mentioned slice thickness are for the temperature gradient e.g. 10 ° C / mm, the mean temperature e.g. 1000 ° C and the time from a few seconds to a few minutes, e.g. 2 minutes.

After deep p-doped layers having an electrically active aluminum concentration of about 1 × 10 ¹⁹ cm ^-3 have been produced in this way, the process of trench formation by means of anodic oxidation in combination with an etching with an HF containing solution, whereby the desired deep trench can be generated.

It is possible, by the method according to the invention trenches in semiconductor bodies and in particular silicon wafers with steep, practically vertical Flanks and a depth of 10 to several 100 microns to produce. That's it even possible, the entire semiconductor body, so durchzuätzen the entire silicon wafer.

preferred Applications for the inventive method are semiconductor devices with deeply etched trenches, for example, with Metal filled up become. It can also at least locally or in total etched-through semiconductor wafers are generated, which then as a carrier disk serve and with the actual semiconductor device by means of wafer bonding be connected, with the trenches then filled up with metal become.

alternative can the trenches depending on the desired Usage also with polysilicon, a metal silicide or else an insulator (e.g., glass or imide). This filling can in whole or in part.

following The invention will be explained in more detail with reference to the drawings. Show it:

1 a top view of two adjacent compensation components in a semiconductor wafer,

2 a sectional view of the two Kompensationsbauelemente of 1 in a preparatory stage for a trench etching,

3 one to 3 similar sectional view with the two compensation components during the electrochemical etching,

4 a sectional view through doping regions on the vertical edge in a MOS transistor in compensation technology (CoolMOS transistor) and

5 to 7 Cross-sectional views illustrating the preparation of p-type regions by thermomigration.

1 shows a plan view of a silicon wafer as a semiconductor body 1 in which two adjacent compensation components 2 . 3 are provided, which may be, for example, a MOS transistor or an IGBT (Insulated Gate Bipolar Transistor). For the method according to the invention, it is irrelevant whether a MOS transistor or an IGBT is present. Between the two components 2 . 3 is a scratching frame 4 located in which the construction elements 2 . 3 be separated from each other. This separation is done in the usual way by sawing.

With the components 2 . 3 For example, these are compensation components, so that in the otherwise n-type semiconductor body 1 p-type compensation areas 5 are introduced. The compensation areas 5 are so doped that in the areas of the components 2 . 3 between the compensation areas 5 and the surrounding semiconductor body 1 essentially charge compensation exists.

Simultaneously with the compensation areas 5 be using the same mask with which these compensation areas 5 in the semiconductor body 1 introduced, still p-conductive areas 6 in this semiconductor body 1 on both sides of the scribe frame 4 generates, so that an n-doped limited area 7 arises.

It should be noted at this point that the specified line types can also be reversed in each case. That is, the n-type conductivity can be replaced by the p-type conductivity if the n-type conductivity is provided instead of the p-type conductivity. In the semiconductor body 1 it is preferably a silicon wafer. Instead of However, silicon may also be provided with another suitable semiconductor material, such as silicon carbide, compound semiconductor A _III B _V or the like.

The semiconductor body 1 preferably consists of a semiconductor substrate 8th on which an epitaxial layer 9 is applied. This epitaxial layer 9 is generated in several steps, each by implantation in the usual way, the p-type columns 5 or the p-type region 6 is formed.

Finally, it is still on the surface of the semiconductor body 1 outside the limited area 7 a passivation layer 10 applied, which may for example consist of silicon dioxide or silicon nitride or the like.

This is the in the 1 and 2 shown structure.

According to the invention then between the p-type regions 5 . 6 and the n-type semiconductor body 1 a voltage source applied, wherein the cathode with the semiconductor body 1 is connected while the anode to the individual p-type regions 5 respectively. 6 connected. With the help of the voltage source 11 Anodic oxidation is then carried out, in the area of the Ritzrahmens 7 the semiconductor body 1 is oxidized on. In other words, in the area of the scribe frame 7 finds an oxidation of the semiconductor body 1 instead of.

As in 3 is shown, then followed by an electrochemical etching with, for example, an HF-containing solution. In this electrochemical etching, the semiconductor body 1 below the passivation layer 10 not attacked, so the in 3 structure shown is obtained.

The etching with the HF-containing solution is preferably stopped when the silicon substrate 8th is reached. The end point of the etching can be detected by measuring the time evolution of a current flowing through the etching solution (electrolyte).

For setting the degree of compensation in the two compensation components 2 and 3 It may be necessary for that from the orbiting area 6 that the area 7 limited, still part of the doping is removed with an isotropic etchant.

Preferably, however, the doping concentration should be in the area 6 and whose width should be chosen so that this area 6 in lock mode at full, on the compensation components 2 . 3 Existing voltage is largely cleared of free charge carriers. Since, as already mentioned above, the compensation structure is produced by a plurality of epitaxial processes, it is possible by appropriate choice of the implantation dose and width of the area 6 In the different epitaxial levels, a slight gradient of the effective dose or an inhomogeneous dopant concentration in verti cal direction can be realized, so that a "variation of the vertical doping" or vertical "p" -doped rings arise. This both increases the maximum blocking capability and limits the sensitivity to surface charges in a very effective manner.

4 shows an example of this in a CoolMOS transistor, in the compensation areas 5a . 5b . 5c . 5d are formed in various epitaxial planes indicated by dashed lines, wherein the effective doping dose (local integral of the doping dose in the lateral direction) with increasing depth in a circumferential region on the silicon substrate 8th decrease or remain approximately constant.

In 4 are still a p-conductive body area 12 , n ⁺ -type source zones 13 , Gate electrodes 14 made of, for example, polycrystalline silicon, a field plate 15 , which may also consist of polycrystalline silicon, and a metallization 16 made of aluminum, for example.

Out 4 is also seen as the originally limited n-type region 7 (in 4 are on the right side the areas 6 omitted) after anodic oxidation (cf. 2 and 3 ) and etching with the HF-containing solution with insulating material, such as a silicon dioxide layer 17 , is filled.

A further exemplary embodiment of a variant of the method according to the invention is described below with reference to FIG 5 to 7 explained in more detail. The components of the 5 to 7 can also be prepared either on Epi base material or even on homogeneous float zone substrate material.

5 shows an n-type silicon body 1 on which a metallization 18 made of aluminum is applied and structured. This is the metallization 18 designed so that it remains only in places where p-type areas 6 should be generated. This structuring of the metallization 18 takes place in the usual way by means of a metal etching process.

This is followed by a temperature step, through which, as in 6 is shown by thermomigration the p ⁺ -type regions 6 in the silicon body 1 be generated. For this thermomigra tion becomes a temperature difference of several ° C between the top of the semiconductor body 1 on the metallization 18 is applied, and set the opposite back. This temperature difference can be for example 5 to 10 ° C. Depending on the slice thickness of the semiconductor body 1 But other temperature differences are possible. To promote thermomigration, it is ensured that the temperature on the back of the semiconductor body 1 is higher than on the front.

After completion of the thermomigration, residual aluminum may still remain 19 at the bottom of the p-type regions 6 back.

The heating of the semiconductor body 1 for setting the temperature difference can, as already mentioned above, be made by RTA or else by irradiation with high-energy particles.

The penetration depth of the p ⁺ -type regions 6 in the semiconductor body 1 can be easily adjusted by the size of the temperature gradient, the average temperature and the time during which the temperature step is performed. A typical value for the doping concentration achieved in the p ⁺ regions 6 is about 1 × 10 ¹⁹ carriers cm ^-3 . Of course, other values are possible, which may be higher or lower.

After the temperature step still becomes a masking layer 20 on the front side of the semiconductor body 1 applied. This masking layer 20 is intended for subsequent anodic oxidation and etching with an HF-containing solution. It therefore only needs the n-type silicon body 1 outside the p ⁺ -type regions 6 protect against anodic oxidation and RF etching, through which the p ⁺ -type regions 6 not to be attacked. Therefore, it is sufficient if the masking layer 20 is so accurate that it is on the surface of the p ⁺ -type regions 6 ends.

This is followed by anodic oxidation and etching with the HF-containing solution to the limited area 7 between the p ⁺ -conducting areas 6 in the already using the 1 to 3 to remove explained way.

Should the limited area 7 p-conducting, so are the areas 6 n-type. For the metallization 18 For example, aluminum is used. After oxidation of the area 7 The oxide thus formed is subsequently etched using HF or hydrofluoric acid-containing solutions.

1

Semiconductor body

2

first Semiconductor device

3

second Semiconductor device

4

kerf

5

compensation columns

5a, 5b, 5c, 5d

compensation columns

6

P-type areas

7

limited Area

8th

silicon substrate

9

epitaxial layer

10

passivation

11

voltage source

12

Body zone

13

source zone

14

gate electrode

15

field plate

16

metallization

17

silicon dioxide

18

aluminum layer

19

balance aluminum

20

masking layer

Claims (16)

Method for introducing a trench into a semiconductor body ( 1 ) of the one conductivity type by etching, comprising the following steps: (a) introduction of regions ( 6 ) of the other, of a conductivity type opposite conductivity type in the semiconductor body ( 1 ) such that between at least two areas ( 6 ) of the other conductivity type is a substantially limited region ( 7 ) of the one conductivity type in the semiconductor body ( 1 ), (b) oxidizing the limited region ( 7 ) by applying a voltage between the limited region ( 7 ) and the areas ( 6 ) of the other conductivity type and (c) etching of the limited region ( 7 ), so that the trench arises. Method according to claim 1, characterized in that that the one conductivity type is the n-type conductivity and that the onoxidation by anodic oxidation takes place. Method according to claim 1 or 2, characterized that the etching by an HF-containing solution he follows. Method according to one of claims 1 to 3, characterized in that the introduction of the areas ( 6 ) of the other type of line together with the generation of compensation areas ( 5 ) is made for the production of Kompensationsbauelementen. A method according to claim 4, characterized gekenn characterized in that a vertical dose variation via an adjustment of the lateral extent of the regions ( 6 ) of the other type of line and / or the compensation areas ( 5 ) in different epitaxial planes of the semiconductor body ( 1 ) is produced. Method according to one of claims 1 to 3, characterized in that the introduction of the areas ( 6 ) of the other conductivity type by thermomigration. A method according to claim 6, characterized in that the thermal migration by applying a metallization layer ( 18 ) on a surface of the semiconductor body ( 1 ) and applying a temperature gradient to the semiconductor body ( 1 ) is carried out. Method according to claim 7, characterized in that for the metallization layer ( 18 ) a structured aluminum layer is used. Method according to claim 7 or 8, characterized that the temperature gradient in a temperature step by means of RTA or irradiation with high-energy particles is set. Method according to one of claims 1 to 9, characterized in that the semiconductor body ( 1 ) is formed of silicon. Method according to one of claims 1 to 10, characterized in that the semiconductor body ( 1 ) is severed at least locally by the trench. Method according to one of claims 1 to 11, characterized in that after the etching of the limited area ( 7 ) at least parts of the at least two regions ( 6 ) are removed. Method according to claim 12, characterized in that the removal of the parts of the at least two regions ( 6 ) is performed by isotropic etching. Method according to one of claims 1 to 13, characterized that the trench is provided in an edge termination. Method according to one of claims 1 to 14, characterized in that the trench is at least partially filled with polycrystalline silicon, a metal silicide or an insulator, in particular with glass (SiO ₂ ) or polyimide. A method according to claim 11, characterized in that the at least locally severed semiconductor body ( 1 ) is used as a carrier disk for a semiconductor device.