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DE102004020497B8 - Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen - Google Patents

Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen Download PDF

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Publication number
DE102004020497B8
DE102004020497B8 DE102004020497A DE102004020497A DE102004020497B8 DE 102004020497 B8 DE102004020497 B8 DE 102004020497B8 DE 102004020497 A DE102004020497 A DE 102004020497A DE 102004020497 A DE102004020497 A DE 102004020497A DE 102004020497 B8 DE102004020497 B8 DE 102004020497B8
Authority
DE
Germany
Prior art keywords
plated
holes
production
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102004020497A
Other languages
English (en)
Other versions
DE102004020497B3 (de
Inventor
Edward FÜRGUT
Holger Wörner
Simon Jerebic
Michael Bauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102004020497A priority Critical patent/DE102004020497B8/de
Priority to PCT/DE2005/000754 priority patent/WO2005104226A2/de
Publication of DE102004020497B3 publication Critical patent/DE102004020497B3/de
Application granted granted Critical
Publication of DE102004020497B8 publication Critical patent/DE102004020497B8/de
Priority to US11/586,740 priority patent/US7482198B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W70/095—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H10W70/09—
    • H10W70/093—
    • H10W70/611—
    • H10W70/614—
    • H10W70/635—
    • H10W72/0198—
    • H10W90/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0215—Metallic fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0242—Shape of an individual particle
    • H05K2201/0257—Nanoparticles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/105—Using an electrical field; Special methods of applying an electric potential
    • H10W70/60—
    • H10W72/9413—
    • H10W90/722—
    • H10W99/00—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Insulated Conductors (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
DE102004020497A 2004-04-26 2004-04-26 Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen Expired - Fee Related DE102004020497B8 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE102004020497A DE102004020497B8 (de) 2004-04-26 2004-04-26 Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen
PCT/DE2005/000754 WO2005104226A2 (de) 2004-04-26 2005-04-25 Verfahren zur herstellung von durchkontaktierungen durch eine kunststoffmasse und halbleiterbauteil mit derartigen durchkontaktierungen
US11/586,740 US7482198B2 (en) 2004-04-26 2006-10-26 Method for producing through-contacts and a semiconductor component with through-contacts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004020497A DE102004020497B8 (de) 2004-04-26 2004-04-26 Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen

Publications (2)

Publication Number Publication Date
DE102004020497B3 DE102004020497B3 (de) 2006-01-19
DE102004020497B8 true DE102004020497B8 (de) 2006-06-14

Family

ID=35197629

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004020497A Expired - Fee Related DE102004020497B8 (de) 2004-04-26 2004-04-26 Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen

Country Status (3)

Country Link
US (1) US7482198B2 (de)
DE (1) DE102004020497B8 (de)
WO (1) WO2005104226A2 (de)

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WO2008009779A1 (en) 2006-07-21 2008-01-24 Valtion Teknillinen Tutkimuskeskus Method for manufacturing conductors and semiconductors
FI122014B (fi) 2007-06-08 2011-07-15 Teknologian Tutkimuskeskus Vtt Menetelmä ja laite nanopartikkelijärjestelmien toiminnallistamiseksi
FI122011B (fi) 2007-06-08 2011-07-15 Teknologian Tutkimuskeskus Vtt Menetelmä elektroniikkamoduulin tuottamiseksi, välituote elektroniikkamoduulin valmistamiseksi, muistielementti, painettu elektroniikkatuote, anturilaite sekä RFID-tunniste
FI122644B (fi) 2007-06-08 2012-04-30 Teknologian Tutkimuskeskus Vtt Menetelmä sähköisesti johtavien tai puolijohtavien reittien muodostamiseksi substraatille sekä menetelmän käyttö transistorien tuottamiseen ja anturien valmistukseen
KR100842921B1 (ko) * 2007-06-18 2008-07-02 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
KR100885924B1 (ko) 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
TWI360207B (en) * 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
FR2923081B1 (fr) * 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
KR20110096060A (ko) * 2008-12-02 2011-08-26 피코드릴 에스 아 기판 내에 구조물을 도입하는 방법
TWI456715B (zh) * 2009-06-19 2014-10-11 日月光半導體製造股份有限公司 晶片封裝結構及其製造方法
US8310835B2 (en) * 2009-07-14 2012-11-13 Apple Inc. Systems and methods for providing vias through a modular component
TWI466259B (zh) * 2009-07-21 2014-12-21 日月光半導體製造股份有限公司 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法
TWI405306B (zh) * 2009-07-23 2013-08-11 日月光半導體製造股份有限公司 半導體封裝件、其製造方法及重佈晶片封膠體
KR20120041224A (ko) * 2009-08-19 2012-04-30 피코드릴 에스 아 기판에 전기 도전성 바이어를 제조하는 방법
US8242543B2 (en) * 2009-08-26 2012-08-14 Qualcomm Incorporated Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
TWI497679B (zh) * 2009-11-27 2015-08-21 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 日月光半導體製造股份有限公司 半導體封裝件及其製造方法
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
JP2012209424A (ja) * 2011-03-30 2012-10-25 Tokyo Electron Ltd 半導体装置の製造方法
CN108376519B (zh) * 2018-04-27 2020-09-01 上海中航光电子有限公司 一种异形显示面板及其制作方法、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2902002A1 (de) * 1979-01-19 1980-07-31 Gerhard Krause Dreidimensional integrierte elektronische schaltungen
EP0611129A2 (de) * 1993-02-08 1994-08-17 General Electric Company Eingebettetes Substrat für integrierte Schaltungsmodule
US6190509B1 (en) * 1997-03-04 2001-02-20 Tessera, Inc. Methods of making anisotropic conductive elements for use in microelectronic packaging
DE10153609C2 (de) * 2001-11-02 2003-10-16 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips

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JPS60167491A (ja) * 1984-02-10 1985-08-30 株式会社東芝 導体路形成方法
US5476714A (en) * 1988-11-18 1995-12-19 G & H Technology, Inc. Electrical overstress pulse protection
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
JPH0861331A (ja) * 1994-08-15 1996-03-08 Toranosuke Kawaguchi 金属接合方法
US5962815A (en) * 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
DE19715898A1 (de) * 1997-04-16 1998-10-22 Polus Michael Substrat mit Leiterbahnvernetzung und Verfahren zu dessen Herstellung
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
DE10138278C1 (de) 2001-08-10 2003-04-03 Infineon Technologies Ag Elektronisches Bauteil mit aufeinander gestapelten elektronischen Bauelementen und Verfahren zur Herstellung derselben
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2902002A1 (de) * 1979-01-19 1980-07-31 Gerhard Krause Dreidimensional integrierte elektronische schaltungen
EP0611129A2 (de) * 1993-02-08 1994-08-17 General Electric Company Eingebettetes Substrat für integrierte Schaltungsmodule
US6190509B1 (en) * 1997-03-04 2001-02-20 Tessera, Inc. Methods of making anisotropic conductive elements for use in microelectronic packaging
DE10153609C2 (de) * 2001-11-02 2003-10-16 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips

Also Published As

Publication number Publication date
WO2005104226A2 (de) 2005-11-03
US7482198B2 (en) 2009-01-27
WO2005104226A8 (de) 2007-03-01
WO2005104226A3 (de) 2006-06-08
DE102004020497B3 (de) 2006-01-19
US20070099345A1 (en) 2007-05-03

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Legal Events

Date Code Title Description
8100 Publication of patent without earlier publication of application
8396 Reprint of erroneous front page
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee