DE10135775B4 - Methods and devices for checking and reading out the programming of a cavity fuse - Google Patents

Abstract

Method for checking the programming of a cavity fuse (10), which comprises a programmable bridge (12) made of a first conductive material with an anode (A) and a cathode (K) and a cover (14) made of a second conductive material the bridge (12) is arranged, characterized in that the resistance between cover (14) on the one hand and anode (A) and / or cathode (K) on the other hand is determined.

Description

The invention relates to a method for testing the programming of a cavity fuse according to the preamble of claim 1, a test circuit according to the preamble of claim 5, a method for Reading out the programming of a cavity fuse according to the generic term of claim 10, a read circuit for a cavity fuse after Preamble of claim 15, a fuse cell according to the preamble of claim 18 and a fuse matrix according to claim 20.

For one-time programming of a integrated circuit or an IC (Integrated Circuit) in cases the high reliability often require, especially in the automotive field so-called cavity fuses are used. Such cavity fuses are also known as fusible links.

Generally, under a fuse in a semiconductor fuse and circuit technology understood that are permanently programmed to a binary value can. In the case of a cavity fuse, for example, a polysilicon bridge is passed through caused a strong programming impulse to melt. The height Reliability of this Programming method stirs hence that the melting of the bridge on the occasion of programming is irreversible is.

In contrast to EPROMs (Electrical Programmable Read Only Memories) or EEPROMs (Electrical Erasable and Programmable Read Only Memories), whose programming load is different u.U. while can volatilize the lifespan of the block, is therefore a permanent programming achieved.

The patent DE 199 26 107 C1 describes a cavity fuse that is arranged vertically between a contact and a buried layer. The cavity fuse has a programmable bridge made of conductive material

The patent US 5,668,818 describes a method in which the programming of a cavity fuse is checked by reading out and comparing it with predetermined target values.

1 shows a cavity fuse known from the prior art 10 with connected readout circuit. The cavity fuse 10 consists of a (polysilicon) bridge 12 , which is arranged between an anode A and a cathode K. The cathode K is at a reference potential. A current is impressed into the anode A via a current mirror. The current mirror consists of the current source IL1 and two p-MOS transistors Q1 and Q2. The source of the p-MOS transistor Q2 is connected to a supply potential VDD; Drain is connected to anode A. bridge 12 , Anode A and cathode K are covered 14 covered, which is indicated as a dashed bordered approximately rectangular area. The bridge 12 the cavity fuse shown 10 has melted, ie the fuse is programmed.

The surface or cover 14 of the cavity under which the bridge is located 12 , Anode A and cathode K is entirely or partially either non-conductive or conductive; in the latter case, however, at least electrically floating. This means that this conductive structure is electrically isolated from the rest of the circuit, so that neither charges can nor can it fly off.

If the fuse is programmed correctly and is not a parasitic conductive Path between anode A and cathode K of the cavity fuse, the potential U1 at the anode A is identical to the supply potential VDD because transistor Q2 is in saturation goes (he can not read current in the extremely high-resistance fuse memorize).

Also from the state of the art Aluminum fuses known. These work similarly to the cavity fuses. By a strong programming pulse becomes a instead of a polysilicon bridge thin aluminum pipe melted. Therefore are exceptional compared to melting a polysilicon bridge high currents required in the range of about 0.5A. This is because the Aluminum web only through a thin Dielectric is separated from the substrate and thus in a very intimate way thermal contact to the good heat-conducting Silicon stands. To keep the necessary temperatures To generate in the fuselage, a high current must flow.

In addition to programming through cavity fuses becomes common also uses the so-called zener zapping. It is during the Programming a high voltage applied to a zener diode, so that the diode is short-circuited and then remains low-resistance. This widespread process has the disadvantage of being compared to cavity fuses also great streams in the range of approximately 200 mA are necessary. In circuits in which for protection reasons there is therefore no series resistance in the supply line possible, an already implemented, i.e. built-in integrated circuit to be programmed (so-called in-circuit programming).

Polysilicon bridges are also used to program an IC at the wafer level, even before assembly in a housing, although these are programmed by bombardment with a laser. Such fuses are therefore referred to as laser fuses. However, they cannot be programmed after the IC has been installed. This means that inaccuracies caused by the assembly of the IC can not be calibrated out. In the case of analog ICs in particular, however, it is often essential that offsets and temperature responses caused by mechanical tensioning of the IC or Chips in the chassis are greatly affected after the chassis assembly trims.

The cavity fuses stand out in the Difference to zener zapping by a much lower one Programming power off: you need a current of only approx. 50 mA, i.e. approx. 25% of the Zener programming current. This low programming current is achieved because the polysilicon bridge does not is in direct thermal contact with the chip: you is not like everyone else Components diffused into the IC, more precisely its substrate or on the surface of the IC grew up, but it is located in a cavity. This means that the point that melts when programming is only of relatively poor thermal conductivity Air surrounds and the thermal contact to the rest of the IC is low. This is achieved by placing the polysilicon fuse on a sacrificial layer (the so-called sacrificial layer) is grown. Comes over it another sacrificial layer, with a kind of cover or cover is covered. This lid contains holes through which an acid passes Dissolve sacrificial layers can. As soon as the sacrificial layers are completely dissolved, the poly fuse floats like a bridge in the Air.

The lid or cover is there essentially of an electrically insulating oxide layer and an electrically conductive Polysilicon layer. The actual fuselage will be a first Polysilicon layer Poly1 produced, so there is the conductive part the cover from a second polysilicon layer Poly2.

While operation, the logical state of a cavity fuse ("programmed" or not programmed ") determined by the fact that a reading current the size of some Micro-amps stamped into the fuse becomes. In the programmed state, the bridge is usually melted, i.e. the conductive path between anode A and cathode K is interrupted.

If the fuse is programmed, it is their resistance is therefore very great. In the theoretical ideal case it is infinitely large, in practice at least larger than some mega-ohms. In this case the voltage drop is over the Fuse practically equal to the supply voltage. The power source goes then in saturation because available to her standing voltage swing is not sufficient to the reading current through the to drive high-resistance fuse. This can be called logic "HIGH" by a logic be recognized.

If the fuse is not programmed, that's her Resistance only about 100 ohms. Then the reading current only creates a very low voltage of approx. 100 mV at the fuse, which is the case with conventional logic in CMOS technology as "LOW" is recognized.

For a reliable one In programming memory, the reading current must be selected so that the voltage on a non-programmed fuse is small enough to be logically "LOW" to be recognized. On the other hand, the reading current must be selected that the voltage across the fuse according to the reading current even then still logically corresponds to "HIGH", if the programmed fuse "only" has a few megohms of resistance.

Under certain conditions However, the following reliability problem arises with cavity fuses come: If the cavity fuse is programmed, it melts and evaporates the polysilicon bridge due to the strong energy input usually within a few Microseconds. Since the cavity is almost hermetically sealed, the residual gases can escape badly and therefore sit on the walls of the Cavity.

Over the course of the life of the device it now especially at high temperatures and high voltages on the cavity fuse that between the two connections Cavity fuse a conductive Path educates. As a result, the resistance of this path can be relatively low be (for example 100 kOhm), so that when reading the Cavity fuse using the reading current method below circumstances such a small tension over the fuse sets that a "LOW" instead of a "HIGH" is recognized. This case must be avoided because the block thus its programming during may lose its lifespan (i.e. a "HIGH" can become "LOW", but not vice versa).

So far, this has been possible through further Process steps are eliminated, but this affects the manufacturing process expensive and the process run lengthened because additional Mask levels or at least additional work steps in processing became necessary.

The object of the invention is therefore Methods and devices for checking and reading out the programming a cavity fuse to indicate that the reliability problem mentioned during the Detect operation of the block and, if necessary, an error signal generate, in particular making the manufacturing process more expensive due to additional Mask levels or at least additional work steps in processing should be avoided.

This object is achieved by a method for checking the programming of a cavity fuse with the features of claim 1, a test circuit for a cavity fuse with the features of claim 5, a method for reading out the programming of a cavity fuse with the features of claim 10, a reading circuit for a Cavity fuse with the features of claim 15, a fuse cell with the features of claim 18 and a fuse matrix with the features of claim 20 solved. further advantageous embodiments, configurations and aspects of the present Er Invention result from the dependent claims, the description and the accompanying drawings.

One based on the invention essential idea is that to check and read the programming a cavity fuse, which is a programmable bridge made of a first conductive material with an anode and a cathode and a cover from a second conductive Material that is arranged to cover the bridge, the resistance between cover and anode and / or cathode is determined becomes. As already mentioned at the beginning, can undesirably parasitic conductive Form paths in the cavity fuse. By the invention can now such parasitic Paths between anode and cathode of the cavity fuse reliably determined and their effects are corrected if necessary.

To identify a parasitic path, the following is Circumstance helpful: It turns out that such a parasitic path usually always about the cover is closed. so if an already programmed one Cavity fuse becomes low-resistance in the course of its service life, usually there is also a low-resistance contact between Cover and anode and / or cathode. Is of particular importance here that the contact resistance between the cover and cathode or anode less than the resistance between the anode and cathode the cavity fuse is. Theoretically, this can be explained by the fact that remains of vaporized polysilicon between the anode and Cover and between the cover and the cathode to two conductive paths form. The series connection of both paths accordingly has one higher resistance on than either of the two individual paths. This can also be an option existing cover oxide damaged be facing the cover Anode and cathode insulated.

With the invention relatively easy detect whether a cavity fuse has tilted from "HIGH" to "LOW" is. This is only possible if the cavity fuse is in perfect working order Coverage with high resistance Anode and cathode. If the cavity fuse is partially damaged, do so there is contact between the cover and only one of the two electrodes (Anode or cathode): in this case the cavity fuse works but still, i.e. when reading out you get a "HIGH", because no path from anode to cover to cathode has yet formed Has. Is the fuse complete? damaged, so there is contact from cover to both electrodes and the reading results in a "LOW" instead of the original programmed "HIGH".

The invention relates to a first aspect is a method for checking the programming of a Cavity fuse, which is a programmable bridge made of a first conductive material with an anode and a cathode and a cover from a second conductive Has material that is arranged to cover the bridge. The procedure is now the resistance between the cover on the one hand and the anode and / or On the other hand, the cathode was found to cause a defect in the cavity fuse detect.

In a preferred embodiment a reading current is impressed into the anode first and then a second potential different from the first applied to the cover and the voltage between the anode and cathode measured. change the measured voltage with the potential change on the cover, so lies a conductive Path between one or both electrodes - anode and / or cathode - and cover in front. This assumes that the cavity fuse is programmed, i.e. the bridge is interrupted. Otherwise, i.e. if the measured voltage does not change is the cavity fuse OK, i.e. there is no leader Path between the electrodes and the cover. With this phase can therefore at least one contact with a programmed cavity fuse one of the electrodes and the cover can be reliably detected.

In a further phase, the Cathode has a reference potential before the reading current is impressed into the anode be placed. Now there is a conductive (parasitic) path between the anode and the cover, this results in the measured Tension a change. In this case there is a correctly programmed cavity fuse a conductive path between anode and cover, i.e. the cavity fuse is defective. This phase can be used for a programmed Cavity fuse a contact between anode and cover can be detected safely.

To establish contact or parasitic paths between Detect cover and cathode in a programmed cavity fuse a reference potential can be applied to the cathode, a read current in embossed the cover, the anode is isolated and the voltage between the cover and cathode can be measured. Is the potential on the cover the cavity fuse is significantly smaller than the operating voltage of the By means that impresses the reading current in the cover, so lies contact between cover and cathode.

Another aspect of the invention concerns a test circuit for a cavity fuse that is a programmable bridge made of a first conductive material with an anode and a cathode and a cover from a second conductive Material that is arranged to cover the bridge has. The test circuit is characterized in that it is used to carry out the The inventive method explained above is trained.

It preferably has means for Memorize one Reading currents, means for applying potentials and voltage measuring means on.

The means for impressing a reading current and the means for applying potentials can be transistors, in particular of the MOS type.

In a particularly preferred embodiment include the means of imprinting a reading current a current mirror, which makes a more accurate and ahead all constant, essentially load-independent reading current is obtained.

The test circuit can furthermore have control means which in particular to carry out the one explained above trained method according to the invention are. Take over in this embodiment the control means control the process steps required to check the Programming the cavity fuse are required. Will the test circuit for example in a complex electronic circuit, in particular used on an integrated circuit, other circuit modules can from implementation be relieved of the procedure. In addition, an examination can be carried out independently of additional external circuit parts or modules be performed by the integrated circuit itself.

The invention further includes a Method for reading out the programming of a cavity fuse, the a programmable bridge from a first conductive Material with an anode and a cathode and a cover a second conductive Material that is arranged to cover the bridge has. Be procedural a first read current in the anode and a second read current in the Cover stamped and the potentials at the anode and cover for determining that in the cavity fuse programmed value logically linked to an output signal.

In a concrete embodiment includes the logical link the inversion of the potential on the cover and an OR link with the potential at the anode. With this, through a few logical circuit elements feasible logic function can be read out at the same time Cavity fuse test performed and verification of the programming is carried out within certain limits become.

According to another aspect the invention is a read circuit for a cavity fuse, the one programmable bridge from a first conductive Material with an anode and a cathode and a cover a second conductive Material that is arranged to cover the bridge has. To safely read out a programmed value from the cavity fuse to be able are means of memorization a first read current into the anode and a second read current in the cover and means for evaluating the potentials on the anode and covering and logically linking the evaluated potentials are provided to be a value programmed in the cavity fuse as Get output signal.

Means for embossing are preferred first read current in the anode and a second read current in the Covering transistors, especially of the MOS type.

The means for evaluating the potential on the anode and cover and for logically linking the evaluated potentials are logic gates in a particularly preferred embodiment.

In a particularly preferred embodiment the second reading current is applied in a pulsed manner, so to speak: he in predetermined first periods, in which the cavity fuse is read, chosen so small that the potential at the cover is smaller than the potential in the event of a fault the anode is.

Finally, the second read stream in predetermined second periods, in which the cavity fuse is not read out, are selected to be of such a size that that it causes electromigration through which the growth of a developing parasitic Current path between the cover and cathode is inhibited.

To ensure the testability of the whole, formed by cavity fuse and the means provided for reading out electronic circuit will increase preferably before reading out the cavity fuse by means of a transistor, especially MOS transistor, put a potential on the cover and the output signal measured the first time; then the potential is generated by means of the transistor switched off and the output signal measured a second time; the The two measured output signal values can then be evaluated.

This includes, for example, measured output signal values from logical "HIGH" and then logically "LOW" both the means intended for reading and the cavity fuse okay. In contrast, the means provided for reading out are functional out of order if there are two consecutive output signal values a logical "LOW" results because, for example, the contact resistance to the cover increases is large; in this case, however, the cavity fuse is OK. Will be twice in a row a logical "HIGH" measured, the cavity fuse is faulty. The measurement result logically "LOW" and then logically "HIGH" is in principle not possible.

A fuse cell according to the invention includes a cavity fuse that makes up a programmable bridge a first conductive Material with an anode and a cathode and a cover made of one second conductive Material which is arranged to cover the bridge, the one explained above Read circuit, and a programming circuit for programming the Hohlraumfuse. Here, the anode with a supply line is the Fuse cell and the cathode connected to a transistor. hereby a very space-saving variant of a fuse cell is created, the one power transistor for switching the programming current on and off (this is the one connected to the cathode of the cavity fuse Transistor).

Preferably, the means for Programming and the means for reading out essentially MOS transistors on.

The fused cells are preferred arranged or used in a fuse matrix. Such a fuse matrix can exist as a library element in a CAD system, for example be so when designing an integrated circuit in this can be installed.

The invention is described below of figures closer to the drawing shown. Show it:

1 a cavity fuse with reading circuit according to the prior art,

2 1 shows a first exemplary embodiment of the reading circuit according to the invention for a cavity fuse in a first operating state,

3 this in 1 illustrated embodiment of the reading circuit according to the invention for a cavity fuse in a second operating state,

4 this in 1 illustrated embodiment of the reading circuit according to the invention for a cavity fuse in a third operating state,

5 2 shows a second exemplary embodiment of the reading circuit according to the invention for a cavity fuse in a first operating state,

6 a programming circuit for a cavity fuse according to the prior art, and

7 an embodiment of a programming circuit according to the invention.

The following can be the same or at least functional the same elements with the same reference numerals.

In 1 the normal reading circuit for a cavity fuse is shown in which the reading current is impressed into anode A and the voltage at anode A (compared to ground = cathode potential) is digitally evaluated. The cover is floating. For a more detailed description of 1 reference is made to the introduction to the description.

In 2 an extension of the conventional read circuit by the pMOS transistor Q3 and the nMOS transistor Q4 is shown, but is still switched to inactive, 3 shows how to use this expansion circuit to make a contact between anode A and the dashed, approximately rectangular cover 14 Detected: Such a contact exists when the anode voltage toggles from "HIGH" to "LOW" as soon as the cover 14 is grounded.

In 4 is shown how to make a contact between cathode K and cover with this expansion circuit 14 detected: Here the reading current is no longer impressed into the anode A, but into the cover 14 (the anode is floating). At the same time, the potential of the cover 14 digitally rated: if it is "LOW", there is a low-resistance contact between the cover and the cathode.

In a productive module, it is advisable to use the circuit functions from the 2 . 3 and 4 Execute in multiplex operation in successive clock cycles (for example, by switching the relevant transistors alternately on and off), save the three voltages or logical variables U1, U2, U3 in flip-flops and then carry out the following evaluation with the collected knowledge:
(U1 = "HIGH") and (U2 = "LOW") means: contact between cover and anode A;
(U3 = "LOW") means contact between cover and cathode K;
(U1 = "LOW") and (U3 = "LOW") means: contact between the cover and both electrodes, i.e. anode A and cathode K.

It is particularly in the last Case assumed that it was only used for programmed cavity fuses to a contact between the cover and one of the two electrodes can come. This may have to be done after processing and before Programming the module (i.e. during the wafer test or possibly also at the beginning of the module test).

The procedure just described requires some effort for the multiplexer circuit and then provides more information than that Module needed in practice for proper functioning.

5 shows a very simple modification of the usual read-out circuit, which not only recognizes the critical error “fuse is programmed, but is, according to contacts to the cover, read out as“ LOW ”, but even corrects it. For this purpose, in addition to the reading current IL1, which is in the anode A of the cavity fuse 10 another reading current IL2 is impressed into the cover 14 imprinted. Both anode and coverage potential are assessed digitally. If the anode potential is "HIGH", there is no further doubt about it. However, if the anode potential is "LOW", the fuse is only "not programmed" when there is no contact with the cover, that is to say when the cover potential is "HIGH" , However, if the coverage potential is "LOW", there is at least one contact 16 . 18 of cover 14 nach Kathode K. This contact 16 . 18 but can only have come about that the cavity fuse 10 has been programmed and a parasitic conductive path has subsequently formed. So the fuse should be "HIGH"; the circuit in 5 makes the correction and delivers "HIGH" at its output.

The additional circuitry for these measures is limited: only an OR gate OR and an inverter INV as well as a pMOS transistor Q3 (as a current source) are required. The additional power loss is in static operation and as long as there is no parasitic path formed by cover against cathode has about zero.

If the cavity fuses are correct and there is no contact with the cover, no read current IL2 flows - so it does not contribute to the power consumption of the device. However, if the cavity fuse has a parasitic path between cover 14 and has cathode K, efforts are made to detect it with a high degree of certainty. Therefore, IL2 should not be too large, so that potential S2 will surely become "LOW" before potential S1 becomes "LOW".

However, it is possible to only turn the potential S2 on read out at certain times. Recommended at other times it is appropriate to choose the current IL2 as large as possible: Electromigration can then possibly reverse the parasitic path. There is an upper limit due to the maximum allowed power consumption of the building block.

A special aspect of the reliability of this circuit is its testability: It could be, for example, that due to processing errors (eg dust on the chip surface during exposure) the contact from the node with the potential S2 to the cover 14 the cavity fuse 10 in 5 is not properly executed. It may then have a contact resistance of many megohms. In this case it can happen when revitalizing the fuse 10 a low-resistance contact from the anode A to the cover 14 and from the cover 14 to the cathode K, but the potential S2 remains "HIGH" because the voltage drop across the contact resistance is so great. Then the circuit does not recognize the cover contact and supplies a "LOW" at the output OUT.

This extremely unlikely case of a double fault ( 1 , Fault: Fuse revitalizes in the course of the service life load, 2nd fault: faulty contact between node or line with potential S2 and cover 14 ) can be switched off if you test the contact resistance in the wafer or block test. The nMOS transistor Q5 in serves for this purpose 5 , Its drain is right on the cover 14 the fuse 10 contacted with their own contact. When testing the device, the gate of Q5 is set to "HIGH" so that its channel becomes low-resistance. If the contact resistances from the node or from the line, the potential S2 is on the cover 14 as well as from the cover 14 on the drain of Q5 are properly low-resistance, then S2 becomes "LOW", S3 "HIGH" and the output signal OFF "HIGH". If Q5 is then switched off, OFF becomes "LOW" (because the fuses have not yet been programmed at this point in time) are).

• 1.) die Abdeckungskontaktierung samt Inverter und ODER-Gatter voll funktionsfähig ist und
• 2.) die Fuse im Originalzustand niederohmig (also unprogrammiert) ist.

From this sequence it can be concluded that

• 1.) the cover contact including inverter and OR gate is fully functional and
• 2.) the fuse is in the original state with low resistance (i.e. unprogrammed).

Would the cover contact has been processed with high resistance, then you would get the sequence "LOW", "LOW" as well as in the test with low-resistance fuse with high-resistance fuse, the sequence "HIGH", "HIGH". Both times the Processing errors discovered; the module can be retired.

It has not yet been shown how the cavity fuse is programmed. 6 first shows the state of the art. An essential feature is that the switching transistors that conduct the high programming current through the fuse are on the anode side of the fuse and the cathode of the fuse is at ground.

In contrast, shows 7 a space-saving variant according to the invention, in which the cathode K of the cavity fuse 10 is placed on the drain of a power nMOS Q6. This nMOS Q6 is switched on for programming the relevant fuse and pulls the programming current towards ground. The reading current is from the cathode K and from the cover 14 The resulting potentials are drawn using an inverter and a nand gate (similar to that in 6 ) linked to an output signal AUS.

This variant has the advantage of being particularly space-saving to be there for each fuse uses only the minimum necessary number of power transistors - namely one. In addition, this is an nMOS transistor due to its lower channel resistance when switched on is again smaller than a pMOS transistor. Another advantage of the nMOS transistor is its powerless control: You can get your gate in normal operation with a strong inverter ground to the transistor so that the transistor also in the event of ESD and EMC events stays safely off. This strong inverter pulls in the static Operation no electricity (except a negligible Leakage current) and thus contributes not significant for the power loss of the device.

The following are those in the 2 - 7 illustrated circuits explained in particular in terms of their operation.

2 shows an extension of the conventional reading circuit according to the invention 1 through the transistors Q3, Q4: If the fuse 10 is correctly programmed and there is no parasitic conductive path between anode A and cathode K of the cavity fuse 10 has formed, the potential U1 is identical to VDD, since transistor Q2 saturates (it cannot impress the reading current in the extremely high-resistance fuse). Transistors Q3 and Q4 represent the extension of the conventional read circuit. They both contact the conductive cover 14 the cavity fuse 10 , but are both turned off at this stage of the reading process (ie from the cover 14 can neither Charges to still drain).

3 : In the 2nd phase of the reading process, the reading current is still in the anode A of the cavity fuse 14 imprinted. However, the gate of Q4 is connected to VDD, so that the cover potential is pulled to ground. If it is - as in 3 indicated - to a contact 16 between cover 14 and anode A of the cavity fuse 10 has come, Q4 pulls the potential U2 over this contact 16 by mass. Such a contact 16 is therefore detected if in phase 1 U1 = "HIGH" (see 2 ) and in phase 2 U2 = "LOW". This damage to the cavity fuse 10 is of minor importance, however, because it does not change the programmed logic state of the fuse 10 (this is still "HIGH").

4 : In the 3rd phase of the reading process, the reading current is fed into the anode A of the cavity fuse 10 switched off so that the anode A floats (ie no charges can be dissipated or supplied from the anode A). Q4 is turned off by grounding its gate. Q3 turns on so this transistor tries to put current into the cover 14 the cavity fuse 10 memorize. Usually - if the cover 14 So the potential U3 = VDD has no conductive connection to the cathode K. However, if - as in 4 shown - a conductive path between cover 14 and cathode K of the fuse 10 trained (contact 18 ), U3 will use this contact 18 pulled against mass.

5 shows a readout circuit that a first read current in the anode A and a second read current in the cover 14 the cavity fuse 10 impresses. If the fuse 10 is correctly programmed (i.e. no parasitic path from A to K via the cover 14 ) the output signal becomes AUS = "HIGH". If a parasitic path has formed from A to K, so that the signal S1 = "LOW", then S2 = "LOW". Here it is assumed that the contact resistance between cover 14 and K can never get larger than that between A and K via cover 14 , If S2 is "LOW", S3 becomes "HIGH" and the output signal OFF = "HIGH". The output signal OFF therefore appears as that of a programmed cavity fuse 10 corresponds to: the circuit has too low AK resistance of the fuse 10 detected and corrected due to cover contact error.

• 1.) Wenn sich ein Kontakt zwischen Anode A und Kathode K unter Umgehung der Abdeckung 14 bildet, so wird dieser immer als „LOW" (= nicht programmiert) bewertet. Dieser Fehlermechanismus tritt jedoch in der Praxis nicht auf.
• 2.) Wenn sich ein Kontakt zwischen Abdeckung 14 und Kathode K bildet, obwohl die Fuse nicht programmiert wurde, so wird ein „HIGH" erkannt. Es gibt keine bekannte Ursache, die zu diesem Fehlerbild im Laufe der Lebensdauer führen könnte. Lediglich ein Prozessierungsfehler und/oder Montagefehler könnte unter Umständen zu einem Kontakt zwischen Abdeckung 14 und Kathode K führen. Daher müssen die Bausteine nach Beendigung der Prozessierung und Montage, aber noch vor der Programmierung diesbezüglich getestet werden.

The circuit only fails in the following two cases:

• 1.) If there is contact between anode A and cathode K bypassing the cover 14 , this is always rated as "LOW" (= not programmed). However, this error mechanism does not occur in practice.
• 2.) If there is contact between the cover 14 and cathode K forms, even though the fuse has not been programmed, a "HIGH" is recognized. There is no known cause which could lead to this error pattern in the course of the service life. Only a processing error and / or assembly error could possibly lead to contact between cover 14 and lead cathode K. For this reason, the blocks must be tested after processing and assembly, but before programming.

To make sure the cover 14 contact has been made correctly and the NOR gate is functioning, the nMOS transistor Q5 is used: this transistor is switched on in the test (before programming). If a "HIGH" then appears as the output signal OFF, the cover contact is OK. Q5 is then always switched off during further operation.

6 shows a programming circuit for fuses according to the prior art: each fuse is expanded by a programming circuit to a fuse cell, which is only used to ignite the fuse. All fuse cells are interconnected for their power supply on a common supply line. The lines drawn in bold carry the programming current when the fuse F shown is fired. In order to switch the large currents at mostly high voltages, npn bipolar transistors are used. The transistor T1 can be actuated in different ways. An extension to a Darlington transistor (transistor T1 with transistor T2) with a control via a pnp transistor T3 is shown.

Essential feature of this circuit (in contrast to 7 ) is that the fuse is grounded on one side and the switching transistor T1 on the anode of the fuse. Furthermore, the line Lp is only connected to a sufficiently high voltage for programming. In normal operation (when the fuses are read out) the line Lp is connected to OV.

Because of the numerous bipolar transistors the space requirement this fuse cell significantly since every single fuse with this circuit must be equipped. Another disadvantage is that voltage pulses on the Lp line (due to ESD and EMC events) cause T1 briefly (for a few nanoseconds to microseconds) because its Base according to the great Basic collector capacity is "pulled up" for a short time. T1 cannot therefore be switched off perfectly (at least in the case of transients Glitches).

7 shows a space-saving variant of a fuse matrix according to the invention. All fuses hang with their anode A on a common "Supply Line" SL. When fusing, ie when programming fuses, this "Supply Line" SL is placed on a high potential and the fuse to be programmed 10 selected by means of transistor Q6. When reading out, the "Supply Line" SL is connected to the supply voltage of the logic gates, which is based on a ner integrated circuit are integrated together with the fuse matrix. The read current IL is fed through a transistor Q2 into the cathode K, through a transistor Q3 into the cover 14 fed. The resulting potentials S4 and S5 are logically combined with an inverter and a nand gate, and deliver a "HIGH" as the output signal AUS if the fuse link AK is high-impedance or if the cover 14 shows a low-resistance contact to anode A, for example via the contact 16 , Transistor Q5 has a function similar to that in FIG 5 transistor Q5 shown.

An advantage of this circuit is that transistor Q6 can be switched off very efficiently, so that no current flows through the fuse even at voltage pulses at anode A. 10 flows and an unprogrammed fuse is loaded as little as possible with electricity. Furthermore, this unit cell is very small compared to that in 6 shown, because it needs exactly one power transistor that switches the fuse current on / off.

10

Hohlraumfuse

12

bridge

14

cover

16

Contact between anode and cover

18

Contact between cathode and cover

Q1

pMOS transistor

Q2

pMOS transistor

Q3

pMOS transistor

Q4

nMOS transistor

Q5

nMOS transistor

IL-1

power source

U1

measuring voltage

U2

measuring voltage

U3

measuring voltage

INV

inverter

OR

OR gate

S1

circuit node

S2

circuit node

S3

circuit node

OUT

readout signal

Claims (20)

Procedure for checking the programming of a cavity fuse ( 10 ) which is a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material that is used to cover the bridge ( 12 ) is arranged, characterized in that the resistance between the cover ( 14 ) on the one hand and anode (A) and / or cathode (K) on the other. A method according to claim 1, characterized in that a reading current is impressed into the anode (A), a first and then a second potential different from the first to the cover ( 14 ) and the voltage (U2) between anode (A) and cathode (K) is measured. A method according to claim 2, characterized in that to the Cathode (K) a reference potential before the reading current is impressed into the anode (A) is placed. Method according to one of the preceding claims, in particular according to claim 1, characterized in that a reference potential is applied to the cathode (K), a read current in the cover ( 14 ), the anode (A) is isolated and the voltage (U3) between the cover ( 14 ) and cathode (K) is measured. Test circuit for a cavity fuse that connects a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material that is used to cover the bridge ( 12 ) is arranged, characterized in that the test circuit (Q3, Q4) is designed to carry out the method according to one of the preceding claims. Test circuit according to claim 5, characterized in that they means (IL1, Q1, Q2; Q2, Q3) for impressing a read current, means (Q3, Q4) for applying potentials and voltage measuring devices (OR, INV). Test circuit according to claim 6, characterized in that the means (IL1, Q1, Q2; Q2, Q3) for impressing a read current and the Means (Q3, Q4) for applying potentials to transistors, in particular are of the MOS type. Test circuit according to claim 7, characterized in that the means (IL1, Q1, Q2; Q2, Q3) for impressing a read current one Include current mirror. Test circuit according to one of claims 5-8, characterized in that it has control means for carrying out a method according to a of claims 1-4 trained are. Method for reading out the programming of a cavity fuse ( 10 ) which is a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material that is used to cover the bridge ( 12 ) is arranged, characterized in that a first read current into the anode (A) and a second Read current in the cover ( 14 ) and the potentials (S1, S2) on the anode (A) and cover ( 14 ) to determine the in the cavity fuse ( 10 ) programmed value can be logically linked to an output signal (AUS) (INV, OR). A method according to claim 10, characterized in that the logical combination of the inversion (INV) of the potential (S2) on the cover ( 14 ) and an OR link (OR) with the potential (S1) at the anode (A). A method according to claim 10 or 11, characterized in that the second read current in predetermined first periods in which the cavity fuse ( 10 ) is selected so small that the potential (S2) on the cover ( 14 ) is smaller than the potential (S1) at the anode (A). Method according to one of claims 10-12, characterized in that the second read current in predetermined second periods in which the cavity fuse ( 10 ) is not read out, is chosen so large that it causes an electromigration through which the growth of a parasitic current path that forms between the cover ( 14 ) and cathode (K) is inhibited. Method according to one of claims 10-13, characterized in that before reading out the cavity fuse ( 10 ) by means of a transistor, in particular MOS transistor (Q5), a potential to the cover ( 14 ) and the output signal (AUS) is measured a first time, then the potential is switched off by means of the transistor and the output signal (AUS) is measured a second time and the two measured output signal values are evaluated. Reading circuit for a cavity fuse that connects a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material that is used to cover the bridge ( 12 ) is arranged, characterized in that means for impressing a first read current into the anode (A) and a second read current into the cover ( 14 ) and means for evaluating the potentials (S1) at the anode (A) and cover (S2, 14) and for logically combining the evaluated potentials are provided to one in the cavity fuse ( 10 ) to receive the programmed value as an output signal (OFF). Reading circuit according to claim 15, characterized in that means for impressing a first reading current into the anode (A) and a second reading current into the cover ( 14 ) Transistors (Q2, Q3), in particular of the MOS type. Reading circuit according to claim 15 or 16, characterized in that means for evaluating the potentials (S1) at the anode (A) and cover (S2, 14) and for logical linking of the evaluated potentials are logic gates (INV, OR). Fuse cell with a cavity fuse ( 10 ) which is a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material that is used to cover the bridge ( 12 ) is arranged, has a reading circuit (Q5, Q3, Q2, NAND) according to one of claims 1-17, and a programming circuit (Q6) for programming the cavity fuse ( 10 ) characterized in that the anode (A) is connected to a supply line (SL) of the fuse cell and the cathode (K) is connected to a transistor (Q6). Fuse cell according to claim 18, characterized in that the Means for programming (Q6) and the means for reading (Q5, Q3, Q2, NAND) MOS transistors (Q2, Q3, Q5, Q6). Fusematrix, characterized in that they follow Fusezellen Claim 18 or 19.