DE10125911A1 - Interface forming device - Google Patents

Abstract

Device for enabling testing of proprietary or manufacturer memory chips with a standard system board. Device (100) for forming an interface between a first circuit board (102) for operation of a first memory module with a first clock signal, and a register for operating a command address bus of the first circuit board and a data bus of a first width and a second memory module (104) that is operated with a second clock signal and a buffer (110) for operating its command address bus. The device has the following characteristics: an arrangement (114) for matching first and second clock signals, an arrangement for matching buffer and register and an arrangement for matching the two data bus widths.

Description

The present invention relates to a device to form an interface and in particular to a front direction for forming an interface between a memory chermodule and a circuit board.

Standard memory modules are usually specified built by Intel. The main board of a Compu ters, such as B. a personal computer (PC), the ver recognize different types of standard memory modules and manage. For the specifications of memory modules are in particular the data bus width used, the clock scheme (Clocking) and the command address bus topology (command Address bus topology) important. Become standard memory modules typically on data buses with a width of 64 bits o of the 72 bits operated when an error code correction (ECC; ECC = Error Code Correction), in addition to the 64 bits 8 bits are used to detect errors and to be able to correct. The clock control from Standardspei chermodule is usually done with a "positive" clock signal (CLK +) indicating a logical LVTTL level (0 V-3.3 V) having. Standard memory modules have their own description Missing address bus topology by the line lengths that used blocks that characterize wave resistances, etc. and is used to operate on the command address Bus usually a register. In the register that is commands can be timed by the clock signal and addresses are temporarily stored or adjusted in order to then, for example, to the memory components in the memory to be passed on. The register has the another function, a capacitive load or electrical load in the main board, which is determined by the cable lengths and the ka capacitive memory devices is caused to reduce  since this capacitive load causes the signal rise times and the timing of signals influenced.

Customer-specific memory modules, for example at Ser vern or workstations used differ of standard memory modules both in terms of data bus wide, the timing scheme and possibly the command Address bus topology. Custom memory modules will be for example on data buses with a width of 144 bits, 2 times 72 bits with error code correction (ECC), operated and ver apply a clock scheme in which the clock control differ tiell, d. H. both with a "positive" clock signal (CLK +) as well as a "negative" clock signal (CLK-). The Clock signals usually have a PECL level (1.6 V-2.3 V). Customer-specific memory modules also have usually also a command address bus topology, where the command address bus is through a buffer, of a logical level, e.g. B. a high logic level ("High") of an input sig nals, input signals to an output of the same pushes. The buffer also serves as the register for the Stan dard memory modules to reduce the capacitive load of the Motherboard. Another difference from custom There are memory modules compared to standard memory modules in that the customer-specific memory modules in total including both mechanically and electrically from standard games Distinguish memory modules and thus with motherboards that according to Intel's specifications for standard games chermodules are built, are not compatible.

Standard memory modules can easily be used for testing conventional PC motherboards that are tested in large Numbers are available on the market and therefore cost are cheap to buy. Custom memory modules on the other hand have to be used in additional main platforms NEN, so-called application boards, are tested and cannot or only to a limited extent on standard motherboards  be checked. This is due, for example, to the aforementioned un Different clock control, the customer-specific Memory modules compared to standard memory modules for example differential (CLK +, CLK-). The development and the use of such application boards is e.g. B. on due to the use of different logic levels at the Signal transmission, with a significant logistical and technical effort connected.

A problem in the prior art is therefore that testing customer-specific memory modules with one is very expensive.

The object of the present invention is therefore in to create a device that is less expensive Allows testing of custom memory modules.

This object is achieved by a device according to claim 1 solved.

An advantage of the present invention is that the same is a simple test of custom memory module on standard motherboards.

Advantageous further training can be found in the subclaims gene and improvements of the Vorrich specified in claim 1 tung.

According to a preferred development of the device of In the present invention, the first clock signal has a be timed up, and the second clock signal has a specific timing and the on direction for adapting the first clock signal to the second Clock signal has a device for adjusting the time Alignment of the first clock signal with the timing of the second clock signal.  

According to a further preferred development, the first te clock signal a certain level and the second clock signal nal a certain level, and the device for on match the first clock signal to the second clock signal means for converting the level of the first clock signal nals to the level of the second clock signal.

According to a further preferred development, the one direction to adapt the buffer mode to the register Operating mode a register with which the command address bus the first circuit board with a register mode is operable, the register having an input and a Has output and with the buffer of a second storage mo duls at the input of the same is connectable.

According to a further preferred development, the one direction to adapt the buffer mode to the register Mode also a phase locked loop to the Be missing in the command address bus of the first circuit board to adjust in time with the first clock signal, the Phase locked loop has an input and an output and connected to the clock input of the register is.

According to a further preferred development, the one direction to adjust the timing of the first Clock signal to the timing of the second clock signal as a phase locked loop.

According to a further preferred development, the one direction to adjust the timing of the first Clock signal to the timing of the second clock signal as a lockable bridging for the case where the timing of the first clock signal and the two th clock signal is the same.  

According to a further preferred development, the one direction for converting the level of the first clock signal to the level of the second clock signal a lockable bypass in the case where the level of the first clock signal nals is equal to the level of the second clock signal.

According to a further preferred development, the Pha Sen control loop of the device for adjusting the buffer Operating mode to the register operating mode a lockable Ü bridging for the case in which the commands in the loading Missing address bus of the first circuit board with the first Clock signal are adjusted in time.

According to a further preferred development, the one direction to adapt the buffer mode to the register Operating mode also an inverter to the time range of the register, whereby the In verter has an input and an output and the on gear of the same ver with the output of the phase locked loop is bound and the output of it with a command Address bus of the first circuit board is connectable.

According to a further preferred development, the level an LVTTL level of the first clock signal, and the level of the second clock signal is a PECL level.

According to a further preferred development, the Means for converting the level of the first clock signal a logic ne in the level of the second clock signal yawed second clock signal.

According to a further preferred development of the present the invention has the phase locked loop of the device to adapt the buffer mode to the register Operating mode and / or the device for adjusting the time Chen adjustment of the first clock signal to the time Ab tuning the second clock signal a line with a be  matched length and a capacitor from the line is grounded.

According to a further preferred development, the first Circuit board a motherboard of a personal computer.

According to a further preferred development, the first Circuit board a circuit board for testing the two th memory module.

According to a further preferred development, the second Circuit board a motherboard of a special purpose Computer.

According to a further preferred development, the front direction on a circuit board on which the device for adapting the first clock signal to the second clock signal, the device for adapting the buffer mode to the Register mode and the facility to customize the second data bus width arranged to the first data bus width are.

Preferred embodiments of the present invention are below with reference to the accompanying drawings nations explained in more detail. Show it:

Fig. 1 shows a preferred embodiment of a device according to the present invention.

Fig. 1 shows an embodiment of an apparatus for forming an interface according to the present invention. The device 100 for forming an interface forms an interface between a first circuit board 102 , on which first memory modules, preferably memory modules that meet the specifications of Intel, can be used and operated, and a second memory module 104 , which is preferably an is custom memory module. The first circuit board 102 is preferably a motherboard of a personal computer, which can be used not only for operation but also for testing a first memory module 104 . The device 100 for forming an interface enables a second memory module 104 , e.g. B. a customized memory module, with a first circuit board 102 , such as. B. egg ner standard motherboard of a personal computer, both be operated and in particular can be tested.

On the first circuit board 102 first memory module and a first memory module 102 applies ver usually operable with a first clock signal having a certain timing and a certain Pe gel. The level of the first clock signal is preferably an LVTTL level. The first memory module 102 of such a first circuit board also has a register for operating a command address bus 106 of the first circuit board 102 with a register mode of operation and is also on a data bus 108 with a first data bus wide, preferably a standard data bus with a width 64 data bits or 72 data bits can be connected when using an error code correction with 8 data bits.

The second memory module 104 is usually operated and used on a second circuit board, which preferably before a customized circuit board for example for a special purpose computer, such as. B. is a main board for a server or a workstation. Customer-specific memory modules, such as the second memory module 104 , can be operated with a second clock signal which has a specific timing and a specific level. The level of the second clock signal is preferably a PECL level. The second memory module 104 has a buffer 110 , which is normally provided for operating a command address bus of a second circuit board with a buffer mode. The second memory module 104 can also typically be connected to a data bus with a second data bus width, which is, for example, a data bus with a customer-specific data bus width of 144 bits. The second memory module preferably has one or more memory components 112 , such as, for. B. dynamic random access memory (DRAM), which are connected to the buffer 110 .

The device 100 for forming an interface between a first circuit board 102 and a second memory module 104 has a device 114 for adapting the first clock signal to the second clock signal. The device 114 for adapting the first clock signal to the second clock signal comprises a device 116 for adapting the timing of the first clock signal to the timing of the second clock signal and further a device 118 for converting the level of the first clock signal to the level of second clock signal.

The device 116 for adapting the timing of the clock signals and the device 118 for converting the level of the clock signals are preferably converter modules which, for example, provide the different logic levels and the timing of the signals of the second memory module 104 , preferably a customer-specific memory module with PECL levels, in the logic level and the timing of the signals of a first memory module, preferably a standard memory module with LVTTL levels, which is on a first circuit board 102 , such as. B. a standard motherboard can be operated, convert into one another.

The device 116 for adapting the timing of the first clock signal to the timing of the second clock signal preferably has a phase-locked loop in which the clock signal is adjusted in time or passed on directly. The phase locked loop is preferably egg ne line with a certain length and a capacitor which is connected from the line to ground. The phase locked loop is also preferably a clock generator. By loading the phase-locked loop, the feedback loop of this loop can be lengthened or shortened. This causes the clock output signals against the input signal, such as. B. an LVTTL clock from the first circuit board 102 , such as. B. a PC motherboard, comes earlier or delayed output. The time intervals can be set using the phase locked loop. This is necessary because the memory components of the memory modules and also the registers require a certain setting time (set-up time) and hold time (hold time) to be able to store signals safely. The clock signals thus require a certain time from the other signals. The device 116 for adapting the timing of the first clock signal to the timing of the second clock signal can also preferably have a lockable bypass 120 for the case in which the timing of the first clock signal and the second clock signal are the same.

The device 118 for converting the level of the first clock signal into the level of the second clock signal can generate a logically negated second clock signal (CLK-) in addition to the second clock signal, since, for example, a PECL input is provided for a phase locked loop in a typical customer-specific memory module is. That is, in a first circuit board 102 , which is designed for LVTTL levels and only has a positive clock signal CLK +, this clock signal must be converted into a differential clock signal with a positive and a negative clock signal (CLK +, CLK-) for a PECL- Logic to be converted. The device 118 for converting the level of the first clock signal into the level of the second clock signal can also preferably have a lockable bypass 122 for the case in which the level of the first clock signal is equal to the level of the second clock signal and a level adjustment is therefore necessary.

The device 100 for forming an interface with a second memory module 104 also has a device 124 for adapting the buffer operating mode to the register operating mode. The device 124 for adapting the buffer mode to the register mode preferably has a register 126 , with which the command address bus 106 of the first circuit board 102 can be operated with a register mode, the register 126 having a first input and has an output and can be connected to the buffer 110 of the second memory module 104 at the first input. The command address signal is applied to a second input 128 of register 126 .

The means 124 for adapting the buffer mode to the register mode further preferably has a phase control loop 130 for timing the commands in the command address bus 106 of the first circuit board 102 with the first clock signal, the phase rule looping 130 has an input and an output and the input of which is connected to the clock input of register 126 . The phase locked loop 130 of the device 124 for adapting the buffer mode to the register mode preferably has a lockable bypass 132 for the case in which the commands in the command address bus 106 of the first circuit board 102 are timed with the first clock signal are adjusted, ie no timing is necessary. The phase locked loop 132 is preferably a line of a certain length connected to a capacitor connected from the line to ground.

The device 124 for adapting the buffer operating mode to the register operating mode furthermore has an inverter 134 which comprises a bypass 136 . The inverter 136 serves to increase the timing range of the register 126 , the inverter 134 having an input and an output, the input of which is connected to the output of the phase locked loop 130 and the output of which is connected to the command address bus 106 the first circuit board 102 is connectable.

By means of the device 124 for adapting the buffer operating mode to the register operating mode, it is possible to operate buffered customer-specific memory modules, here the second memory modules 104 , in register-based systems, whereby a timing compensation (timing compensation) by the Command locking (command latch) generated time offset takes place in relation to the customer-specific buffer mode. With the device 124 for adapting the buffer mode to the register mode, it is possible, similarly to the device 114 for adapting the first clock signal to the second clock signal, to time-control the command address signals.

The device 100 for forming an interface with a second memory module 104 also has a device 138 , which can be connected to the second memory module 104 and the first circuit board 102 , for adapting the second data bus width of the second memory module 104 to the first data bus width of the first Memory module or the first circuit board 102 on. The device 138 for adapting the data bus widths reduces, for example, the typical data bus width of the second memory module 104 , e.g. B. a customer-specific memory module, from 144 bits to the data bus width of 72 bits for a first circuit board 102 , such as. B. a standard motherboard, the le for first Speichermodules such. B. for standard memory modules is provided. With the aid of the device 138 for adapting the data bus widths, the data bits are distributed accordingly. For example, to test a memory module with 144 bits, two un different devices 100 are necessary to form an interface.

The device 100 for forming an interface also preferably has a circuit board on which the device 114 for adapting the first clock signal to the second clock signal, the device 124 for adapting the buffer mode to the register mode and the device 138 are arranged to adapt the second data bus width to the first data bus width. Such a circuit board is also called a Raiser card, in which the second memory module 104 , which is, for example, the device under test, is located in a memory module socket on the Raiser card, which itself, for. B. on an underside thereof, is connected to a memory module socket of the first circuit board 102, which is arranged on the first circuit board 102 for the first memory modules. The second memory module 104 is therefore not located directly in a socket on the first circuit board 102 but raised above the first circuit board 102 in a socket of the raiser card. The device 100 for forming an interface is also preferably arranged in order to rewire the chip select signals (chip select) and write enable signals (write enable) accordingly, ie to terminate signals that are not required and to add additional signals, such as. B. by doubling, inversion, etc. to generate.

The Raiser card or adapter card, which comes in standard Application or test boards can be inserted and ih on the one hand can accommodate the customer-specific memory modules, can be customized customer-specific memory modules in a tested or operated in a standard application environment become. The Raiser card transfers the signal levels and the timing from the standard Application board, d. H. the chipset, in a correspond appropriate customer-specific signaling and provides the physi calic connection. The raiser card therefore enables  a simple and inexpensive testing of customer-specific memory modules.

Although the present invention has been described above with reference to a preferred embodiment is described is the same not limited to this, but in a variety of ways can be modified.  

LIST OF REFERENCE NUMBERS

100

Device for forming an interface

102

first circuit board

104

second memory module

106

Instruction address bus

108

bus

110

Buffer from

104

112

Memory device from

104

114

Device for adjusting the clock signals

116

Device for adjusting the timing

118

Device for converting the levels

120

lockable bridging of

116

122

lockable bridging of

118

124

Device for adapting the operating modes

126

Register of

124

128

second entrance of

126

130

Phase locked loop of

124

132

lockable bridging of

130

134

inverter

136

lockable bridging of

134

138

Device to adjust the data bus width

Claims (17)

1. Device ( 100 ) for forming an interface between a first circuit board ( 102 ), which for operating first memory modules that can be operated with a first clock signal, a register for operating a command address bus of the first circuit board ( 102 ) have a register mode and can be connected to a data bus ( 108 ) with a first data bus width, is suitable, and a second memory module ( 104 ) which can be operated with a second clock signal, a buffer ( 110 ) for operating a command address Bus of a second circuit board with a buffer mode and can be connected to a data bus with a second data bus width, the device ( 100 ) for forming an interface having the following features:

• - means ( 114 ) for matching the first clock signal to the second clock signal;
• - means ( 124 ) for adapting the buffer mode to the register mode; and
• - A device ( 138 ) for adapting the second data bus width to the first data bus width.

2. The device ( 100 ) according to claim 1, wherein the first clock signal has a specific timing and the second clock signal has a specific timing, and the device ( 114 ) for adapting the first clock signal to the second clock signal means ( 116 ) for adapting the timing of the first clock signal to the timing of the second clock signal. 3. Device ( 100 ) according to claim 1 or 2, wherein the first clock signal has a certain level and the second clock signal has a certain level, and the device ( 114 ) for adapting the first clock signal to the second clock signal means ( 118 ) for converting the level of the first clock signal to the level of the second clock signal. 4. The device ( 100 ) according to claim 1, 2 or 3, wherein the means ( 124 ) for adapting the buffer mode to the register mode comprises a register ( 126 ) with which the command address bus ( 106 ) the first circuit board ( 102 ) can be operated with a register operating mode, the register ( 126 ) having an input and an output and being connectable to the buffer ( 110 ) of a second memory module ( 104 ) at the input thereof. 5. Device ( 100 ) according to one of the preceding claims, wherein the means ( 124 ) for adapting the buffer mode to the register mode further comprises a phase control loop ( 130 ) to the commands in the command address bus ( 106 ) of the first circuit board ( 102 ) to be adjusted in time with the first clock signal, the phase control loop ( 130 ) having an input and an output and having the input thereof connected to the output of the register ( 126 ). 6. The device ( 100 ) according to any one of claims 2 to 5, wherein the means ( 116 ) for adapting the timing of the first clock signal to the timing of the second clock signal comprises a phase locked loop. 7. The device ( 100 ) according to any one of claims 2 to 6, wherein the means ( 116 ) for adapting the timing of the first clock signal to the timing of the second clock signal has a lockable bypass ( 120 ) for the case in which the timing of the first clock signal and the second clock signal is the same. 8. The device ( 100 ) according to any one of claims 3 to 7, wherein the means ( 118 ) for converting the level of the first clock signal into the level of the second clock signal comprises a lockable bypass ( 122 ) for the case in which the level of the first clock signal is equal to the level of the second clock signal. 9. The device ( 100 ) according to any one of claims 5 to 7, wherein the phase locked loop ( 130 ) of the device ( 124 ) for adapting the buffer mode to the register mode has a lockable bypass ( 132 ) for the case in which the commands in the command address bus ( 106 ) of the first circuit board ( 102 ) are temporally adjusted with the first clock signal. 10. The device ( 100 ) according to any one of claims 5 to 7, wherein the means ( 124 ) for adapting the buffer mode to the register mode further comprises an inverter ( 134 ) to enable the register ( 126 ), wherein the inverter ( 134 ) has an input and an output and the input thereof is connected to the output of the phase-locked loop ( 130 ) and the output thereof can be connected to the command address bus ( 106 ) of the first circuit board ( 102 ). 11. The device ( 100 ) according to any one of claims 3 to 10, wherein the level of the first clock signal is an LVTTL level and the level of the second clock signal is a PECL level. 12. The apparatus ( 100 ) according to any one of claims 3 to 11, wherein the means ( 118 ) for converting the level of the first clock signal to the level of the second clock signal further generates a logically negated second clock signal. 13. The device ( 100 ) according to any one of claims 5 to 10, wherein the phase locked loop ( 130 ) of the device ( 124 ) for adapting the buffer mode to the register mode and / or the device ( 116 ) for adapting the timing of the first clock signal to the timing of the second clock signal has a line with a certain length and a capacitor which is connected from the line to ground. 14. The device ( 100 ) according to one of the preceding claims, in which the first circuit board ( 102 ) has a main circuit board of a personal computer. 15. The device ( 100 ) according to one of the preceding claims, in which the first circuit board ( 102 ) has a circuit board for testing the second memory module ( 104 ). 16. The device ( 100 ) according to one of the preceding claims, in which the second circuit board has a main board of a special purpose computer. 17. The device ( 100 ) according to one of the preceding claims, comprising a circuit board on which the device ( 114 ) for adapting the first clock signal to the second clock signal, the device ( 124 ) for adapting the buffer mode to the registers Operating mode and the device ( 138 ) for adapting the second data bus width to the first data bus width are arranged.