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DE10083287T1 - Double differential comparator and programmable analog block architecture to use the same - Google Patents

Double differential comparator and programmable analog block architecture to use the same

Info

Publication number
DE10083287T1
DE10083287T1 DE10083287T DE10083287T DE10083287T1 DE 10083287 T1 DE10083287 T1 DE 10083287T1 DE 10083287 T DE10083287 T DE 10083287T DE 10083287 T DE10083287 T DE 10083287T DE 10083287 T1 DE10083287 T1 DE 10083287T1
Authority
DE
Germany
Prior art keywords
same
differential comparator
analog block
programmable analog
double differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10083287T
Other languages
German (de)
Inventor
James L Gorecki
William G Gazeley
Yaohua Yang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Publication of DE10083287T1 publication Critical patent/DE10083287T1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/06—Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
DE10083287T 1999-09-22 2000-09-22 Double differential comparator and programmable analog block architecture to use the same Ceased DE10083287T1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15551299P 1999-09-22 1999-09-22
PCT/US2000/026180 WO2001022344A1 (en) 1999-09-22 2000-09-22 Double differential comparator and programmable analog block architecture using same

Publications (1)

Publication Number Publication Date
DE10083287T1 true DE10083287T1 (en) 2002-03-07

Family

ID=22555747

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10083287T Ceased DE10083287T1 (en) 1999-09-22 2000-09-22 Double differential comparator and programmable analog block architecture to use the same

Country Status (4)

Country Link
AU (1) AU7711400A (en)
DE (1) DE10083287T1 (en)
GB (1) GB2358747B (en)
WO (1) WO2001022344A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6982582B1 (en) 2003-06-23 2006-01-03 Marvell International Ltd. Simplified comparator with digitally controllable hysteresis and bandwidth
EP3866342A1 (en) * 2020-02-14 2021-08-18 Imec VZW Low-power consumption comparator and method for comparison

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9204434D0 (en) * 1992-02-27 1992-04-15 Sec Dep For The Defence Differential amplifier
US5574678A (en) * 1995-03-01 1996-11-12 Lattice Semiconductor Corp. Continuous time programmable analog block architecture
US5525920A (en) * 1995-05-01 1996-06-11 Motorola, Inc. Comparator circuit and method thereof
US5912567A (en) * 1997-10-22 1999-06-15 Sun Microsystems, Inc. Dual differential comparator with weak equalization and narrow metastability region

Also Published As

Publication number Publication date
WO2001022344A1 (en) 2001-03-29
GB2358747A (en) 2001-08-01
GB0112006D0 (en) 2001-07-11
AU7711400A (en) 2001-04-24
GB2358747B (en) 2004-06-09

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8131 Rejection