DE10062123C1 - Reference current source for memory cell read-out uses sub-groups of parallel transistors connected to common switches coupled together on their output side - Google Patents

Abstract

The reference current source has a number of parallel transistors (15) with their control electrodes coupled to a common voltage source. The transistors are combined into sub-groups (12.0,12.1,12.2,12.3) each connected to a common switch (22), the outputs of all switches connected together. All of the latter switches can be provided by a binary switching device, controlled by a dataword with a bit length corresponding to the number of switches. An Independent claim for a memory element provided with a reference current source is also included.

Description

The invention relates to a reference current source for the loading tuning the memory content of memory cells using Current measurement according to the preamble of claim 1. Ins particular, the invention relates to EPROM or EEPROM memory cells.

In the field of memory devices have been around for a long time erasable, programmable read-only memories, such as EPROMs (Erasable Programmable ROMs) and EEPROMs (Electrically Erasable Programmable ROMs). With this fixed value The programmable elements are saved by MOS Transistors with floating, i.e. H. electrically insulated Polysilicon gate formed by high field strengths the tunnel current flowing through a thin oxide layer is loaded. In the programming process, a becomes relative high gate voltage applied, while during the reading process lower, only above the threshold voltage of the MOS Transistors lying reading voltage is applied. With usual, EEPROM memory components in use this reading voltage typically at 2.4 V. The memory the EEPROM cell is read by a current evaluation sen, d. H. it becomes the at the applied gate voltage of 2.4 V flowing transistor current rated. This happens because that the transistor current the positive input of a Stromkom parators is fed during the negative input Reference current is supplied. With such a memory structure ren, whose cells are thus evaluated by means of current evaluation reference current sources are necessary.

With typical EEPROM memory components that use a Memory content "1" was programmed, the current is of the read transistor current in the order of 20 µA with an applied gate voltage of 2.4 V. The current  a corresponding transistor current at Speicherzel len with the memory content "0", however, is at this gate voltage zero. However, such memory cells have a certain degradation behavior over time. This is expressed in that the read current of the memory cells with memory content "1" decreases over time in its current strength takes, while memory cells programmed with "0" one of 0 assuming different and steadily increasing current values men. During test runs of the memory components, a Fixed reference current with one in the example above Current of 10 µA can be set. The current comparator then delivers a digital output signal corresponding to 0 or 1, depending on whether the transistor current supplied is above or is below this reference current. However, it is already possible instead of this preset reference current with Reference current sources enter certain specific current values to be used to read the memory cell under stricter conditions can be made possible. To this Faulty memory cells can be ascertained and if necessary, corrected by redundancy memory cells the.

This requires that the reference current source be within one beforehand according to the technological requirements sufficient reference current band in discrete current steps is adjustable. For reference current sources according to the state of the Technology uses a number of UV-programmed refes for this reference cells used. These have a given gate voltage a current strength specified by the technology. she are parallel to each other, possibly by means of electricity apply, interconnected. But it is necessary according to the Number of desired current values (margins) to be set a corresponding number of transmission gates or current spikes gels to use. The conventional reference current sources are therefore relatively complex due to the circuit and also complicated to control.  

From the U.S. 6 072 724 A is a reference current source for EEPROM sense amplifier known, in which different Stromwer te can be selected in which one of several sour EEPROM transistors connected in parallel with ver bound control gates with the help of a switching arrangement Sense amplifier is connected. With this reference current source However, the gradation of the individual current values is not yet optimally solved.

It is accordingly an object of the present invention, a Re to specify the reference current source of the type described, the simpl is constructed and controlled or programmed more easily can be.

This task is carried out with the characteristic features of Pa claim 1 solved. Advantageous further developments are in specified in the subclaims.

An essential idea of the present invention is in that the reference current source ge a plurality in parallel switched transistors, especially EPROM or EEPROM Has memory transistors, the control electrodes with egg ner common voltage source are connected, the A plurality of transistors in sub-groups of transistors is divided, each one or more transistors included, the outputs with a common switch ver are bound, and the outputs of the switches ver are bound. By activating these switches you can optionally different sub-groups of transistors be switched off.

The number of transistors in the subgroups is preferably a power of 2. So if there are M subgroups, the number of transistors in the subgroups is 2 ^N-1 with N = 1,. , , M. A further sub-group consisting of a single cell or a single transistor can also be added to this arrangement. The entirety of the individual switches can be formed by a binary switch which can be controlled by a data word whose bit length corresponds to the number of switches. Each bit position thus corresponds to a switch. If the bit position of the bit word contains "0", the corresponding switch should not be closed. If, on the other hand, the bit position contains a "1", the corresponding switch should be closed and the corresponding subgroup of transistors or reference cells should be connected. The individual switches which can be controlled in this way can be formed, for example, by transmission gates.

A current divider is preferably arranged downstream of the arrangement, by means of which the current flowing through the closed switches and summed up is divided by a factor D _F.

The individual transistors can be provided by reference cells EEPROM memory cell array can be formed so that the Refe limit current source together with the EPROM or EEPROM Memory device arranged on a common substrate is. The transistors of the reference current source are thus formed by EPROM or EEPROM memory transistors. It can also be provided that the reference current source at least Mostly certain circuit blocks of memory construction elements such as (high) voltage sources, sense amplifiers or sequential control circuits used.

The following is an embodiment of the invention hand of the drawing figures explained in more detail.

Show it:

Fig. 1 is a block diagram of an embodiment of egg ner reference current source according to the invention;

Fig. 2 shows an embodiment of a circuit according to the block diagram of Fig. 1;

Fig. 3 with the reference current source according to the invention an adjustable current values (A: simply linear; B: Gefen stert linear).

Fig. 1 is a block diagram showing an embodiment of an inventive reference current source. This has a reference cell array 10 , which is essentially made up of a number of N + 1 transistors. In the present case, the reference current source according to the invention is intended to serve to provide an adjustable reference current in order to evaluate the current read from an EEPROM memory cell with the aid of a current comparator. The reference current source is thus advantageously arranged together with the EEPROM memory on a substrate. It is therefore technologically advantageous if the transistors 15 of the reference cell array 10, like the memory transistors of the memory cell array, are designed as EEPROM memory transistors, as shown. This also opens up the possibility of programming the transistors to different current values, which additionally increases the variety of setting options for the reference current. The Transisto ren 15 are connected in parallel to each other, and a common voltage U _{0 is} applied to their gate electrode. As will be explained later, the transistors 15 are summarized in terms of circuit technology in sub-groups. The EEPROM memory transistors 15 can be constructed identically, so that they deliver currents of the same current strengths at the same gate voltage U ₀ (I ₀ = I ₁ ,..., I _N ).

The individual streams brought together from these subgroups are fed to a binary switch 20 , which is constructed from a number of individual switches 22 corresponding to the number of subgroups M + 1. The control of this binary switch 20 takes place via an M = log (N) / log (2) / bit long data word. The individual bits in the data word are hereinafter referred to as b ₀ ,. , ., b _m denotes, where b _{0 represents} the least significant bit or the so-called "offset" bit. The switches 22 can each assume the two positions "open" or "closed", for example the control with a "1" on the corresponding bit position closes the switch, while the control with "0" keeps the switch open. The switches 22 can be formed, for example, by trans mission gates.

As already indicated in Fig. 1, individual EEPROM memory transistors 15 are connected together in groups, and the current flowing through them is bundled and fed to a common switch 22 . The current I _2,. , ., I ₃ thus denotes the summed current I ₂ + I _{3 of} the corresponding memory transistors 15 . This is illustrated using a specific embodiment of FIG. 2.

Following the binary switch 20 , the lines coming from the individual switches 22 are brought together and the corresponding currents from the transistor subgroups are added up. These can then be fed to a current divider 30 , in which, for example, a possibly necessary current division can be carried out by a factor D _F by means of a downstream current mirror. The reference current I _REF thus obtained can then be supplied to the current comparator for comparison with a memory cell current to be evaluated.

In FIG. 2 is a concrete embodiment of a he inventive reference current source is shown in accordance with the block diagram of FIG. 1. In this, the memory transistors 15 are each grouped into subgroups 12.0 , 12.1 , 12.2 and 12.3 . The first two sub-groups 12.0 and 12.1 each have a single memory transistor 15, while the sub-group is made up of two memory transistors 15 12.2 12.3, and the subgroup of four chertransistoren SpeI composed 15th The memory transistors 15 are connected to a current source at their inputs. The reference current source thus has a number M = 3 sub-groups 12.1 , 12.2 and 12.3 , in which memory transistors with a number 2 ^n-1 with n = 1,. , ., M are interconnected. A further subgroup 12.0 with a single transistor 15 is added to this arrangement. This further subgroup can optionally also be omitted. If desired, the arrangement can also be expanded to include further subgroups, the number of memory transistors of which are correspondingly higher powers of 2.

The reference current I _REF is obtained according to Figure 2 by the fol lowing expression.:

As can be seen from this formula, there is complete freedom in the choice of the individual cell currents I ₀ to I _N and in the setting of the bits b ₀ to b _M. In this way, almost any reference current values and courses of reference current values can be set.

Finally, FIG. 3 shows various curves of reference current values obtained with a reference current source according to the invention as a function of the numerical value b of the data word supplied to the binary switch.

Referring to FIG. 3A, a reference current source with N = 16 was chertransistoren SpeI used, which according to FIG. Were combined into sub-groups 2. The currents I ₀ ,. , ., I _N-1 showed currents of 20 µA, while the current divider 30 worked with a division factor D _F = 8.

According to the Fig. 3B, however, a windowed linear Ver scored run. The number of transistors was also 16. In this case, however, the transistors were designed such that they had different forward currents when the voltage U ₀ = 2.4 V was applied. Specifically, I was ₀ . , ., I ₃ = 10 µA, I ₄ ,. , , I ₇ = 30 µA and I ₈ ,. , ., I ₁₅ = 20 µA. The current divider 30 had a division factor D _F = 8. This example shows the advantage of the programmability of the memory transistors 15 to different currents in the pass band for a given bias.

Claims (8)

1. Reference current source for determining the memory content of memory cells, in particular EPROM or EEPROM memory cells, by means of current measurement or current evaluation
a plurality of transistors ( 15 ) connected in parallel, in particular EPROM or EEPROM memory transistors, the control electrodes of which are connected to a common voltage source, and
whose inputs are connected to a power source,
marked by
a number of sub-groups ( 12.0 , 12.1 , 12.2 , 12.3 ) of transistors ( 15 ), each containing one or more transistors ( 15 ), the outputs of which are connected to a common switch ( 22 ) within a sub-group, and
the outputs of the switches ( 22 ) are connected to one another. 2. Reference current source according to claim 1, characterized in that M subgroups ( 12.1 , 12.2 , 12.3 ) are present, the number of transistors ( 15 ) in the subgroups 2 ^n-1 with n = 1,. , ., M is. 3. Reference current source according to claim 2, characterized by a further sub-group ( 12.0 ), consisting of an individual transistor ( 15 ). 4. Reference current source according to one of claims 1 to 3, characterized in that the entirety of the switches ( 22 ) is formed by a binary switch ter ( 20 ) which can be controlled by a data word whose bit length corresponds to the number of switches ( 22 ) , 5. Reference current source according to one of the preceding claims, characterized by a switch ( 22 ) downstream current divider ( 30 ) through which the total current flowing through the closed switch ( 22 ) is divided by a factor (D _F ). 6. Reference current source according to one of the preceding claims, characterized in that the switches ( 22 ) are formed by transmission gates. 7. Memory component such as EPROM or EEPROM memory with a reference current source according to one of the preceding An say, which with the memory cells of the EPROM / EEPROM Storage is arranged on a common substrate. 8. Memory device according to claim 7, characterized in that the reference current source is at least partially circuitry blocks of memory, such as voltage sources, sense amplifiers or sequencing circuits used.