DE10061243A1 - Data propagation time determination method for databus in semiconductor memory has time interval between transfer of data to output buffer and transfer to output altered in dependence on data comparison - Google Patents

Abstract

The data propagatiom time determination method has a signal sequence supplied to the semiconductor memory, for transfer of test data written into at least one memory cell to an output buffer via the databus, with subsequent transfer of the data in the output buffer to the memory output and comparison of the output data with the original test data. The process is repeated with the interval between transfer of the test data to the buffer and transfer to the memory output extended until no fault is indicated between the compared data. An Independent claim for a device for determining the propagation time of data along a databus in a semiconductor memory is also included.

Description

The invention relates to a method and an apparatus for Determine the runtime of data on a data bus in one Semiconductor memory.

Semiconductor memories basically consist of memory cells, which are organized in such a way that every cell can be accessed from the outside le exists. The memory cells of the semiconductor memory are generally designed so that 1-bit information per cell mation is stored, with each cell addressed individually is cash.

As a semiconductor memory for fast data exchange in particular read / write memory (RAM) used in de the data can be read in and out as often as required. The memory cells in RAM are a square matrix arranged, being used to select a particular memory cell the corresponding address from a column or row co the memory is decoded. Except the addresses a RAM generally has a data input and a data output with a data output buffer as well a read / write switch and possibly a chip selection conclusion that a multiplex operation of several RAMs enables a common data line.

Read access to a RAM is simplified fol in the following way: First the read / write switch is set to Reading set. Then the row address is read out one sent to the memory cell. At the same time, a so-called RAS Line activated, which ensures that the row address is taken over by the line decoder. According to a given The column address is then sent and a so-called CAS line enabled, which ensures that the column address  is taken over by the column decoder. After this The addressing process becomes the content of the addressed memory memory cell in the data output buffer of the RAM and then created at the data output. The time that the RAM memory needed until the data after activating the CAS line is written into the data output buffer as CAS latency. This CAS latency is therefore a Measure of the internal runtime of the data in RAM and is in generally between 40 ns and 60 ns for the first read access.

RAMs are basically of two different types manufactured. With static RAMs (SRAM) the information is stored in the memory cell, as long as the operating voltage is present in the RAM memory. With dynamic RAMs (DRAM) there must be periodically refreshed against the memory content. DRAMs have the advantage over SRAMs that the same power consumption and the same costs significantly higher Have storage capacities realized here. As a storage type DRAMs have so-called synchronous DRAM memories (SDRAM) enforced, in which all processes synchronized with the Sy run clock cycle and always be one or more clock periods lay. Has the system clock with which the SDRAM module operates will, e.g. B. a frequency of 100 MHz, this corresponds to one Clock period of 10 ns. Takes an action on this SDRAM 8 ns, a clock cycle is required for this action the action needs 11 ns, two clock cycles klen be estimated for the execution of the action.

An essential time when specifying such SDRAM memory is the above-mentioned CAS latency Classification always specifies the number of clock cycles from activating the CAS line to writing of the data pass into the data output buffer.

The speed sorting of the SDRAM modules according to their CAS latency is experienced as part of conventional chip testers  performed. These chip test procedures are in the we significant in front-end test procedures and back-end test ver drive divided. The difference between the two test runs fen is that during the frontend check the tests be performed while the individual memory chips are still present undivided on the semiconductor wafer. In the backend In contrast, the individual chips according to Zersä will be tested tested separately against the wafer.

The front-end test procedure has the particular task of: to perform a first function test of the chips on the wafer to find faulty circuits. This broken th circuits are then part of a subsequent Troubleshooting process through redundant, already on the Chip provided circuits replaced. The frontend check can be done with a simple test setup because the required test data is already far at the clock rate below the clock rate normally used during operation of the SDRAM modules can be processed.

In the downstream back-end test procedure, a complete functional test of each individual chip under Using the system clock speed at which the SDRAM module then to be operated. First, the Basic functions of the SDRAM module tested and then the building block aged to filter out early failures. To These two test procedures are then based on the required Chen readout time of test data while performing the read operation with the system clock rate the CAS latency that the in internal runtime of the data in the SDRAM module indicates, determined and classified.

The backend test procedure does because of the need a test data processing under SDRAMs operating conditions a large amount of hardware is required and is therefore only feasible with a large expenditure of time and money. at however, it was the previously known chip test method  always possible, the CAS latency check of the SDRAM module in the As part of such a complex backend test procedure perform.

The object of the present invention is therefore a Ver drive and a device for determining the internal run time of data in a semiconductor memory, in particular egg nem SDRAM that is easy and inexpensive can always be carried out.

This object is achieved by a method according to claim 1 and solved a device according to claim 6. Preferred execution Forms are specified in the dependent claims.

According to the invention, to determine the internal run time of data in a semiconductor memory, in particular egg nem SDRAM module, in which the memory cells with a data buffer memory are connected to a data output Test date written in at least one memory cell, then applied a signal sequence to start with a first signal a transfer of the stored test date over the data bus into the buffer memory and with a second, at times a predetermined time period after the signal of the date written in the buffer memory at the output effect, the date at the exit with the test date is compared to determine an error. If If an error is found in the comparison, the before steps with another in a storage cell le registered test date and one around a given Value extended period of time for the second signal so long repeated until the comparison no longer reveals where at as the internal term of the data, d. H. as CAS latency last period of time applied between the first and the second signal is held. If at the first ver If no error is found at the same time, the steps with another in a memory cell registered test date and one around a given  Repeat the value of the shortened period of time until the ver immediately between the date at the exit and the Test date an error is found, being as internal Term, d. H. as CAS latency, the penultimate applied Time between the first and the second signal fixed is held.

With the inventive technique for determining an inter NEN data runtime in semiconductor memory, especially in egg a SDRAM module, it is particularly easy to implement speed sorting of the semiconductor memory perform, which requires only a small amount of hardware changed. The measuring method can therefore already be used in the framework the front-end test of the semiconductor device at still zero divided semiconductor wafer can be performed. In particular is it neither for the speed test according to the invention necessary to change the chip design nor modifications the well-known test hardware for front-end test methods respectively. The CAS latency possible according to the invention testing as part of the front-end test processes the expensive back-end test procedure is essential shorten and make it cheaper.

According to a preferred embodiment, the first Step parallel a plurality of test data into the memory cells of the semiconductor memory are written, which then after each other to determine the internal data runtime on the da tenbus can be used in semiconductor memory. hereby the test time required for CAS latency significantly reduce speed determination.

The invention will become more apparent from the accompanying drawings explained. Show it:

Fig. 1 timing diagrams for a read access in a syn-synchronous dynamic read / write memory with random access memory (SDRAM), wherein Fig. 1A is a read operation for a CAS latency of 3 and Fig. 1B is a read operation for a CAS latency of 2 represent

Fig. 2 is a schematic representation of the test setup for determining the CAS latency of a wafer with SDRAM chips, and

Fig. 3 is a schematic representation of the test process.

As an embodiment of the runtime determin invention In the following, the determination of the CAS latency in egg synchronous, dynamic read / write memory with choice free access SDRAM explained. The inventive method In principle, however, can also be used to determine the internal data runtime in all other known semiconductors save, in particular use all RAM memory types.

An SDRAM is a semiconductor memory, where the signal input and output on the memory chip with a clock is synchronized. This clock is in the generally with the clock of a central processing unit (CPU) coordinates so that the timings in the memory chip and the time sequences of the CPU are coordinated. With This memory design can be a particularly high Da transfer rate between the CPU and the semiconductor memory to reach.

SDRAMs are generally square-shaped memory cells trix designed, the individual memory cells over Zei lenlinien, the so-called. Word lines (WL), and column lines gene, the so-called bit lines (BL), are addressable. To the end selection of a specific memory cell is the address created se this memory cell from a row or column code rer decoded. To save on address connections, the The address is generally sent to the Deco in two steps dier created, first the row address and then the Column address is sent. Except for the address inputs  the SDRAM still has a data input and a data output as well as a read / write switch and possibly a chip off Dial-up connection to multiplex the SDRAM with others Allow storage over a common data line.

For writing or reading out the data in the individual Memory cells, the bit lines are preferably used, the data read out via the bit lines before Creation at the data output in a data output buffer between cached.

Read access to the SDRAM is organized in this way folds as follows: The read / write switchover of the SDRAM is initially set to read. Then the address of the Memory cell placed on the address bus. A storage con troll unit decodes the specified address and triggers one Access cycle. The line address is first ge sends. After a waiting period, which ensures that the time memory address is stable, activates the memory control an associated RAS line. Then the lines address taken from the memory and the corresponding word line of the associated memory cell activated. Subsequently the column address is sent. After another wait time, which ensures that the column address is stable the memory control unit activates an associated one CAS line. The column address is then over from the memory take and the corresponding bit line of the associated memory cell activated. Then on this bit line addressed memory content in the data output buffer read. The memory control unit then directs the Contents of the data output buffer in the correct order on the data output and signals a ready signal, wor then read the data from the requested device or CPU become. From activating the CAS line to writing the Data in the data output buffer pauses time, the so-called CAS latency. With SDRAMs, this CAS latency specified as the number of clock cycles by the isochronous  CAS line activation up to a possible isochronous Reading of the data from the data output buffer elapses.

Fig. 1 shows an example of the timing of a read cycle in an SDRAM, which is operated with a clock frequency of 100 MHz be. This clock frequency corresponds to a period of 10 ns, which thus indicates the minimum time reserved for a process in SDRAM. FIG. 1A shows a read cycle with a CAS latency of 3 and FIG. 1B shows a read cycle with a CAS latency of 2. As shown in Fig. 1A and Fig. 1B, is applied in synchronism with the row address ZA the rising clock edge of a first clock cycle C1 and the corresponding RAS line is set to 1. After a waiting time of three clock cycles, the column address SA is then output on the rising clock edge of clock signal C4 and the corresponding CAS line is set to 1. After the activation of the CAS line, three further clock cycles pass in the exemplary embodiment shown in FIG. 1A until the data of the addressed memory cell are taken over into the data output buffer with the rising clock edge of the clock signal C7. In the exemplary embodiment shown in FIG. 1B, on the other hand, the data appear after two clock cycles, ie with a rising clock edge of clock signal C6 in the data output buffer.

In order to keep the memory access time short, the SDRAMs are preferably read in burst mode. The address of a first memory cell is transferred and stored in the address buffer of the SDRAM. Is to read out the next three memory cells then only indexed as shown in FIG. 1A and FIG. 1B, so that no re-wide dead time occurs here.

In addition to the operating mode shown in Fig. 1, in which all processes in the SDRAM are carried out with a rising clock edge, there is also the possibility with a faster SDRAM variant to carry out the processes on both the rising and the falling clock edge of the clock signal, where which essentially doubles the data transfer rate.

According to the invention, the CAS latency in SDRAM is preferably determined using a test system, as shown in FIG. 2. This test system 1 is preferably part of a front-end test system, and the components of the test system necessary for CAS latency speed sorting can then also be used for other test processes as part of the front-end test method. In the front-end test, as shown in FIG. 2, a semiconductor wafer 3 , on which the memory chips 21 , in the illustrated embodiment the SDRAMs, are formed, is still undivided. For the test, who contacted the pins 22 of these chips with a needle card 3 , which is only indicated in FIG. 3. Several pins can be contacted in parallel by the needle card. The needle card 3 is in turn connected to the test system 1 . The test system 1 has a data output unit 11 and a data input unit 12 , which are included on the needles 31 , 32 of the needle card 3 , which contact the data pins of the memory chips 21 . Furthermore, a clock signal generator 13 is provided in the test system 1 , with which a variable system clock can be generated. This clock signal generator 13 is connected to the needles 33 of the needle card 3 , which contact the clock signal pins of the memory chips 21 . The test system 1 also has an evaluation unit 14 which controls the data signal input unit 11 , the data output unit 12 and the clock signal generator 13 .

The test system 1 is used as part of the front-end test to carry out a first function test of the memory chips 21 on the wafer 3 and in particular to determine defective circuits on the memory chips. These defective circuits are then replaced by redundant circuits already provided for this purpose on the memory chips 21 in the course of subsequent troubleshooting processes. The signals necessary for these tests are output via the data output unit 11 on the memory chips, the memory chips in the front-end test by the clock generator 13 in principle with a clock rate well below the clock rate normally used when operating the memory chips, ie, e.g. B. at a frequency of 30 MHz instead of the operating frequency of 100 MHz, operated. The data generated during the functional test of individual memory chips 21 on the basis of the signals input are received by the test system 1 via the data input unit 12 and processed by the evaluation unit 14 .

The determination of the CAS latency as a measure of the column access times in the memory chips during the reading process can be carried out with the test system shown in FIG. 2. The CAS latency test process is shown in more detail in FIG. 3 for a memory cell 23 .

In the test process for determining the CAS latency of the memory chip 21 , test data are written into the memory cell 23 of the memory chip 21 via the data output unit 11 of the test system 1 . The test data input can be carried out in parallel for a large number of memory cells. However, there is also the option of successively writing the test data required for each test step into the memory cells. The entire test can also be run in parallel for a variety of memory chips.

To determine the CAS latency, a read cycle is triggered by the evaluation unit 14 . The clock frequency at which the memory chip is operated during this read cycle is predetermined by the clock signal generator 13 , the clock period preferably being set to two or three times the system clock period with which the memory chip is conventionally operated. The clock period thus corresponds approximately to the time span of a CAS latency 2 or a CAS latency 3 of the memory chip in conventional operation. The address of the memory cell 23 to be read, in which the test date is written, is applied to the memory chip by the evaluation unit 14 . A memory control unit (not shown) on the chip decodes the specified address and then triggers an access cycle, the row address of the memory cell 23 being applied together with the RAS signal with an increasing first clock frequency (not shown). With the next clock edge, the column address with the CAS signal is created by the memory control unit, so that the test date can then be read out from the memory cell 23 via the corresponding bit line and transferred to a data buffer memory 24 . From the data buffer memory 24 , the temporarily stored test data is then, in turn, applied to a data output 25 of the chip with the subsequent rising clock edge and read from there by the data input unit 12 of the test system 1 .

The test date originally written into the memory cell 23 via the test system 1 is then compared by the evaluation unit 14 with the date read via the data input unit 12 . If there is a match, the evaluation unit 14 triggers a new test read cycle, the evaluation unit 14 setting the clock signal generator 13 to a clock period shortened by a predetermined period of time. This shortened clock cycle is shown in dashed lines in Fig. 3 Darge. If the written test date also coincides with the date read from the memory cell during this new test run, a new test read cycle is carried out with a clock period shortened again by the predetermined time period. The test run is then repeated with shortened clock periods until the date read from the memory chip no longer matches the registered test date. The evaluation unit 14 of the test system 1 then determines the cycle period in the previous test step as the CAS latency, in which the test date still coincided with the read out date.

If, on the other hand, the read-out date does not match the written test date during the first test read cycle, the clock signal generator 13 is set by the evaluation unit 14 for the next test read cycle in such a way that a read cycle is carried out with a clock period increased by the predetermined time period, such as this is also shown in dashed lines in FIG. 3. The clock period is then increased step by step until the written test date matches the date read out from the memory cell 23 . The evaluation unit 14 then accepts this last clock period as the CAS latency.

The method according to the invention can be used in parallel for a lot number of memory chips or memory cells in parallel leads. At the same time, the test time continues to increase shorten the possibility in a first step a lot number of different test data in different memory to write memory cells of the memory chip to be tested and then a read for the successive test run process for the various memory cells.

The measured internal data runtime during the reading process for the individual SDRAM memory chips can then be inserted into the corresponding CAS Latency Reversed Based on Operating Clock Frequency be counted. Alternatively, there is also the option of runtime measured in the front-end test procedure with at Back-end test procedures for exemplary measured CAS latencies correlate.

The invention enables the runtime of Da to be determined ten on a data bus in a semiconductor memory, in particular the CAS latency for SDRAM modules as part of the frontend Procedure so that test time and test costs at the backend Checking this speed sorting conventionally is carried out, can be saved. Farther can the speed sorting according to the invention in the frame the conventional frontend test without changing the  Test hardware are running. To carry out the Ge Speed tests are also not a modification on the chip design necessary.

The in the above description, the claims and the Drawings disclosed features of the invention can both individually as well as in any combination for the entanglement chung of the invention in its various embodiments be essential.

Claims (7)

1. A method for determining the transit time of data on a data bus in a semiconductor memory which connects the memory cells in the semiconductor memory to a data buffer memory at an output, a test date being written into at least one memory cell in the semiconductor memory, with the method steps:

• a) Applying a signal sequence to the semiconductor memory in order to transmit the test data stored in the memory cell via the data bus into the data buffer memory with a first signal and with a second signal shifted in time by a predetermined period of time to apply the date written in the data buffer memory on Effect output;
• b) comparing the date at the exit with the registered test date in order to determine an error;
• c) if an error is found in step b), repeating steps a) and b) with a further test date written in a memory cell and a time period for the second signal extended by a predetermined value until step (b ) no error is recorded, the last period of time between the first and the second signal being determined as the running time, or
• d) if no error is found in step b), repeat steps a) and b) with a further test date written into a memory cell and a time period for the second signal shortened by a predetermined value until step b) An error is determined where the penultimate time period between the first and the second signal is recorded as the runtime.

2. The method of claim 1, wherein a plurality of test data entered into the memory cells in the semiconductor memory are written one after the other to determine the term  of data on the data bus used in the semiconductor memory become. 3. The method according to claim 1 or 2, wherein the processes in Semiconductor memory executed synchronously with a clock signal and the determined duration of data on the Da correct with the corresponding number of clock periods is determined by the access time of the semiconductor memory for classify a read. 4. The method according to any one of claims 1 to 3, wherein the first and second signal consecutive clock edges Signals are and the period between the first and the second signal is determined by the clock period. 5. The method according to any one of claims 1 to 4, wherein the Runtime as part of a front-end test of semiconductor memory chern is determined. 6. Device for determining the transit time of data on a data bus in a semiconductor memory ( 21 ) which connects the memory cells ( 23 ) in the semiconductor memory to a data buffer memory ( 24 ) at an output ( 25 )
a device ( 11 ) for reading a test data into at least one memory cell in the semiconductor memory,
a device ( 13 ) for applying a control signal sequence to the semiconductor memory in order to transmit, with a first signal, a transfer of the test data stored in the memory cell ( 23 ) via the data bus into the data buffer memory and with a second signal shifted in time by a predetermined period of time effecting the creation of a date written in the data buffer memory ( 24 ) at the output ( 25 ) of the semiconductor memory, and
an evaluation device ( 14 ) for comparing the semiconductor memory of the test date read in with the data present at the output in order to determine an error and for controlling the device ( 13 ) for applying the control signal sequence so that, if an error is determined, a new test read cycle is triggered with a control signal sequence in which the second signal is applied with a time period shortened by a predetermined value, and, if no error is found, a new test read cycle is triggered with a control signal sequence in which the second signal is extended with a predetermined value Period is created. 7. The device according to claim 6, which is part of a front end Testers of semiconductor memories on a semiconductor wafer is.