DE10052152C1 - Analogue/digital conversion method e.g. for machine tool position sensor signals uses comparison method for correction of digital output value dependent on analogue input signal - Google Patents

Abstract

A method for converting an analog input signal (a) into a sequence of digital output values (qn) uses the formation of a first differential value (e) between the current output value and the analog input signal (a). The method also provides for a check to determine whether the amount of the first differential value (e) exceeds a predetermined amount (S). Should the amount of the first differential value (e) exceed the predetermined amount, the method provides that the digital output value (qn) is re-adjusted using a certain adjustment value. Should the amount of the first differential value (e) not exceed the predetermined amount, the method provides that a second differential value (d) between the first difference (e) and an integral value (S) consisting of the sum of first differential values (e) occurring since the checking stage showed throughout that the amount of the first differential value (e) does not exceed the predetermined amount is formed; and that the second differential value (d) is compared with a predetermined threshold value and the digital output value (qn) is incremented or decremented according to the result of this comparison.

Description

The present invention relates to the conversion of egg analog input signal into digital output values and especially on the analog / digital conversion of positions sensor signals when positioning machine tools.

For measuring a path or an angle of rotation α with mechani Arrangements or machines become linear differential transformers (LVDT = Linear Variable Differential Transfor mer) or rotary differential transformers (RVDT = Rotational Variable Differential Transformer), the encoder or resolver be called, or a special arrangement magnetoresisti ver resistors or Hall sensors are used. These sensors deliver two output signals that depend on the mechani position vary, so that the position from the signals is determinable.

FIG. 1a and FIG. 1c, for example, show two different arrangements for measuring the linear position, while Fig. 1b shows an arrangement for measuring an angle of rotation.

Fig. 1a shows an excitation coil 10 and two measuring coils 20 and 30 and a measurement object 40 with suitable Materialei properties, such as a suitable magnetic susceptibility between the excitation coil 10 on the egg NEN and the measuring coils 20 and 30 on the other Side is arranged, and is linearly movable along an axis 50 . The arrangement is designed such that a linear displacement of the measurement object 40 or the excitation coil 10 causes a change in the coupling ratios between the excitation coil 10 and the measurement coil 20 and between the excitation coil 10 and the measurement coil 30 . An excitation voltage on the excitation coil 10 therefore causes signals on the measuring coils 20 and 30 which are in quadrature with each other. The position of the measurement object 40 can be defined as an angle α, which determines the relationship between the two measurement signals, as will be explained in the following.

The arrangement shown in FIG. 1b corresponds to the arrangement shown in FIG. 1a except for the measurement object 40 . In this case, the measurement object is formed by a rotatable body 50 . By rotating the body 50 , as in the arrangement in Fig. 1a, the ratio between the measuring coils 20 and 30 detected in the measuring signals as a function of the angle of rotation α, whereby the angle of rotation α can be determined.

Fig. 1c shows an alternative to Fig. 1a arrangement with magnetoresistive sensors 60 and 70 , a magnetic scale 80 being used as a linearly displaceable measuring object. The magnetic scale 80 has two suitably aligned magnetic areas, each producing opposite magnetic fields at the location of the magnetoresistive sensors 60 and 70 , these areas in FIG. 1 c by four bar magnets 80 a, 80 b, 80 aligned in an alternating direction c and 80 d are shown. By moving the scale 80 ent along an axis 90 , the magnetic field at the location of the magnetoresistive sensors 60 and 70 and thus the elec trical resistance changes such that signals are measured at the sensors 60 and 70 , which are in quadrature to each other.

Consequently, the variation of these signals is characterized in that they are essentially quadrature with one another. Fig. 2 shows the relationship between the value α egg on the other hand and the measurement signals on the measuring coil 20 or the ma gnetoresistive sensor 60 (Usin) and on the measuring coil 30 or the magnetoresistive sensor 70 (Ucos) on the other hand in dependence on an excitation voltage U ₀ . From Figure two, the following relationships between the excitation voltage U ₀ , the measured value α, such as. B. the angle of rotation, and the measurement signals Usin and Ucos:

Usin = U ₀ sin (α)

Ucos = U ₀ cos (α)

Here U ₀ can be any DC or AC voltage and the general form of

have, wherein U _i amplitudes, ϕ _i the associated phases at time t = 0 and ω are the carrier frequency.

Since almost all controls and regulations of mechanical systems are increasingly implemented digitally, the analog output signals of the sensors must be digitized before they can be processed to control the machines. To determine a digital equivalence of the position Θ = α _dig , the ratio of Usin to Ucos must be evaluated, with the following relationship in general between the angle of rotation α and the measurement signals Usin and Ucos:

An evaluation of the measurement signals must therefore be independent of the variation in U ₀ . Several methods for digitizing the measured value α are known from the prior art. In systems with separate digitization, both measuring voltages Ucos and Usin are digitized separately, and the digital output value αdig is then digitally calculated.

Fig. 3 shows the block diagram of a device with separate digitization. The input signals Usin and Ucos are fed in at two channel inputs 100 and 110 , respectively. Both inputs 100 and 110 are connected to series-connected low-pass filters 120 and 130 and analog / digital converters 140 and 150 , which are connected in series. The low-pass filters 120 and 130 are the analog-to-digital converters 140 and 150 upstream to meet the Nyquist criterion when scanning within the converters 140 and 150 . The demodulation of the digitized signals generated in this way is carried out by means of a multiplication 160 or 170 with a carrier frequency signal fed in at an input 180 . The calculation of Θ by calculating the arctangent is done digitally in a computer block 190 . The low-pass filters 120 and 130 and the analog-digital converters 140 and 150 must consequently be designed for processing signals with a carrier frequency, which means an increased outlay. A digital filter 200 is connected behind block 190 to effect interference suppression.

All elements of the circuit shown in Fig. 3 are integrated monolithically or hybrid in a module. A disadvantage of this method is that the resolution and order duration cannot be set dynamically. In the event that a noise signal that is larger than the least significant bit is superimposed on the input signal, the resolution can be increased by Ni bits in the digital filter by averaging over 2 ^2Ni values. This is known as dithe ring and results in an increase in the resolution proportional to the root of the averaged time period. The theoretical physical limit for the measuring accuracy is characterized by a constant product of resolution and averaging time and lies above all at higher resolutions, far from the results of this method.

Other methods known in the art evaluate the Measuring signals after a post-processing with counter and ver different types of feedback. Implementers of this type are for example in the assemblies of the company Data Device Cooperation (DDC) with the business address 105 Bill Ba Place, Bohemia, New York 11716-2482, from Analog Devices INC. with the business address one signality way, poBox. 9196, Nor worth MA 02062-9196, the company NAI and the company iC-House used.

The tracking process is based on the tracking of the digital Value Θ using a control loop. The required, returned coupled error signal is through nonlinear analog scarf calculations.

Fig. 4 shows a conventional converter after the post-processing, which is produced by the company iC-House, with a sine / digital converter.

The converter of FIG. 4 comprises two inputs 200 and 210 , at which the demodulated signals A × sin (α) and A × cos (α) are present. The two inputs 200 and 210 are connected directly and via an inverter 220 and 230 , respectively, to two inputs of a switching device 240 . The switching device 240 receives segment control information at an input 245 , which will be explained in the following, and accordingly directs this information either the non-inverted or inverted input signal of the input 200 to the non-inverting input of a comparator 250 or either the non-inverted or inverted input signal of input 210 to a multiplier 260 . The output of the multiplier 260 is connected to the inverting input of the comparator 250 . The output of the comparator 250 is connected to an up / down counter 270 , which receives information about the resolution to be achieved or signals for controlling hysteresis effects and a clock signal via three inputs 280 , 290 and 295 . The output of the up / down counter 270 is connected to the converter output 300 and in a feedback loop to the input of a digital / analog converter 310 . The output of the digital / analog converter 310 is connected to an input of a calculation device 320 for calculating the tangent or the cotangent, the selection of the function on which the calculation is based being controlled via an input 330 by the segment control information. The output of the calculation device 320 is connected to a further input of the multiplier 260 .

The mode of operation of the converter from FIG. 4 will now be described. The digital conversion result or the current output value Θ is stored in the up / down counter 270 and is converted into an analog voltage via the digital / analog converter 310 . This is multiplied by one of the two output signals of the switching device 240 , the product being compared by the comparator 250 with the analog output signal. The output of the comparator 250 leads to the direction input of the counter 270 . The counting direction for each clock signal 295 is maintained by the counter until the output voltage of the digital / analog converter 310, which is proportional to the output value, corresponds to the value α of the input voltages.

In contrast to conventional analog / digital converters, the output value of the sine / digital converter is not proportional to the input voltage, but rather to its phase α. The phase is available at inputs 200 and 210 in the form of A × sin (α) and A × cos (α). The tangent function is formed from the initial value Θ in the feedback along the feedback loop, and the result is multiplied by cos (α). The end result is compared to sin (α). The following relationship is therefore obtained as a regulation for the regulation:

Asin (α) = Acos (α) tan (Θ)

Since the tangent function has pole positions and cannot be formed over a full period, a period is divided into eight segments. For certain segments, the input signals at inputs 200 and 210 are interchanged by the segment control, and the cotangent function is formed in the feedback instead of the tan function. The sine-digital converter runs automatically on the shortest path into the segment and has thus reached its operating point after a maximum of n / 2 clock cycles with a static input signal, where n corresponds to the resolution. The demodulation of possibly carried signals can be realized in the converter by carrier-synchronous control of the segment control.

A disadvantage of the converter described above is that the resolution is determined internally by the number of counting steps and cannot be changed dynamically by anyone who can. In addition, the converter shown in FIG. 4 never comes to rest, since the counter continuously counts up or down the least significant bit of the output value even with a constant input signal, which must be prevented by hysteresis control. For this purpose, an area is spanned on both sides of the counter value and checked within two clock periods whether the input signal is still within this area. The output frequency is therefore only half the clock frequency, and an additional circuit is necessary to prevent the fluctuation of the output value with an otherwise constant input signal.

In Fig. 5 the block diagram is shown of another conventional converter according to the tracking method. This ratiometric converter is used, for example, in the modules of the RDC-19200 series from DDC or AD2S44 from ANALOG DEVICES. As Fig. 5 shows, this converter comprises two inputs 400 and 410, against which the input signals Vsin and Vcos. The two inputs 400 and 410 are connected to a device 420 for sin / cos multiplication and addition. Device 420 outputs an alternating signal error ε to an output 430 and to an input of a phase-sensitive demodulator (PSD) 440 . The PSD also receives a signal at the carrier frequency via an input 450 . The PSD 440 outputs a DC signal error E to an output 460 and to the input of an integrator 470 . The integrator outputs an integrated error signal to an output 480 and to an input of a VCO 490 . The VCO 490 outputs clock signals clk and direction information to a counter 520 via two lines 500 and 510 . The counter 520 is connected to the digital output 530 of the converter and to a further input of the device 420 .

The operation of the converter of Fig. 5 will now be explained. First, the input signals at inputs 400 and 410 are multiplied by device 420 by sin (Θ) and cos (Θ), and the results are then subtracted from one another. After demodulation by the PSD 440 , an error signal E results which is proportional to (α - Θ) for small deviations from (α - Θ):

E = sin (α) cos (Θ) - cos (α) sin (Θ) = sin (α - Θ) ≈ α - Θ.

This signal E is integrated at least once, as a result of which a signal V (velocity) is obtained which is supposed to be proportional to the speed. Depending on the size and sign of V, the VCO controls the counter at the appropriate speed, forwards or backwards. By using the integrator, the conversion process is suppressed. The blocks are typically all integrated into a hybrid module or an IC (IC = Integrated Circuit), although connections 540 and 550 to the outputs 560 and 580 must be arranged outside the module so that the control properties can be influenced can.

A disadvantage of the circuit shown in Fig. 5 is that its behavior depends largely on the external structure and the Be circuit. In addition, the resolution is determined internally by the width of the counter word and can therefore not be changed dynamically during operation. In principle, it would be possible to adjust the resolution using a variable filter. For reasons of stability, however, the integration time of the analog integrator in practical use is longer than the averaging time of the digital filter. Shortening the digital integration time does not lead to higher dynamics with reduced resolution.

WO 93/22622 describes an interpolating converter, which is used in the AD598 module from ANALOG DEVICES becomes. This converter converts LVDT signals into PWM-encoded Di capital signals around. Instead of arctan (x) formation, only one Quotient formation carried out. This is done via the linea re multiplication of the input signals by the PWM signal. in the Principle, this converter is a single Bit-sigma-delta converter with special single-bit Feedback on the two input signals. This translator can only approximately evaluate resolver signals, since the Si modulation is not taken into account.

In those described above, in the state of the Technique known converter methods result in the following Problems:

The drives of modern machine tools are getting faster and faster and should always position more precisely. To get it ever increasing speeds (with resolvers) or process higher linear speeds with fixed resolution To be able to use the carrier frequency and the input band width of the evaluation circuits become ever larger. This is necessary a faster and faster regulation in the wake move or ever higher sampling rates of the analog / digital Converter with separate digitization, which in turn is high  Requirements for the subsequent control electronics that just a lot of the quickly generated position information can continue processing with great effort.

With a high bandwidth of loop control of a caster setter, the control system can also become slightly unstable. Especially multi-integrating systems that are characterized by small Static control deviations are in this Hin view vulnerable. This also affects the user of the Circuit out, since it becomes difficult to convert the converter module in to integrate a working system. In addition, the An due to electromagnetic interference from others Assemblies larger.

Thus, although it would be desirable to have the entire converter system Integrating the monolithic stem is the conventional method The procedure for this is either very high or even un possible.

Integration is involved in the ratiometric process for example the offset of the integrator, the PSD and the VCO, that lead to distortion or unstable behavior can, counter. In addition, the time constants of the VCO show ne high scatter, and the PSD causes interference and distortions. Another disadvantage is that the resolution of the multipliers used or the multipliers DACs depend and hardly dynamic in favor of speed is reducible. In addition, the counter always counts plus or mi only one step of the maximum resolution and thus sets the ma ximal speed da / dt fixed, consequently mostly the maximum conversion speed of the multiplying DAC cannot be fully exploited.  

In the aforementioned method of separate Di gitalization the problem arises with integration that the chip area requirement for "long" digital filters and the exact Arctan (x) calculation is large. It is also disadvantageous that the resolution depends on the resolution of the ADCs and mostly is firm.

EP 0158841 A1 describes an analog-to-digital converter, in which a first discriminator the input voltage with the off output voltage of a digital integrator compares th digital-to-analog converter and a forward or Count down the digital integrator by a minimum bit causes if the input voltage is more than about half of those corresponding to a least significant bit Voltage is lower or higher. To improve the after window discriminators are also planned, which a faster output signal feedback at rapid Allow fluctuations in the input voltage.

DE 195 40 106 C2 describes a control unit for an E electric motor with a position sensor with analog output signal. The position sensor is an analog-digital converter downstream, which in turn a computing circuit for investigation downstream of position values. It is a Kor rectification circuit provided to the time delay in loading correct the calculation of the position value.

EP 0169535 A2 describes an analog / digital converter, in which is a voltage generated by a built-in D / A converter is successively subtracted from an analog input signal, and the digital code of the built-in D / A converter as the di gitale output signal is derived if between  the voltage generated by the D / A converter and the analog input signal through a comparator mood is determined. The output signal of the comparator is fed back to overlay the subtracted result as well as to be used to convert the D / A converter Taxes.

UK 2242583 A describes a double reference angle ber / digital converter, in which in a DAW a cosine and Si nus encoder signal with an internal digital sine or cosi nus signal is multiplied, and the output signals one Error amplifier are supplied, which he an error signal testifies, which is digitized by a converter and by a digitized reference signal is demodulated by the encoder. The output signal is demodulated in the demodulator and ü Via a digital filter fed to a binary accumulator. The Accumulator output signal is first by a cosine Lookup table to be the cosine via a modulator generate signal for the DAW, and secondly by a Sine lookup table used to over another mo dulator to generate the sine input signal for the DAW. The Demudulator and the modulators are equipped with an internal digi talen reference synthesizer connected.

The object of the present invention is a Ver drive and an apparatus for converting an analog one input signal in a sequence of digital output values create so that the dynamic properties of the conversion are improved and still high for static input signals Resolutions can be achieved.  

This object is achieved by a method according to claim 1 and solved a device according to claim 9.

The inventive method for converting an analog Input signal in a sequence of digital output values comprises forming a first difference value between the current output value and the analog input signal. The The method also includes checking whether the amount of the first th difference value exceeds a predetermined amount, where, if the amount of the first difference value exceeds the previous agreed amount exceeds, the readjustment of the digital Output value using a certain control value is provided. If the amount of the first difference value forming does not exceed the predetermined amount a second difference value between the first difference and an integration value, which is the sum of the negated first difference values have existed since the review in the Step of reviewing consistently revealed that the amount of the first difference value does not exceed the predetermined amount  steps, comparing the second difference value with egg predetermined threshold and incrementing or Decrementing the digital output value depending on the Result of the comparison provided.

The inventive device for converting an analog Input signal in a sequence of digital output values comprises means for forming a first differential value tes between the current digital output value and the ana log input signal and a device for checking whether the amount of the first difference value is a predetermined Be load exceeds. It is a facility for readjusting the digital output value using a predetermined Control value if the amount of the first difference value is the exceeds a predetermined amount. The Vorrich tion further comprises means for forming a second Difference value between the first difference value and one Integration value, which is the sum of the negated first dif reference values has been in existence since then has consistently determined that the amount of the first difference value does not exceed the predetermined amount, for ver same of the second difference value with a predetermined Threshold and for incrementing or decrementing of the digital output value depending on the result of the Comparison if the amount of the first difference is equal agreed amount does not exceed.

The present invention takes into account the knowledge that that mechanical systems have mechanical inertia tet, so that when a machine moves quickly Evaluation of the current position of the machine with full open solution is not necessary. Only when the movement is relatively slow when the machine has almost reached its destination  has and stands, the more precise position becomes interesting. Here is the expression "slow down" relative to the electroni to understand processing speed insofar as that it only takes a few milliseconds for a machine are to slow down, and a human observer to this Process described as a "stand still" for integrated electronic systems but a few milliseconds a "long Time ".

In one embodiment according to the present invention the readjustment of the initial value, d. H. the rough quanti sation, performed by adding a plurality of counter values or the current output value depending on the time who add or subtract the first difference value until the output value crosses the input signal or exceeds. After the initial value has been adjusted or if the deviation of the current digital off initial value of the value of the input signal is small a fine quantization is carried out, during which it is checked whether the second difference value has crossed the threshold, and if so, the direction is determined in that the second difference value has crossed the threshold value, whereupon the current digital output value depends on the specific direction is incremented or decremented. In the case of a constant input signal, the oscillates resulting sequence of output values around the two digi tal values closest to the constant input signal around. From the frequency of occurrence of the values can by Subsequent averaging with regard to a variable Number of successive output values of the sequence from Output values a higher resolution can be achieved at for example when the machine approaches its target position and the output rate may be lower. about  the number of digital used for averaging Initial values can be the averaging duration and thus the dead time of the control system to a current travel speed or to a suitable output rate for the sequence of output rate can be set.

According to a special embodiment, this will be the case de Invention on signals in quadrature to each other as used when using LVDTs and RVDTs or Arrangements with magnetoresistive resistors or Hall sensors ren emerge. This is a 4 quadrant adder that consists of there are two multiplying DACs and an adder, ver turns to from the signals in quadrature to each other to get the first difference value. The present inven is therefore suitable to make a pair of signals the same Process frequency and one from the current amplitude to determine digitally represented value of one in the eye represented by a sensor. At digitization can be the phase of the input signals contained carrier are taken into account, thereby a implementation tion and demodulation can be carried out simultaneously.

An advantage of the present invention is that a Integration of a converter according to the present invention lighter than with the converters known in the prior art is feasible. In particular, integration into a Standard CMOS technology possible. The reason for this is there in that between the subsequent linear interpolation a higher resolution than the resolutions solution of the multiplying DACs of the 4-quadrant Multiplier can be achieved, which increases the area needed for the multipliers used, and the same become faster. In addition, three comparators take over  the task of those used in conventional converters, VCOs that are difficult to reproduce, and because of that In the absence of a PSD, interference, signal distortion occur increased chip area consumption, offset problems, etc., as in State of the art occur away so that overall less critical components must be used.

Another advantage of the present invention is that better dynamic properties with high static on solution can be achieved. Consequently, using the Method or device of the present invention also very fast machine controls digitally implemented become. In particular, the resolution of the sequence depends on digi tale output values, as required in practice, from the Dy namik of the input signal, with rapidly changing on Abge signals with a high rate but with low resolution be groped, such as B. with a step size that a more times the total resolution, and slowly changing Input signals can be sampled with high resolution.

Another advantage of the present invention is the speed and stability of the tracking of the digital output value, since the sequence of output values can react more quickly to a large change in the input signal and still has hardly any overshoot. The interference suppression and the elimination of the control deviation using the integration value are retained. In addition, the integration value sums up all previous conversion errors and consequently enables the subsequent interpolation of values between the values that can be set with the multiplier DACs. The resolution of a converter according to the invention can be increased by an interpolation filter with a length of 2 ^Ni by Ni bits.

Preferred embodiments of the present invention are made below with reference to the accompanying drawings gene explained in more detail. It shows

Fig. 1a, 1b and 1c are schematic representations of Sensoranord regulations for position measurement with generation of mutually quadrature output signals according to the prior art;

Fig. 2 is a vector diagram to illustrate the coherence between mutually quadrature output signals, an excitation signal and an angle of rotation;

Fig. 3 is a block diagram of a converter with separate digitization of the two input signals according to the prior art;

Fig. 4 is a block diagram of a converter with a Si nus / digital converter according to the prior art;

Fig. 5 is a block diagram of a ratiometric converter according to the prior art;

Fig. 6 is a block diagram of a converter according to an exemplary embodiment from the present invention;

FIG. 7 is a block diagram illustrating the part of the converter of FIG. 6 that performs the rough quantization;

FIG. 8 is a block diagram of the fine quantization by leading part of the converter of FIG. 6;

FIG. 9 is a block diagram of the part of the converter of FIG. 6 performing the averaging of the sequence of output values; FIG.

Fig. 10 is a block diagram of the 4-quadrant adder of the converter shown in Fig. 6;

11a is a graph plotted in the klenschritte against successive signal values Zy Fig occurring in a first example of the circuit of Fig. 6.;

Figure 11b is a graph plotted in the klenschritte against successive Zy further signal values that occur in the first example process of Fig 11a..;

11c is a graph plotted in the klenschritte against successive signal values Zy Fig occurring in a second example of the circuit of Fig. 6.;

Fig. 11d is a graph plotted in the klenschritte against successive Zy further signal values which occur in the second example flow of Fig 11c. and

Fig. 12 is a block diagram of a converter according to a spe cial embodiment of the present inven tion.

Referring to FIG. 6, a converter will first be described according to an embodiment of the present invention. In particular, FIG. 6 shows the block diagram of the converter, while FIGS. 7-10 show individual parts of the converter, on the basis of which the mode of operation of the converter of FIG. 6 is explained.

As shown in FIG. 6, the converter includes a 4-quadrant adder 610 , an inverting integrator 620 , an adder 630 , three comparators 640 , 650 , 660 (H, L, I), control logic 670 , an open / Down counter 680 and an adaptable digital filter 690 . An input of the adder 610 is connected to the input 700 of the converter to receive the input signal α, the output of the adder 610 being connected to the inputs of the comparators 640 and 650 and the integrator 620 and an input of the adder 630 . In addition to the output signal ε of the adder 610, the adder 630 receives the integrated output signal Σ of the integrator 620 . The output δ of the adder 630 is connected to an input of the comparator 660 . The outputs of the comparators 640-660 are each connected to an input of the control logic 670 . The control logic 670 is connected at three outputs to an input of the integrator 620 , the up / down counter 680 and the adaptable digital filter 690 . The output of the up / down counter 680 is connected to a further input of the adder 610 and to an input of the digital filter 690 and outputs the conversion result or the current digital output value Θ _n . The output of the adaptive filter 690 is connected to an output 710 of the converter in order to output the filtered conversion result.

After the circuit structure of the converter has been described with reference to FIG. 6, the mode of operation of the converter is explained with reference to FIGS . 7-10, it being pointed out that in FIGS. 7-10 the same elements as in FIG Fig. 6, the same reference numerals are used, and an explanation of the interconnection of these elements is therefore omitted. In addition, to simplify the Dar position in Fig. 8, the control logic 670 has been omitted.

FIG. 7 shows the part of the circuit of FIG. 6 which carries out the rough quantization of the input signal α. This portion is formed by a feedback loop that includes 4-quadrant adder 610 , comparators 640 , 650, and 660, control logic 670, and up / down counter 680 . In the adder 610 , the current conversion result Θ _n , which is stored in the up / down counter 680 , is subtracted from the analog input signal α, as a result of which an error signal ε = α - Θ _{n is} generated at the output of the adder 610 . The comparator 640 receives the error signal ε and checks whether the error signal ε exceeds a certain threshold value S. Correspondingly, the comparator 650 checks the error signal ε to determine whether it is less than the minus the threshold value S. Since the integrator 620 ( FIG. 6) does not supply an output signal, the adder 630 ( FIG. 6) passes on its input signal ε directly and can be omitted for this consideration. The comparator 660 checks whether the value of ε exceeds zero. Consequently, the three comparators 640 , 650 and 660 cooperate in order to check whether the error signal ε lies outside a specific area surrounding the zero or whether the magnitude of the error signal ε exceeds the threshold amount and which sign ε has.

If the amount of the error signal ε exceeds the threshold amount, this means that the instantaneous digital value or the conversion result Θ _{n is} very far away from the analog input value α, the respective comparator 640 or 650 sending a corresponding signal to the control logic 670 , to cause the current digital value stored in the up / down counter 680 to be matched to the input signal α. The adaptation or readjustment of the instantaneous digital value is carried out by suitably adding or subtracting a control value, for example a specific number of counter values, the control loop acting in such a way that the current digital value is tracked until the converter result Θ _n the analog input value α exceeds or crosses. This tracking is preferably carried out without a major time delay, for example using proportional control. For example, it can be provided that in the event that the amount of the error signal ε exceeds the certain threshold value, the up / down counter 680 the current digital value per control cycle by a certain number of counter values adapted to the amount of the error signal ε increased or decreased. A lookup table could be used to determine the number of counter values depending on the error signal ε. Such an adjustment of the counter increment or the resolution takes into account the fact that machines have a mechanical inertia, so that it is not necessary to track the current digital value by individual counter values. This also enables faster machine movements to be tracked. However, it is also possible for the current digital value Θ _n in the up / down counter 680 to be updated per cycle simply by adding or subtracting a single counter value or incrementing or decrementing it.

It is optionally also possible not to wait for the completion of the rough quantization until Θ _n α crosses over, but to proceed to fine quantization immediately after the amount of ε falls below the threshold value S.

7, the resolution of the conversion result Θ _{n is} limited by the digital width of the up / down counter 680 in the case of the rough quantization which is described with reference to FIG. 7, it is the case with a fine quantization that refers to FIG. 8 will be described in the following, possible by subsequent digital filtering to increase the resolution of the conversion result Θ _n . The part of the circuit of FIG. 6 which carries out the fine quantization is shown in FIG. 8 and comprises in a control loop the 4-square adder 610 , the inverting integrator 620 , the adder 630 , the comparator 660 , the control logic 670 ( FIG. 6) and the up / down counter 680 . This part of the circuit acts to carry out the fine quantization in the event that the current conversion result Θ _n deviates only slightly from the input signal α, for example only by at most 2 counter values. If this is the case, the integrator 620 is activated by the control logic 670 ( FIG. 6), which is again not shown in FIG. 8 for reasons of clarity, and the fine quantization begins. If the fine quantization takes place during successive clock cycles, ie if the check of the error signal ε in successive cycles shows that the current implementation result Θ _n differs from the input signal α by less than the certain threshold value S, the integrator 620 inputs at its output Integration signal Σ off, which corresponds to the integration of the previously occurring inverted error signal -ε since the time since the amount of the error signal ε was below the threshold amount for the last time. The adder 630 subtracts the integration value Σ from the current error signal ε and outputs the difference δ to the comparator 660 . The comparator 660 compares the difference value output by the adder 630 with a comparison value and outputs the result of the comparison to the control logic 670 . The control logic 670 ( FIG. 6) controls the up / down counter 680 in such a way that the current digital value Θ _n is incremented by a counter value if δ is greater than the comparison value of the comparator 660 , and Θ _n is otherwise decremented. As will become clear in the following, this regulation causes the conversion result Θ _n to fluctuate around the two digital values that are closest to the input signal α. The mode of operation of the fine quantization feedback is explained in more detail below with reference to Table 1.

Table 1

Table 1 comprises 8 columns in which from left to right the control cycle n, the value of the input signal α in the control cycle n, the digital value Θ _n in the control cycle n, the error signal ε, the integration value Σ in the control cycle n, the Difference value δ, which is output by the adder 630 in the control cycle n, the mean value of the last 10 digital values Θ _n and the control action of the control logic 670 are given before and after the decision. In FIG. 11a the values of ε, Σ and δ are plotted for easier illustration and in FIG. 11b the values of α, Θ and the mean of Θ are plotted over 10 steps on the y-axis, while the cycle steps are plotted on the x-axis are applied. In the example of Table 1, it is assumed that the digital resolution of the up / down counter 680 is limited to integer numbers. In addition, it is assumed that the determined threshold value is 2 and the comparison value is 0. Consequently, the fine quantization takes place if the magnitude of the error signal ε is less than two. Furthermore, it is assumed in the example of Table 1 that the input signal α is the angle of rotation of a machine and that the machine is at rest from a cycle n = -2.

In the cycles n = -2 to n = 0, the converter is in a rough quantization state, since the error signal ε = α - Θ _{n is} greater than two. In this case, the integrator is switched off, the integration value Σ equals zero and the difference value δ equals ε, since fine quantization is deactivated, and the coarse quantization is activated in order to readjust the digital value Θ of the up / down counter 680 until the current one Digital value Θ _n exceeds the input signal α. As shown in Table 1, it is assumed that this process requires n0 = 3 cycles. In cycle 1, the current digital value Θ _n and the input signal α are close together, so that the fine quantization is carried out.

The integration value Σ is initialized to the value 0 by the control logic 670 . The difference value δ generated by the adder 630 results in -0.3. Comparator 660 determines that this value is less than its comparison value. The control logic 670 decides that the counter 680 is now decrementing Θ to the value 14. When Θ is switched, ε and δ change abruptly to the value 0.7. Since fine quantization begins here, the control logic 670 now enables the inverting integrator 620 . From this point on, -ε is continuously integrated. In this example, the integrator time constant is chosen such that Σ changes by -ε after a step with the constant signal ε at the input of the integrator 620 .

Up to step n = 2, the integrator signal Σ has dropped to -0.7 and the difference signal δ has risen to 1.4 with it. The comparator 660 determines that the value of δ is now greater than its comparison value. The control logic 670 decides that the counter 680 Θ must increment to the value 15. When switching Θ, ε and δ change abruptly to the values -0.3 and 0.4.

Since ε is negative, the integrator signal Σ rises again and reaches the value -0.4 until step n = 3. δ has thus dropped to 0.1. Nevertheless, δ is still larger than the comparative value of the comparator 660 . The control logic 670 decides that the counter 680 Θ must increment again. Θ receives the value 16. When Um is switched, ε and δ change abruptly to the values -1.3 and -0.9.

Up to step n = 4, the integrator signal Σ continues to rise, up to the value 0.9. δ thus drops to -2.2 and is then smaller than the comparison value of the comparator 660 . Θ is decremented to the value 15 and ε and δ jump to -0.3 and -1.2, respectively.

Up to step n = 5, the integrator signal Σ continues to rise, up to the value 1.2. δ thus drops to -1.5 and is again smaller than the comparative value of the comparator 660 . Θ is decremented to the value 14 and ε and δ jump to 0.7 and -0.5, respectively.

Up to step n = 6 the integrator signal Σ falls again, down to the value 0.5. δ thus rises to 0.2 and is greater than the comparison value of the comparator 660 . Θ is incremented to the value 15 in and the signals ε and δ jump to -0.3 and -0.8, respectively.

The integrator signal Σ rises up to step n = 7, up to the value 0.8. δ thus drops to -1.1 and is then less than the comparison value of the comparator 660 . Θ is decremented to the value 14. ε and δ jump to 0.7 and -0.1, respectively.

Up to step n = 8, the integrator signal Σ falls again, down to the value 0.1. δ thus rises to 0.6 and is greater than the comparative value of the comparator 660 . Θ is incremented to the value 15 in and the signals ε and δ jump to -0.3 and -0.4, respectively.

This continues until step n = 11, where Θ at n = 9 de incremented and incremented at n = 10.  

Up to step n = 11, the integrator signal Σ has the value 0.0 reached again. The situation corresponds to that of the step n = 1. From the table it can be seen that from step n = 11 to step n = 21 the states from step n = 1 to Repeat step n = 11. This cyclical behavior with the Period of ten steps in which the digital output value Θ fluctuates around those digital values that initial value α is closest, continues as long as α does not change.

In other words, the error signal ε is compared with the integrator signal Σ at each step. Θ oscillates between the two nearest α values - as can be seen in steps n = 5 to n = 12. If ε is rather positive on average, i.e. Θ too small on average, Σ continues to decrease until Θ increases again from größeren _{i + 2} from the larger of the two values - as in step n = 13 - because Σ is smaller than the smaller value of ε. As a result, Θ becomes too large on average, Σ rises again and Θ oscillates back and forth between the two α closest values Θ _i <α and Θ _i + 1 <α.

If α lies exactly between Θ _i and Θ _i + 1, Θ only oscillates between the two values.

If α <Θ _i + 0.5, the value Θ _i + 2 also occurs regularly to compensate. If α <Θ _i + 0.5, the value Θ _i - 1 also occurs regularly.

Overall, this fine quantization feedback process corresponds to the functioning of a SIGMA-DELTA converter. Interpolated intermediate values can be determined from the ratio of the frequency of the occurrence of the digital values by averaging over several steps in a digital filter, as will be explained in more detail with reference to FIG. 9.

If one averages the last 10 Θ values of Ta belle 1, you get after a settling time of maximum 10 steps after fine quantization begins, the ge closer conversion result of 14.7, as in the seventh column the table is plotted as once within a period the value 16, five times the value 15 and four times the value 14 occurs.

Referring to Fig. 8 and Table 1, however, it should be noted that although in the foregoing the comparative value of the comparator 660 was zero, it can also be set to another value. Accordingly, the initialization value of the integrator 620 can also be set to a value other than zero. It is also possible to add the error value ε to the initialization value immediately upon initialization. With reference to Table 1, it is pointed out in particular that the fine quantization control in discrete cycles has been described above, but that the actual digitization only takes place at the up / down counter 680 , and that the integrator 620 , the adder 630 and the Represent comparator 660 analog components, and the integration value Σ and the difference value δ are analog signals. The values shown in Table 1 are only obtained by applying a suitable clock to the control logic and to the up / down counter.

The analog signal path to the integrator 620 ensures that small disturbances, which are superimposed on the input signal α, are averaged by the integrator 620 and small or slow changes in the input signal are continuously taken into account by summing up all previous errors in the output signal Θ.

Furthermore, it is pointed out that the switching behavior of the control logic 670 in this example represents a simple implementation, and that the integrator 620 and the up / down counter 680 can also be controlled with more complex decision criteria and thus other sequences of digital values are generated , which on average also correspond to the input signal α.

As an example, reference is made here to the sequence illustrated in Table 2 and shown in FIGS . 11c and 11d. The structure of the columns of Table 2 corresponds to that of Table 1. In Fig. 11c the values of ε, Σ and δ and in Fig. 11d the values of α, Θ and the mean of Θ over 10 steps on the y- Axis plotted, while the cycle steps are plotted on the x-axis. In the process shown, the assumptions are identical to those for the process described with reference to Table 1. The only difference lies in the decision criterion for the up and down control of the counter 680 . Here the counting direction is also determined from the sign of δ.

Table 2

First, however, only one step is counted further and then, with the sign of δ remaining the same, at least a certain number n _W steps are waited until counting continues again in the same direction. In the present example, the number of steps to be maintained is n _W = 3. If δ retains the same sign for a long time, counting continues in this direction, since it must be assumed that α has changed. In this way, however, it is ensured that Θ _n only switches back and forth between the two α closest values Θ _i <α and Θ _i + 1 <α.

As can be seen from Table 2, the mean value of the last 10 values of Θ _n again corresponds to the input value α = 14.7.

The part of the circuit of FIG. 6 that performs the averaging will now be described with reference to FIG. 9. This part comprises the control logic 670 and an adaptable or adaptive digital filter 690 , which outputs the filtered conversion result at the output 710 .

If the input signal α is constant for a longer period of time or changes very slowly, a digital value corresponding to the input signal α can be linearly interpolated with high accuracy between the Θ _n values by averaging over a longer period of time. With a high traversing speed or rapid change in the input signal α, however, it makes sense to keep the mean duration short so that the dead time of the control system remains short. The adaptable digital filter 690 makes it possible to adapt the resolution and the dynamic course of the filtered conversion result Θ to the current speed of travel. The control logic 670 receives the information on the travel speed, for example via a further input from the outside, or uses the comparator signals KI, KM and KL ( FIG. 6) originating from the coarse and fine quantization, and controls the digital filter 690 accordingly. For this purpose, the control logic 690 dynamically controls the instantaneous filter length of the digital filter 690 or adjusts the same to the travel speed. In addition, it can be provided that the control logic 670 further information such. B. predetermined by the user resolution requirements, emp catches to control the adaptable digital filter 690 or its momenta ne filter length.

The structure of the 4-quadrant adder 610 of FIG. 6 will now be explained in more detail with reference to FIG. 10. However, it should be noted in advance that any adder can be used in the circuit of FIG. 6 if the input signal α is already present as a single analog value. The 4-quadrant adder 610 is provided in order to determine the error signal ε from the current digital value Θ _n and the signals Usin and Ucos, which are in quadrature with respect to one another, for example by a measuring arrangement as shown in FIGS . 1a-1c is shown.

As can be seen in FIG. 10, the 4-quadrant adder 610 comprises a sine 810 and a cosine multiplier 800 and an adder 820 . An input of the cosine multiplier 800 is connected to an input 805 of the 4-quadrant adder 610 to receive the input signal Usin, and another input is connected to an input 807 of the 4-quadrant adder 610 to the current digital value Θ _n to receive. The output of the cosine multiplier 800 is connected to a non-inverting input of the adder 820 to output the result of the multiplication of Usin and cos (Θ _n ). An input of the sine multiplier 810 is connected to an input 815 of the 4-quadrant adder 610 to receive the input signal Ucos, and another input is connected to the input 807 of the 4-quadrant adder 610 for the current digital value Θ _n to receive. The output of sine multiplier 810 is connected to an inverting input of adder 820 to output the result of multiplying Ucos and sin (Θ _n ). The adder 820 outputs the error signal small ε at an output 830 . The value of the error signal ε consequently assumes the value ε = U ₀ (t) (sin (α) cos (Θ) - cos (α) sin (Θ)). Using the approximation

E = sin (α) cos (Θ) - cos (α) sin (Θ) = sin (α - Θ) ≈ α - Θ

the error signal ε = U ₀ (t) thus generated results. (α - Θ).

The 4-quadrant adder can be supplemented by a correction table 840 , which also receives the current digital value Θ _n , received. Its output feeds the digital / analog converter 850 , the output of which in turn is fed to the adder. The correction table 840 can also additionally receive the carrier synchronization signal 855 required for the demodulation described subsequently.

With this arrangement, manufacturing tolerances of the multipliers 800 and 810 can be compensated for. The correction table le 840 generates a digital correction signal 860 from the digital value 807 , which is converted in the digital / analog converter 850 into an analog signal which corrects the ε signal by small values. This is particularly important if the demodulation described below is to be carried out and the factors of the multipliers 800 and 810 for Θ _n and -Θ _{n have} to match.

Since Θ tracks the input signal α, a similarly large signal α is always to be expected for a certain Θ _n in connection with a certain state of the carrier synchronizing signal 855, and the result ε is therefore always subject to the same error. A correction of ε is therefore sufficient; a correction of the factors of the multipliers 800 and 810 is not necessary.

The phase-sensitive demodulation of one with, for example, U ₀ (t) = U ₁ . cos (ωt) modulated pairs of signals can be easily accomplished by using the steps in which the carrier signal U ₁ . cos (ωt) <0, instead of Θ _n a -Θ _{n is} fed back. Due to the sinusoidal shape of the carrier but the achievable accuracy of linear interpolation decreases with constant filter length. It is also important to ensure that the mediation takes place over a whole number of periods of the carrier signal.

Referring to FIG. 12, a converter according to a particular embodiment of the present invention will now be described, FIG. 12 showing the block diagram of the converter. The converter is intended for use in digitizing measurement signals, such as those generated by the measurement arrangements shown in FIGS . 1a-1c.

The converter of FIG. 12 comprises two inputs 900 and 905 for receiving the input signals Usin and Ucos which are quadrature with respect to one another and an input 910 for receiving a clock signal CLK. An input 915 is also provided, to which a signal U carrier with carrier frequency is coupled. The circuit further comprises an output 920 , at which the ge filtered conversion result THETA_OUT is output, an output 925 , at which the voltage UEPSILON is output, which corresponds to the error signal ε, and an output 927 , at which the voltage UINT is present, which corresponds to the integration value. The two inputs 900 and 905 are each connected to the input of a DAC (Digital Analog Converter = Digital tal / analog converter) 930 and 935 , the outputs of which are connected to an inverting and a non-inverting input of a summer 940 . The output of the summer 940 is connected to the output 925 of the converter, an input of an inverting integrator 945 and an input of three comparators 950 , 955 and 960 . The output of the inverting integrator 945 is connected to the other input of the three comparators 950-960 and the output 927 of the converter. The outputs of the comparators 950-960 are connected to three inputs of a control logic 965 in order to output signals KI, KH and L to the control logic. In the control logic 965 , a further input is connected to the input 910 of the converter in order to receive a clock signal CLK, as well as an output with an input of the inverting integrator 945 for transmitting a reset signal RESET_INT to the same and a further output with a loop counter 970 for transmitting a counter control signal CNT_CNTRL. Another input of the loop counter 970 is also connected to the input 910 in order to receive the clock signal CLK. The output of the loop counter 970 is connected to both a quadrant selector 975 and an input of a digital interpolation filter 980 and outputs the signal THETA_COUNT stored in the loop counter 970 , which corresponds to the digital output value. The digital interpolation filter 980 outputs the filtered signal THETA_OUT to the output 920 , which corresponds to the filtered digital output value. Another input of the quadrant selector 975 is connected to the input 915 , a sign detector 985 being interposed in order to output a signal SYNCH_CMP indicating the sign of the signal U carrier to the quadrant selector 975 . The quadrant selector 975 is connected at an output to a further input of the DACs 930 and 935 in order to output the signals THETA_CDAC and THETA_SDAC to the same. The output THETA_CDAC of the quadrant selector 975 is connected to another input of the DAC 930 , the output THETA_SDAC to another input of the DAC 935 .

After the structure of the circuit has been described above with reference to FIG. 12, the mode of operation of the circuit is described below.

To demodulate the input signals Usin and Ucos, an additional factor (-1) should be taken into account, depending on the sign of U carrier. The two multiplying nonlinear DACs 930 and 935 are also identical and implement the multiplication in two of the four quadrants of a sine and cosine function. Since the control signals THETA_SDAC and THETA_CDAC of the two DACs only cover half the value range of THETA_COUNT, the resolution NDAC is necessary for THETA_SDAC and THETA_CDAC, but the resolution NDAC + 1 is required for THETA_COUNT, so that depending on the sign of Ucarrier and depending on the range of values the factors sin (Θ) and cos (Θ) or -sin (Θ) and -cos (Θ) can be set, the quadrant selector 975 THETA_SDAC and THETA_CDAC from THETA_COUNT must be determined appropriately.

An example is given below with reference to Table 3 for the determination of THETA_SDAC and THETA_CDAC from THETA_COUNT. Table 3 comprises 6 columns, from left to right the THETA_COUNT, the size of the carrier, the factor desired for the DAC 930 , the THETA_CDAC to be set for it, the factor desired for the DAC 935 and that for THETA_SDAC to be set. It is assumed that the multipliers realize a factor cos (Θ) for 0 ° <Θ <180 °. The result is the calculation of the THETA_CDAC from THETA_COUNT and carrier according to the fourth column of table 3 and the calculation of THETA_SDAC from THETA_COUNT and carrier according to the sixth column of the table.

Table 3

The two DACs 930 and 935 multiply the input signal Usin by +/- cos (THETA_COUNT) or the input signal Ucos by +/- sin (THETA_COUNT). In the summer 940 , the signal UEPSILON is formed according to the following equation:

ε (t) = U ₀ (t). sign (carrier). (sin (α) cos (Θ) - cos (α) sin (Θ))

This signal is integrated in the inverting integrator 945 from the time tr, since the integrator 945 has been reset by the RESET_INT signal from the control logic 965 , the result of the integration being output as the signal UINT to the comparators 950-960 becomes. The time dependence of the signal UINT is given by the following equation:

Here, T _{I represents} the integration time constant of the integrator 945 .

The comparators 950-960 compare UEPSILON with UINT. In particular, the comparator 950 compares the signal UINT with the signal UEPSILON and uses the digital output signal KI to indicate whether UEPSILON is greater than UINT. The comparator 950 checks whether UEPSILON is much larger than UINT and, if this is the case, activates the digital output signal KH. Correspondingly, the comparator 960 checks whether UEPSILON is much smaller than UINT and, if this is the case, activates the digital output signal KL.

The loop counter 970 can change its stored value on each active clock edge of the clock signal CLK. The control logic 965 controls the state of the counter 970 and the reset of the integrator 945 by the signals RESET_INT and CNT_CNTRL after the next clock depending on the signals KI, KH and KL. In the present case, the Steuerlo gik 965 controls the loop counter 970 such that if

• a) the signal CI is active, the loop counter 970 increments the loop counter value stored ge THETA_COUNT or otherwise decremented, whereby the signal THETA_COUNT takes a sequence of values corresponding to the input signal on the average.
• b the signal KL or the signal CH is active), that is, the magnitude of the error signal e is very large, the loop counter 970 subtracts a predetermined number of counter values from the stored value THETA_COUNT or to one of the same, so that here by the tracking of THETA_COUNT to the fine quantization range is achieved.

In the latter case, the control logic activates the signal RESET_INT, since the integration is not required. Hereby the loop for tracking THETA_COUNT becomes faster.

Interpolation of intermediate values is carried out if necessary by averaging in the digital filter 980 in conjunction with the integrator 945 . In the event that UEPSILON is too large for a few bars, but is not sufficient to switch AI, UINT continues to drop. The errors due to the multiplication of smaller resolution N _DAC in the DACs 930 and 935 are summed up in the integrator 945, namely until the signal KI switches. This makes UEPSILON much smaller, and in most cases negative. As a result, UTNT increases until signal K is switched again. In this way, the digital signal THETA_COUNT, which has a fixed resolution of NDAC + 1, always oscillates around the two values closest to the input signal. From the frequency of the occurrence of the values, however, the signal THETA_COUNT with a higher resolution than N _DAC + 1 can be obtained by averaging in the digital filter 980 .

By resetting the integrator 945 for large error signals UEPSILON, which occur when α changes rapidly, it is ensured that it is not overdriven and goes into saturation. In this case, the integrator 945 is immediately available for interpolation as soon as the signal THETA_COUNT is again in the correct area or the fine quantization area. The signal THETA_COUNT contains the information about the input signal coded with the highest possible sampling rate of the system. This allows the interpolation filter 980 to determine the output signal THETA_OUT optionally by reducing the sampling rate in the required resolution N = N _DAC + 1 + N _Interp , where N _Interp indicates the resolution gained by the interpolation _filter 980 .

Having described the invention in the foregoing by way of example, it should be understood that although the apparatus and method of the present invention have been described in relation to signals quadrature with one another, the present invention is applicable to any analog signal is, and the same can be used particularly advantageously if rapid changes in the input signal allow a coarse quantization, while otherwise a high resolution is required. In this case, the 4-quadrant adder of Fig. 6 could be replaced with a normal adder.

It is also possible to use the coarse quantization control loop belonging comparators several times and with different ver to perform equivalent values that differ in amount from each other distinguish, whereby one depends on the size of the error signal fit tracking can be realized.

Claims (17)

1. A method for converting an analog input signal (α) into a sequence of digital output values (Θ _n ), with the following steps:

• a) forming a first difference value (ε) between the current digital output value (Θ _n ) and the analog input signal (α);
• b) checking whether the amount of the first difference value (ε) exceeds a predetermined amount (S);
• c) if the amount of the first difference value (ε) exceeds the predetermined amount, readjusting the digital output value (Θ _n ) using a specific control value;
• d) if the amount of the first difference value (ε) does not exceed the predetermined amount,
  • 1. Forming a second difference value (δ) between the first difference value (ε) and an integration value (Σ), which consists of the sum of the first difference values (ε), since the check in step d) consistently showed that the Amount of the first difference value (ε) does not exceed the predetermined amount;
  • 2. comparing the second difference value with a predetermined threshold value;
  • 3. Incrementing or decrementing the digital output value depending on the result of the comparison in step d2).

2. The method according to claim 1, wherein the step of readjusting in step (c) adding or subtracting a plurality of predetermined counter values to or from the current digital output value (Θ _n ) depending on the sign of the first difference value (ε ) until the output value (Θ _n ) crosses the value of the input signal (α) or the amount of the first difference value (ε) falls below the predetermined amount (S). 3. The method according to claim 1 or 2, wherein step d3) has the following substeps:

• 1. if the second difference value (δ) is greater than the predetermined threshold value, incrementing the digital output value (Θ _n ); and
• 2. If the second difference value (δ) is smaller than the predetermined threshold value, decrement the digital output value (Θ _n ).

4. The method according to claim 3, wherein step d3a) has the following substep:
Suppressing the increment for a predetermined number of times since the comparison in step d2) continuously showed that the second difference value (δ) is larger than the predetermined threshold value,
and in which step d3b) has the following substep:
Suppressing decrementing for a predetermined number of times since the comparison in step d2) consistently showed that the second difference value (δ) is smaller than the predetermined threshold. 5. The method according to any one of claims 1 to 4, further comprising the following steps:
Forming an average value with respect to a variable number of successive output values (Θ _n ); and
Output of the mean value as a filtered output value in the sequence of output values (Θ _n ) instead of the successive output values (Θ _n ). 6. The method of claim 5, further comprising the step of having: Adapting the variable number to a given off feed rate. 7. The method according to any one of the preceding claims, wherein step a) of forming the first difference value comprises the following steps:
Receiving a first and a second input signal (Usin, Ucos) which are in quadrature with one another;
Multiplying the first input signal (Usin) by the cosine of the digital output value (Θ _n );
Multiplying the second input signal (Ucos) by the sine of the digital output value (Θ _n );
Adding up the results of the multiplications; and
Output the sum as the first difference value (ε). 8. The method according to claim 7, in which the negative digital output value (Θ _n ) is used for multiplication if the carrier signal (U carrier) with which the first and second input signal (Usin, Ucos) is modulated is less than zero. 9. Device for converting an analog input signal (α) into a sequence of digital output values (Θ _n ), with
means ( 610 ) for forming a first difference value (ε) between the current digital output value (Θ _n ) and the analog input signal (α);
means ( 640 , 650 ; 655 , 660 ) for checking whether the amount of the first difference value (ε) exceeds a predetermined amount (S);
means ( 670 , 680 ; 965 , 970 ) for readjusting the digital output value (Θ _n ) using a predetermined control value if the amount of the first difference value (ε) exceeds the predetermined amount (S);
a device ( 620 , 630 ; 945 , 950 ) for forming a second difference value between the first difference value (ε) and an integration value (Σ), which consists of the sum of the first difference values (ε), since the check by the device for checking ( 640 , 650 ; 955 , 960 ) consistently showed that the amount of the first difference value (ε) does not exceed the predetermined amount (S), for comparing the second difference value with a predetermined threshold value, and for incrementing or decrementing the digital output value (Θ _n ) depending on the result of the comparison. 10. The apparatus of claim 9, wherein the means ( 670 , 680 ; 965 , 970 ) for readjusting further a device for adding or subtracting a plurality of predetermined counter values to or from the current digital output value (Θ _n ) depending on has the sign of the first difference value (ε) until the digital output value (Θ _n ) crosses the input signal (α) or the amount of the first difference value falls below the predetermined amount (S). 11. The device according to claim 9 or 10, wherein the device for incrementing or decrementing has the following features:
means for incrementing the digital output value (Θ _n ) if the second difference value (δ) is greater than the predetermined threshold value; and
means for decrementing the digital output value (Θ _n ) if the second difference value (δ) is smaller than the predetermined threshold value. 12. The apparatus of claim 11, wherein the means for incrementing comprises:
means for suppressing the increment for a predetermined number of times since the comparison by the means for comparison continuously revealed that the second difference value (δ) is larger than the predetermined threshold value,
and in which the device for decrementing has the following feature:
means for suppressing decrementing for a predetermined number of times since the comparison by the means for comparison continuously revealed that the second difference value (δ) is less than the predetermined threshold. 13. The device according to one of claims 9 to 12, further comprising:
means ( 690 ; 980 ) for forming an average value with respect to a variable number of successive output values (Θ _n ) and for outputting the average value as a filtered output value instead of the successive output values (Θ _n ). 14. The apparatus of claim 13, further comprising:
Means ( 670 ) for adapting the variable number to a predetermined output rate. 15. Device according to one of claims 9 to 14, wherein the device ( 610 ) for forming the first differential value (ε) receives a first and a second input signal (Usin, Ucos), which are in quadrature with one another, and has the following features :
a cosine multiplier ( 800 ) for receiving the first input signal (Usin) and for multiplying it by the cosine of the digital output value (Θ _n );
a sine multiplier ( 810 ) for receiving the second input signal (Ucos) and for multiplying it by the sine of the digital output value (Θ _n ); and
an adder ( 820 ) which receives the results of multiplication of the cosine and sine multiplier ( 800 , 810 ) for adding them and outputting the sum as the first difference value (ε). 16. The apparatus of claim 15, wherein the sine and cosine multiplier ( 800 , 810 ) use the negative digital output value (Θ _n ) for multiplication when the carrier signal (U carrier) with which the first and second input signal ( Usin, Ucos) is modulated, is less than zero. 17. The device according to any one of claims 9 to 16, which in egg standard CMOS technology is implemented.