DE1004242B - Clock relay circuit with a relay for telecommunications, in particular telephone systems - Google Patents

Description

The invention relates to a clock relay circuit with a relay that is triggered by a capacitor surge to respond and after charge reversal of the capacitor by a second capacitor surge Direction is brought back to waste, for telecommunications, especially telephone systems.

There are already clock relay circuits of this type become known in which the capacitor on the Switching spring of a switching contact of the relay is switched on, so that it is dependent on the purpose of reloading of the respective state (energized, de-energized) of the relay with either one or the other pole connected to a battery. In these known arrangements are for the control of further processes, z. B. to identify the state of the clock relay circuit or to identify marker points, additional contacts are required because the The changeover contact connected to the capacitor cannot be used multiple times.

The object of the present invention is to provide additional clock relay circuits of the type mentioned To save contacts. This is achieved by closing a self-holding circuit via a Contact of the relay at the same time the recharging circuit of the capacitor runs and that said contact is on a fixed potential. Accordingly, the contact in addition to switching on the holding device and the control of the charge reversal of the capacitor. B. the identification of the condition the clock relay circuit or the control of subsequent clock relay stages.

In FIGS. 1 and 2, two exemplary embodiments of the invention are shown, the mode of operation of which follows should be explained in more detail:

A. How the clock relay circuit works
according to FIG. 1

In the idle state, the capacitor K is charged:

Clock relay circuit with one relay

for telecommunications, in particular

Telephone systems

Applicant:
Siemens & Halske Aktiengesellschaft,

Berlin and Munich,
Munich 2, Wittelsbacherplatz 4

Günther Gattner, Ottobrunn,
has been named as the inventor

After the end of the pulse, contact 4 »is opened again and contact 2i is closed. The capacitor is in series with resistor R1 in parallel with resistor R2:

3. +, Sz,

R2

K, 2%, Rl

, uz, -.

In this circuit, the capacitor K is charged in the opposite direction, so that the winding IZ, after the capacitor is again connected in parallel, is traversed by a current in the opposite direction when the second pulse starts. The relay Z drops out and the circuit 1 is established again.

B. Operation of the clock relay circuit according to FIG. 2

2i, K, R2
Al

UZ,

The winding HZ of the relay Z located in this circuit receives fault current so that the relay does not pick up. With the first pulse, contact 2i opens and interrupts the charging circuit of capacitor K. With contact 4i, the capacitor is switched parallel to winding IZ of relay Z. Due to the discharge current surge, relay Z responds, opens its contact 1 ζ and closes its contact 3z. The winding HZ of relay Z is in a new circuit in which the relay remains:

2. +, 3z, R2.IIZ, -:

In the clock relay circuit shown in FIG. 2, the charge reversal of the capacitor K takes place after the relay Z has responded in a circuit that is independent of the pulse contact controlling the clocking process. The contact 2i shown in FIG. 1 was replaced by a resistor RZ in this exemplary embodiment. Accordingly, the resistor R3 is also located in the circuit 1 instead of the contact 2i. After relay Z has responded, a holding circuit corresponding to circuit 2 is closed during the first pulse, which is still ongoing:

4. +, Zz,

R2

K RZ, Rl

IZ, 4 *

609 839/157

When the pulse ends, the becomes parallel to the Winding IZ of the relay Z lying capacitor disconnected from this and connected to a circuit 3 corresponding Circuit reloaded:

222

5. +, 3z, -

K ₁ R3, Rl

UZ, -.

As in the case of the clock relay circuit according to FIG. 1, the relay Z of the arrangement shown in FIG. 2 drops out again by discharging the capacitor K through its winding IZ after the onset of the second pulse.

Claims (2)

PATENT CLAIMS: 1. Clock relay circuit with a relay, which is brought back to waste by a first capacitor surge to respond and after reloading the capacitor by a second capacitor surge in the opposite direction, for telecommunications, in particular telephone systems, characterized in that a self-holding circuit closing contact ( 3z) of the relay (Z) at the same time the charge reversal circuit of the capacitor (K) runs and that said contact (3z) is at a fixed potential (e.g. positive potential). 2. Clock relay circuit according to claim 1, characterized in that the charge reversal circuit of the capacitor (K) runs via a circuit that is independent of the pulse contact controlling the clocking process (^ i '). Considered publications:
German patent specification No. 931 535. 1 sheet of drawings © 609 839/157 3.57