DD211171A1 - CIRCUIT ARRANGEMENT FOR DIGITAL MEASUREMENT IMPLEMENTATION IN INCREMENTAL MEASUREMENT SYSTEMS - Google Patents

Abstract

In a circuit arrangement for digital measured value conversion in the incremental measuring system, the implementation time and the technical-economic expenditure of providing the measured values in the corresponding mass system of the further processing should be reduced. For this reason, the number of information processing steps required for the measurement acquisition and conversion had to be reduced. According to the invention, the measured value conversion already takes place directly during the acquisition and storage of the measured value, in that instead of the directly arriving incremental count signals and direction signals only certain count signals are evaluated, the necessary regime being generated by means of addition-substration steps and sign tests, so that a multiplicative Expression of the acquired measured value is present.

Description

Title of invention:

Circuit arrangement for digital measurement conversion in incremental Meßaystemen

Application Which Achieves , J ₁

The invention relates to a SohaItungaanOrdnung for digital Meßwertumsetzung in incremental Meßaystemen, in the digital counting and Zählrichtungssignale an incliners pulse encoder detected and the count signals are stored in the form of counter contents as measured values and in which the measured value information to be converted into other systems.

The invention is applicable, for example, to those systems in which the dimensioning is given by the wavelength of light but is to be measured in the metric system. (Laser interferometer )

The application is particularly advantageous if the measured values are needed in a very fast lateral sequence for further processing.

A special application is a corpuscular beam exposure system in which a slide shift is dynamically integrated into the active machining process and thus to be detected in fast-paced object positions in the metric system.

4097

Characteristic of the known technical solutions:

It is generally known to record and store the increment or decrements of incremental transducers as counter contents. When using such transducers, it is often necessary to convert the determined measured values into other systems of measurement (for example, metrical system J. For these conversion functions, sufficiently well-known systems are needed.) It has also already been proposed to use a possibly present device control computer, which in In addition, the relatively high expenditure of time for providing up-to-date measured values in the required system of measurement for their further processing is disadvantageous.This expenditure of time can be shortened within certain limits if the conversion of the measured values involves complex, extremely fast computing units However, due to the relatively high number of required information processing steps, this reduction in the measured value provision time is due to the fact that the teohnisch-economical effort increases unreasonably but only to a limited extent possible.

Aim of the invention;

The aim of the invention is to reduce the implementation time and the technical-economic effort in providing the measured values in the corresponding measurement system of further processing.

Presentation, the story of the invention

The invention has for its object to provide a circuit arrangement for Meßwertumsetzung with a reduced number of required for the data acquisition and conversion information processing steps.

This object is achieved by a circuit arrangement for the digital measurement conversion in incremental measuring systems, in which digital counting and counting direction signals of an incremental im-

4097

44

* 3 bass

Pulsgebera detected and the count signals are stored in the form of counter contents in a counter as measured values and in which the measured information to be converted into other systems measure, according to the invention achieved in that constant register connected via a Auswählstufβ with two control inputs output side and connected to a first input of an adder are whose sum output is coupled to the D- or Setzeingang a test register at its output side feedback to the second input of the Addieratufe j that the highest bit position output (MSB) of the test register with the first control input of the selection stage, at the second oteuereingang the Zählrichtungssignal is applied, and is connected via a delay and Impulsverkürzungsstufe with a first input of an OR gate and the clock input of the counter and that the incremental count signals applied to the second input of the OR gate, the sen output to the clock input of the test register is connected.

It is advantageous if the selection stage consists of four respective gate circuits assigned to the constant registers and one of 1 selection selectors if the first input of the gate circuit has the output of the associated constant register if the second inputs of the gate positions are connected to the four outputs of the gate register 1 out of 4 select decoder and when the outputs of the gating circuits are respectively connected to the first input of the adder stage.

It is also advantageous if the gate circuits consist of BUS drivers with three-state output each. According to the invention, the measured value conversion already takes place directly in the measured value acquisition, in that instead of the directly arriving incremental counting signals and direction signals only certain counting signals are evaluated, the necessary regime being generated by means of addition-subtraction steps and sign tests, so that a multiplicative expression of the detected Measured value is present.

4097

t; mi -id Q Q * Or »Ii isf» G

.. 4 - JL, · ^ s β e ν Execution example:

The invention will be explained in more detail below with reference to an embodiment shown in the drawing.

An incremental pulse generator 1, consisting of an incremental measuring system ζ and a pulse conditioning stage 3 provides digital counting pulses ZI and a Zählriohtungssignal RI, which are to be detected by a counter 4 to a measured value. By means of the circuit arrangement according to the invention, this measured value detection in the counter 4 no longer takes place directly as an incremental measured value, but already in further processable form as a metric measured variable. For this purpose, 4 constant registers 5 »6, 7» 8 are provided for the constants -B, A, B and -A, which are connected on the output side via gate circuits 9, 10, 11, Vc to a first input E of an adder 13 , The four control inputs of the gate circuits 9, 10, 11, Vd are connected to four outputs of a 1-out-of-4 selector decoder, to whose first control input 15 the counting direction signal RI is applied The gate circuits 9, 10, 11, Va are provided by BUS drivers with The sum output 3 in the required bit width © is fed to the D or set input of a test register 16 by the adder 13 in order to store the summation value of the adder 13. The output Q of the test register is set to a second one Input Ε., Fed back to adder 13. Output signal MSB of the highest bit position of test register 16 (sign of the register contents) forms the second control signal at a control input 17 of the 1-out of 4-select decoder H and at the same time is at the input of a delay and pulse shortening stage 18 on the output side is connected to a first input of an OR gate 19 and to the clock input 0 of the counter 4. Die The Zählimpulsa ZI of the incremental pulse generator 1 are applied to a second input of the OR gate 19, the output signals of which feed the clock input C of the test register 16 as a set clock. The counting direction signal RI of the incremental pulse generator 1 is applied to the counting input ZR of the counter 4. At the counter and the test register 16 are reset inputs R, the

4097

are connected to each other and can be reset by a Rückaetzsignal SEo the counter 4 and the test register 16 to a defined initial state.

According to the invention, each increment or decrement of the pulse generator 1 causes an addition / subtraction of the constant A or a subtraction / addition of the constant B to the content of the test register 16, depending on the sign of the contents of the test register 16 (selection of the constant registers 5, 6, 7, 8) or which counting direction, ie Increment or decrement, present (selection addition / subtraction;

The puncture of the 1 of 4 selection decoder 14 consists in selecting one of the constants ± A, + B according to the following rule

EI = L · RI- = H

MSB a L - A A

243B = I-I B - B

KI = L - Vorwärt a count RI = H - countdown

With a corresponding change in sign of the content in the test register 1fo a count pulse for the counter 4 is output to the measured value detection and thus an additional addition / subtraction in the test register 16 triggered, the other one of the constant register 5, 6, 7, 8 (for the constant A or B; is selected.

The counter 4 produces a pulse rate which is reduced in comparison to the counting pulses ZI, whereby at any time on a digit exactly in the counter 4, the value y = χ. A / B is generated.

4097

Claims (3)

44 invented ungaana ur uoh. 1. Schaltungaanordnung for digital Meßwertumsetzung incremental Maßsystemen, in the digital counting and Zählrichtungasignale an incremental Pululagebera detected and the Zählaignale be stored in the form of counter contents in a counter ala measured values and in which the measured information obtained are to be converted into other measurement systems, characterized in that constant registers are interconnected on the output side via a selection stage with two control inputs and are connected to a first input of an adding stage © whose sum output is connected to the O or Set input of a test register is coupled at its output side feedback to the second input of the adder, that the highest bit position output (MSB) of the test register with the first control input of the selection stage, at the second control input the Zählrichtungssignal is applied, and a delay · - and ImpulsverkUzungsatufθ is in communication with a first input of an OR gate and with the clock input of the counter and that the incremental count signals are applied to the second input of the OR gate whose output is connected to the clock input of the test regulator. Z. Circuit arrangement according to item 1, characterized in that the Auswahlatufe consists of four times each of the constant registers associated gate circuits and a 1 of 4-Auawahldekoder that each of the first input of the gate with the output of the associated constant register that the second inputs of the gate circuits with the four outputs of the 1 aua 4- ^Ä uswahldeköder and that the outputs of the gate circuits are connected respectively to the first input of the adder. 3. Circuit arrangement to Funkt ki, characterized in that the gate circuits consist of BUS drivers, each with three-state output. For this 1 page drawings 4097