DD160015A1 - CIRCUIT ARRANGEMENT FOR MEASURING PULSE DAMAGE - Google Patents

Abstract

The invention relates to a circuit arrangement for measuring the pulse distortion, as used in Traegerfrequenzuebertragungssystemen used. The aim and object of the invention is to provide a circuit arrangement in which bounces of Signalrelaiskontaktes independent Speicheruebernahme- and Zaehlerruecksetzimpulse are generated whose output signals can be evaluated by computer or other automated systems whose recalibration is no longer required and their accuracy is very high. The object is achieved in that a circuit part is inserted in a known per se counter circuit, so that thus a delay of the input pulses is effected, so that bruises the signal relay contact of the measurement object exert no influence.

Description

Inventor: Bautzen, 01.06.1981

Ingo Reinhard Pötschke Title of invention:

Circuit arrangement for measuring pulse distortion Field of application of the invention?

The invention relates to a circuit arrangement for measuring the pulse distortion, as "B _e comes in carrier frequency transmission systems for use» z

Characteristic of the known technical solutions:

Circuit arrangements for measuring the pulse distortion in the general technical literature are already known. These circuits consist of a character transmitter, and a character receiver * The required Tastspaxmung is in the transmission part of the 'Hetzwechselspannung' ';' f = 50 Hz obtained by frequency division «The signal-to-noise ratio is 40/40 ms or 20/20 ms * The character receiver consists of a rotary coil instrument, which lies above the signal contact of the DUT on a constant current source * Integration of the signal «. The indicated current is

a measure of the signal-pause ratio *. When compared with the transmission signal, the system's pulse distortion can be determined «.

The disadvantage of this circuit arrangement is that it is not possible to use it in automated or computer-controlled test systems, since the evaluation of the measurement results is only possible manually. The "good-bad" statement is therefore subject to subjective influences Circuitry ,, in order to obtain measurement results with sufficient accuracy, must be constantly re-calibrated *

Aim of the invention;

The aim of the invention is to provide _s a circuit arrangement for measuring the pulse distortion whose output signals can be evaluated by computer or other automated systems whose recalibration is no longer necessary and their accuracy is very high and thus eliminates the disadvantages of known circuits mentioned in the prior art and thereby the measuring time is made economically more favorable '.

Explanation of the essence of the invention;

The invention has for its object a circuit arrangement for measuring the pulse distortion to create, in the buffers of the signal relay contact independent memory transfer «and Zählerrucksetzirnpul.se be generated? · According to the invention, the task is" solved "that 'in a known per se counter circuit between the gate and the numerator input and memory of the counter is inserted a circuit part is such that the signal relay contact is applied to the second input of the gate via an inverter and at the same time on the '' S-Eitigang and a delay circuit and a second Negator on the R input

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a flip ^ flop. The output of the flip-flop is connected once to a pulse recognizer circuit and negated to a monostable multivibrator »The output of this flip-flop is located on a Impulsverkurzerstufe. The output of this is connected on the one hand via a NAND gate to the memory and on the other hand via a different Impulsverkürzerstufe and a second NAND gate to the counter input «At the input of the second NAND gate is also the output of the pulse characteristic circuit« The output of this is also via a further negator to a second gate circuit, at whose input also the output of the generator is connected j «Der Ausgang der. second gate switch reaches the memory via the second NAND gate

A basic generator supplies a square wave voltage with a frequency of 10 kHz. This is converted by frequency division in the transmission pulse train with a signal-pause ratio of 20 / 20ms and fed to the DUT. The contact of the signal relay is subjected to a voltage which is applied to the gate circuit of the measuring arrangement. * When the relay contact is closed, the 10 kHz pulses of the basic generator reach a counter, i.e. "that with undistorted received transmission signal 200 4; 1 pulse for counting "The resolution of the measuring system is 10 pulses per 1 ms signal duration". The occurring measurement error is -j- 0.1 ms *

The counter is followed by a memory. During the course of the measurement, during the time in which the signal contact is opened, a memory transfer pulse and thereafter. Counter reset ζ pulse generated «'. . '·. ·.

Embodiment:

The invention will be explained in more detail below using an exemplary embodiment *

In the accompanying drawings show:

FIG. 1: block diagram of the circuit according to the invention

arrangement

Figure 2a; Pulse at output of pulse relay stage 7 Pigur 2bj Switching voltage of signal relay contact 8 Fig. 2cϊ negated switching voltage of signal relay contact 8 Fig. 2ds Pulse train at output of gate circuit 10 Fig. 2ei Pulse train at output of flip-flop 19 Fig. 2fϊ Pulse train of monostable flip-flop 24 Fig. 2gϊ SpeieherÜbernahmeimpuls Figure 2hs counter ratchet pulse

The generator generates a square wave voltage with a frequency of 10 kHz. These 10 kHz pulses are converted into the required transmission pulse sequence with the signal-to-pause ratio 20 ms / 20 ms in the divider chain 2; 3; 4; adapted by means of the following amplifier 6 to the test object to be tested »

To the other, the 10 kHz pulses of the generator 1 reach a pulse shortener stage I ₉ are shortened to a pulse duration of 35 ns and reach the gate circuit 10 Input of the gate circuit 10 placed

When the relay contact 8 is closed, the 10 kHz pulses are applied via the gate circuit 10 to the counting input of the counter 11, 12, 13.

If the transmission signal received undistorted _{s e} deh the signal relay contact 8 is 20 ms closed or "20 _s may ms.geöffnet 200. pulses in the counter reach."

If there is a pulse distortion, then correspondingly more or fewer pulses are counted. , , ·. , '·. '·. Dem.Zähler is a memory 14; 15; 16 _$ downstream at the outputs of the measurement result BCD = encrypted ready for further processing. " , , To accept the counter content into the memory and to subsequently reset the counter during the time in which the contact 8 is open, memory overflow and counter memory

-,. 5. - & W i B Ss / * »·. B

reset pulses, regardless of bouncing of the relay contact 8, are generated *

For this purpose, the negated input signal of the relay contact 8 is given to the S input of the flip-flop 19. The R input of the flip-flop 19 is delayed by the delay signal 17 by about 2.5 ms and negated in the negative input signal of the Relay contact 8 beschalte, so that at the output of the flip-flop 1-9 by about »2.5ms compared to the input signal of the contact 8 extended signal results * This signal passes, negated in the inverter 23, the monostable multivibrator 24 and is in the time in which the contact 8 is opened, shortens,. Starting from the 0 / H edge of this signal, the memory transfer pulse, which reaches the clock inputs of the memory 14, 15, 16 via the NAND gate 30, is produced in the pulse shortener stage 25. The second input of the NAND gate 30 must thereby be turned on. Potential lie *

The Zählerrücksetsimpuls arises, the memory transfer pulse below, in the Impulsverkürzerstufe 26 'at H potential of the second input of the NAND gate 27 «If the signal relay contact 8 is defective, d"> h "permanently opened or * closed, counter and memory must sequentially to zero be asked «,.

In this case, the pulse recognizer circuit 22 switches from potential H to O ₀ Thus, the output of the NAND gate 27 goes high and the counter 11, 12, 13 is reset. · Furthermore, the output of the inverter 29 switches to high potential. Pulses of the generator 1 now pass through the gate circuit 28 and the NAND gate 30 to the clock inputs' of the memory 1 4>15; 16 *. Thus takes over the, memory 1 4; 1 5; 1 6 the counter reading 0 * '.' · '·

Claims (1)

Invention claim t 1. Circuit arrangement for measuring the pulse distortion by means of a counter circuit known per se, whose input signal from a generator (1), in a divider chain (?.; 3; 4; 5.) Converted and adapted by means of an amplifier (6) to the DUT is generated and with the bouncing of the signal relay contact of the test object (8) independent Speicherübernahme- and Zählerrücksetzimpulse, characterized in that between gate (10) and counter input (11; 12; 13) and the memory of the counter (14; ) is inserted 'is a circuit part is, consisting of a flip-flop (19), at its S input, the negated switching voltage of the signal relay contact of the measurement object (8), which also still applied to the input of a gate circuit (10) and also still on the input of a Ver.zb'gerungsschaltung (17) is connected, whose output signal is negated at the R input dee flip-Plop (19), the output of a pulse to a switch (22) and on the other hand via a negator (23) to a monostable multivibrator (24) is connected and whose output via a pulse-Verkürzerstufe (25) on the one hand via a IiAND-member (30) to a memory (14; 16) and on the other hand via a Impulsverkürzerstufe (26) and a further negator (2?) To the counter input (11; 12; 13) is switched ₉ at the input of the inverter (? 7). the output of the pulse characteristic circuit is applied and this also via an inverter (29,) to the input of a 'second gate circuit (28), - to. the The generator (1) is also connected and its "output" is connected to the input of the inverter (30). For this 2 pages drawings.