CN85105547B - Memory access control system for an information processing device - Google Patents

Abstract

A memory access control system is used for an information processing apparatus having a buffer memory and a main memory. In this system, when an access request is made, if a data block to be accessed is not in an address in the buffer memory, data of a storage request from the data register is written into the buffer memory before first data among data read out from the main memory is written into the buffer memory, and then the data register is released to receive the next request.

Description

Memory access control system for an information processing device

The present invention relates to a memory access control system, more specifically, to a memory access control system suitable for an information processing device having a main memory and a buffer memory.

In an information processing device that requires high-speed data processing operations, a buffer memory capable of reading/writing data at a higher speed than the main memory is provided, and data blocks commonly used among data blocks stored in the main memory are provided in the buffer memory. Copying of part of the data, thus enabling a quick response to a CPU's access request. As an information processing apparatus having a buffer memory, the apparatus is disclosed in the following specification, for example, U.S. Patent No. 3,735,360, "Cache Buffer Operation in a Multiprocessing System" or U.S. Patent No. .3, 829, 840, "Virtual Storage Systems."

In such an information processing device having a buffer memory system, it should be allowed to reflect the update of data performed in the buffer memory to the main memory. So far, in so-called "store-through" access systems, whenever an access occurs in a data block in the buffer memory, this data is also stored in the corresponding data block in the main storage. According to this system, since the number of times of access to the main memory increases, the advantages of buffer storage cannot be exerted.

In contrast, there are well-known systems such as the "Store-in" system, in which when a data deposit/retrieval request is made, the data block that needs to be accessed is stored in the buffer memory, and the data is only stored in the buffer memory. is stored in the buffer memory, and the stored number of the main memory does not change at this time. In the "store in" system, a change bit table corresponding to each data block in the buffer memory is provided to store bits indicating whether the data is updated. When it is necessary to replace a data block (I) in the buffer memory with a new data block (II) from the main memory, if the change indication bit corresponding to the data block (I) in the aforementioned table If set, the data block (I) is swapped out to the main memory and then the data block (II) is swapped in. If the change indication bit is not set, the swap out operation of the data block (I) is omitted, and the data block (II) is transferred to the buffer memory. According to this "store in" system, the memory read and write requests from the CPU can be satisfied only by accessing the buffer memory without accessing the main memory, until the data block in the buffer memory is swapped out to the main memory, As a result, data processing can be performed at high speed.

However, in the aforementioned information processing general apparatus having a buffer memory system, if the data to be accessed is not in the buffer memory, the entire data block including the data will be transferred from the main memory to the buffer memory, The data block is then stored at a predetermined address in the buffer memory. Therefore, in the processing device, for example, a data block consists of 64 bytes, and the data block transfers data D ₀ to D ₇ from the main memory to the buffer memory in units of 8 bytes per machine cycle. The following problems will occur under the situation, that is, if a full storage request about the data D ₀ and D ₁ of 16-bit bytes is generated, usually as shown in Figure 1, until the last time when reading from the main memory into the buffer memory After the write operation of a data D ₇ is completed, the write operation of data D ₀ and D ₁ from the data register storing the request is completed, and the data register can be opened to receive the next request.

An object of the present invention is to provide a storage access control system in an information processing apparatus having a buffer memory in which the time required for data storage processing when data to be accessed is not in the buffer memory can be reduced.

Another object of the present invention is to provide a memory access control system in an information processing apparatus having a buffer memory, in which the time required to transfer a data block from a main memory to a buffer memory according to an access operation can be reduced.

Another object of the present invention is to provide a high-speed memory access control method for an information processing device having a buffer memory.

In order to achieve the above object, a memory access control system for an information processing device according to the present invention includes:

a first memory, divided into blocks;

A second memory for storing on a block basis a copy of a portion of the data stored in the first memory, the second memory being accessible at a higher speed than the first memory and having a smaller size than the first memory storage capacity;

A data register for temporary storage of data required for storage;

An address register, which is used to temporarily store the address of the required data;

judging means for issuing a judging signal indicating whether a copy of the data block including the data specified by the address in the address register is in the second memory.

The first memory access control device is used to control the operation of reading data from the first storage and the operation of writing data to the first storage;

The second memory access control device is used to control the operation of reading data from the second memory and the operation of writing data into the second memory;

A third control means for providing a control signal to the first and second memory control means in response to the identification signal of the judging means when a data storage request is generated, in such a manner that it is provided when corresponding to the request When the copy of the data block is in the second memory, the data in the data register is written into the second memory; and when the data block mentioned above is not in the second memory, the data in the aforementioned data register is written After entering the second memory, a copy of the remaining data in the corresponding data block read from the first memory is written into the second memory.

For example, in an information processing device using a memory configured with a two-level storage system (main memory and cache memory), the first memory corresponds to the main memory, and the second memory corresponds to the cache memory. However, in another information processing device using a multi-level storage system, the multi-level storage system further includes an intermediate buffer memory between the main memory and the buffer memory, and the intermediate buffer memory may be the first memory or the second memory. Two memory.

In the embodiment of the present invention.

The second memory has a data storage area consisting of a number of data blocks;

The judging means has a fourth means for generating location information to designate an area in the second memory, so that when the copy of the data block where the data specified by the address in the address register is located is not in the second memory, it is stored in the second memory from the second memory. A copy of the block of data read from memory.

The second memory takes the address determined according to the partial content of the address register as a starting point, and writes the data from the data register and the remaining data of the data block of the first memory within the range of the storage area specified by the location information from the address.

Also according to the present invention, a memory access method for an information processing device comprising a first memory divided into a plurality of data blocks and for storing part of the data stored in the first memory on a block basis a duplicate second memory capable of accessing data at a faster rate than the first memory,

The method consists of the following steps

In the first step, when the data storage request is generated, it is determined whether the copy of the data block corresponding to the storage address is in the second memory;

The second step, when judging in the first step that the data block corresponding to the storage address is not in the second memory, designate a storage area for storing the copy of the above data block;

In the third step, before transferring the data block from the first memory to the second memory, the data required for storage is written into the specified area in the second memory;

The fourth step is to store the remaining data in the data block read from the first memory and not including the data required for storage into the specified area in the second memory.

Preferably only the remaining data in a data block from the first memory is read out so that writing to the second memory can begin with data at the next address where the requested data is stored.

Other features and advantages of the present invention will become apparent from the following description in conjunction with the accompanying drawings.

Fig. 1 is a timing diagram of data storage operations in a traditional storage access control system;

Fig. 2 is a diagram for explaining the relationship between the main memory and the buffer memory;

Fig. 3 is a sequence diagram showing an example of a data storage operation in a memory access control system according to the present invention;

Fig. 4 is a block diagram showing an embodiment of the memory access control system according to the present invention;

FIG. 5 is a block diagram showing in detail the buffer memory unit 30, the main memory unit 50 and the address corrector 23 in the embodiment.

Fig. 6 is a diagram for explaining the operation of storing data into the buffer memory.

First, the relationship between the buffer memory 300 and the main memory 500 will be described with reference to FIG. 2 . The main memory 500 is divided into many blocks in such a manner that each block has a certain size, for example, 64 bytes, and each block is designated by column addresses 0 to n and row addresses 0 to m. On the other hand, the buffer memory 300 has column addresses 0 to n and row addresses 0 to 3 corresponding to the main memory. Therefore, in this example, out of the data blocks (m+1) in main memory, a maximum of 4 copies of the data blocks can be stored in the buffer memory for each column address. Of course, when it is necessary to further transfer a data block (II) from the same column in the main memory 500 to the buffer memory, it is in this state: for example, a column of the buffer memory 300 has stored four data blocks, by A least recently used (LRu-least Recently Used) system method selects a data block (I') from the buffer memory, and the data block (II) is stored in the buffer memory to replace the data block. At this time, if the content of the data block (I′) to be retired is different from that of the corresponding data block (I) in the main memory, the data block (I′) is swapped out to the main memory 500 .

Compared with the conventional system described in FIG. 1, the characteristics of the memory access control system of the present invention will be shown by the timing diagram in FIG. 3. Referring to FIG. That is, when a storage/retrieval request from the CPU occurs regarding, for example, two data D ₀ and D ₁ each having 8 byte units is included in a data block not in the buffer 300 , according to the present invention, the operation of writing the data D ₀ and D ₁ in the data register to the buffer memory starts before writing the relevant data block from the main memory 500 into the buffer memory 300 . Only the remaining data D ₂ to D ₇ (excluding the data D ₀ and D ₁ ) are transferred from the main memory 500 to the buffer memory 300 . A command for the above-mentioned data transmission can be sent to the access controller of the main memory at the same time as the data in the buffer memory is written from the data register. Since the access time to the buffer memory is much faster than the access time to the main memory, the data D ₀ and D ₁ in the data register before the first data D ₂ read from the main memory arrives in the buffer memory has been completely written, and the data register can be released immediately after the write is complete. In addition, according to the present invention, a small portion of data not including the data portion for which the CPU generates a storage request, can be transferred from the main memory to the buffer memory in the data of a data block, so that to the buffer memory Block transfers of data can be done in many more blocks than traditional systems.

FIG. 4 is a block diagram showing an embodiment of the memory access control system of the present invention for performing the above-mentioned memory access. In the figure, reference numeral 30 is a buffer memory unit including a buffer memory 300 and an address circuit, and reference numeral 50 is a main memory unit including a main memory 500 and an address circuit. In this example, _CPUs normally have access to the memory system as two registers. A storage address, a request code and a storage data supplied from the first CPU are loaded into the registers 1a, 2a and 3a, respectively. On the other hand, a storage address, a request code and storage data supplied from the second CPU are sent to the registers 1b, 2b and 3b, respectively. The contents of the registers 1a to 3a or 1b to 3b selected by the selectors 1c, 2c and 3c are respectively sent to the address register 1, the request code register 2 and the storage data register 3. The address register 1 consists of 3 fields. The first field A , composed of the second field B and the third field C. The first byte field A and the second field address B of the address register 1 represent the block address part, and the third field C represents the address part in the block. For example, the size of a block is 64 bytes, and field C, which specifies the address portion of the block, has 5 bits. Of the fields A and B representing the block address portion, field B is used as the column address of the buffer address array 5, and field B designates the column address as described above. The number of bits of the field B is the number required for specifying each column of the buffer address array 5 . For example, when the column number n is 32, the number of bits of field B is 5. Number 4 is a request receiving controller for controlling the selectors 1c, 2c and 3c.

Sequence number 5 is a buffer address array, used to store the high digit part of the address in the main memory 500 of each data block stored in the buffer memory 300 corresponding to the first field A. The buffer address array consists of 0 to n columns and each column has 0 to 3 row addresses similar to the buffer memory 300 . Sequence number 7 is a block replacement table, indicating the row address of each column in the data block, the data block will be withdrawn from the buffer memory so that a new data block can be added to the buffer memory, and sequence number 8 is a table for storing change indication bits , which is used to indicate whether the storage number of each data block in the buffer memory has changed.

When the storage address, the request code and the storage data are respectively placed in the registers 1, 2 and 3, the data retrieval by the buffer address array 5 is performed to see if the data at the address in the address register 1 exists in the buffer memory 300 in or not. This data retrieval work is accomplished in such a way that the contents of the 4 rows of the buffer address array 5 are read out using the value in the second field B in the address register as a column address, and the stored data read from each row The value of the address and the value in the first field A in the address register 1 are compared by comparators 6a, 6b, 6c and 6d. The comparators 6a to 6d correspond to row and column addresses 0 to 3, respectively. The row number judging circuit 13 decides the row address by the output of each comparator, and number 14 is a coincidence detection circuit which sets an output 14S to "1" when one of those comparators produces a coincidence output. . A selector 16 is controlled by the output 14S of the coincidence detection circuit 14 . When the output 14S is "1", the output of the line number of the judging circuit 13 is set into the register 17 through the selector 16. The selector 16 allows the output 9S of the decoder 9 to decode the output of the block substitution table 7 to be supplied to the register 17 when the output 14S of the coincidence detection circuit is "0". Therefore, when the data block required by the CPU exists in the buffer memory, the row address in the relevant data block is put into the register 17, and in the opposite case, the row address in the data block that should be converted from the buffer memory The row address is placed into register 17. The output 17S of the register 17 is supplied to the buffer memory together with the output 1BC of the second and third fields B and C in the address register 1 .

The output 14S of the coincidence determination circuit 14 is also input to 3-input AND gates 19 and 20, a buffer memory access controller 21, and a main memory access controller 22 for the required The output signal 11S from the decoder 11 encoded for decoding, and the change indication bit in Table 8 selected by a selector 10 are also input to AND gates 19 and 20 . The output 19S of the AND gate 19 is supplied to a buffer memory access controller 21, a main memory access controller 22 and a main memory address corrector 23 which will be described later. The output 20S of the AND gate 20 is provided to the controller 21 and the corrector 23 .

When the output 14S of the coincidence detection circuit 14 and the change indication bit 10S are both "0" and the output signal 11S of the decoder is "1", the output 19S of the "AND" gate 19 becomes "1". The signal 11S becomes "1" when a slave CPU generates a store request, for example, the aforementioned 16-byte full store request. Therefore, in this embodiment, when a new data block is transferred from the main memory to the buffer memory, and no swap operation is performed, the output 19S of the "AND" gate 19 is used as a drive signal to indicate the buffer memory memory access controller 21 to start the storage operation, and instruct the main memory access controller 22 to start the data transfer.

The output signal 20S of the AND gate 20 acts as a control signal allowing data in the buffer memory to be swapped out to the main memory. When a coincidence detection signal 14S is "0" and the change indication bit 10S is "1", the output signal 20S becomes "1". When the controller 21 received the "1" level of the signal 20S, it allowed a block of data specified by the signal line 17S and 1BC to be swapped out from the buffer memory 300 into the main memory, and after the swapping out was completed , set signal 21C to "1". An AND gate 18 in the output circuit of the change indication bit 10S is controlled by the signal 21C. When the signal 21C is set to "1", the output of the AND gate 18 is set to "0". Therefore, the output 19S of the "AND" gate 19 becomes "1" instead of the output 20S of the "AND" gate 20; thus since the buffer memory access controller 21 starts to store to the buffer memory and the memory operation is started by the main memory controller Block transfer operation.

FIG. 5 shows details of the buffer memory unit 30, the main memory unit 50 and the address corrector 23. Referring to FIG.

In the buffer memory unit 30, the stored information 1BC of the second and third fields B and C in the address register 1 is brought into an address register 32 through the selector 31 in the first memory cycle. The output 32S of the address register 32 addresses the buffer memory 300 . In addition, after the address 32S is updated by an increment circuit 33 having a wraparound function, this address output 32S is held by a delay register 34 . The selector 31 is controlled by a control signal 21S′ output from the controller 21 . The output of delay register 34 is brought into address register 32 during the second store cycle and subsequent store cycles. On the other hand, the stored data 3S of the 8-byte unit output from the data register 3 is brought into a data buffer 36 through a selector 35, and is stored at the position of the address 32S in the storage area, which is at On the selected row in the buffer memory 300 by the selector 37a selected by the row address 17S.

In the address register 1, the output address 1ABC of the first to the third field, the output address 1BC of the second and the third field, and the data block address 12S read from the buffer address array 5 selected by the selector 12 are input to the main In the memory address corrector 23. The corrector 23 includes: an address correction circuit 24, which, through a relative data length value, causes skip address 1ABC for which the storage request has been completed for the data length; also includes a lock circuit 26, which generates an address 26S on the back , for swapping out by combining addresses 1BC and 12S; also includes a selector 25 that selects any one of address 1ABC and a correction address 24S to respond to the control signal 19S; and also includes a selector 27 that selects address 26S And selector 25 outputs any one of addresses 25S in response to control signal 20S.

The main memory unit 50 includes: a selector 51, which selects any one of the address 23S output from the main memory address corrector 23 and the address output from the delay register 54; including an address register 52, temporarily storing the selected The output of the device 51; and also includes an increment circuit 53 with a wrap-around function to update the output of the address register 52. The selector 51 is controlled by a control signal 22S output from the controller 22 . This selector selects the address 23S in the first store cycle, and selects the incremented address, that is, the address output from the delay register 54 in the next and subsequent store cycles, and puts into the address register 52.

In Fig. 3, the description about the 16-byte full storage request will be given as an example. The address 1ABC output from the address register 1 indicates the range of any data in -8 byte units in the 64 byte data block shown in FIG. 6 . In this case, when the first data D written in by the buffer memory access controller 21 starts at the address 101, the data can be read from the main memory 500 sequentially at the address indication 102 from the data D Start reading. The main memory address correction circuit 24 is used to address 1ABC based on the response number 101. The main memory read is generated starting from the corresponding number 102. On the one hand, in FIG. 6, after the data D is stored in the buffer memory 300, it is necessary to return from the storage address 32A to the boundary address 100 in the corresponding 64-byte data block. Likewise, even in the main memory unit 50, it is necessary to return to the boundary address 100 from the next address 52S after the reading of the data D is completed. Increment circuits 33 and 53 and correction circuit 24 perform previous address updates due to the aforementioned wraparound function.

Returning to FIG. 5, the data ( _D2 to _D7 ) read from the main memory 500 are sequentially supplied to the buffer memory unit 30 through the line 50S, and input to the data buffer 36 through the selector 35. In addition, when a read request is generated, the data read from the buffer 300 or the main memory 500 is taken out of the data buffer 39 and the line 30S (supplied to the buffer memory unit) through the selector 38, and sent to the CPU.

If a block of data read from the buffer memory 300 is swapped out into the main memory 500, the output 20S of the AND gate 20 becomes "1". In this case, the selector 27 in the unit 23 selects the output 26S of the lock circuit 26 and outputs it as the main memory address 23S. The lock output 26S is an address value, which is composed of the address indication value 12S of the data block to be swapped out in the main memory and the value 1BC of fields B and C in the storage address, the address indication value The memory address is read from the buffer address array 5 output from the address register 1. The latch circuit output 26S indicates the address in main memory of the data that was first read from buffer memory 300 and swapped out. Therefore, in the main storage unit 50, the data read from the buffer memory 300 and sequentially supplied through the line 30S are written into the above-mentioned address location and the subsequent address location, thereby causing the data to be updated in the main memory 500. . On the other hand, between the buffer memory 300 and the main memory 500, a cache register having data like a As much storage capacity as a block, and data blocks fetched from buffer memory 300 and brought into this buffer register may thereafter be transferred to main memory 500 at idle time.

In the above-mentioned embodiments, the embodiment of the present application is a two-stage hierarchical memory storage system composed of the main memory 500 and the buffer 300 has been described. However, in a multi-level hierarchical storage system, which has one or more levels of intermediate buffer storage between the main memory and the buffer storage, the memory access control of the present invention can be appropriately Used for data transfers between the main memory and the intermediate buffer, between the intermediate buffer and the intermediate buffer, and between the intermediate buffer and the most significant bit buffer memory. In this case, the storage at the lower significant bits in this embodiment may be the corresponding main storage, and the storage at the more significant bits may be the corresponding buffer memory .

In addition, in the above-mentioned embodiment, the constitution has been given so that only necessary data other than the stored data written into the buffer memory 300 from the register 3 is read from the main memory 500, and the main memory 500 is used. The corrector 23 transfers the data to the buffer memory 300 . However, as an improved form, it is also possible to employ a structure in which when all data sub-blocks are read from the main memory and written into the buffer memory, the write operation of the stored data is not performed. In this case, since the data storage operation from the data register to the buffer memory is performed in parallel with the data read instruction to the main memory, the advantage of quickly releasing the data register has been utilized, so the required The next stored message can be received earlier.

On the other hand, the data transfer operation when generating the entire storage request of 16 bytes has been described in the above-mentioned embodiment, but the present invention can obviously be applied to any other storage data requests at the same time, and is not limited to the above-mentioned full storage request. storage request.

Claims (26)

1, a memory access control system that is used for signal conditioning package comprises:

A first memory that is divided into many;

One second memory, be used for storing with duplicating of partial data that is the unit basis will be left in the above-mentioned first memory, this second memory can be coming access than first memory faster speed, and second memory is littler than the memory space of first memory;

One data register is used for the data of storing a memory requirement temporarily;

One address register is used for storing the address of the data of above-mentioned memory requirement temporarily;

Decision maker is used for sending a decision signal and indicates duplicating whether in second memory by the specified data place data block in the address in the above-mentioned address register;

The first memory access control device is used for control from the operation of above-mentioned first memory sense data with write data manipulation to this first memory;

The second memory access control device is used for control sense data operation and write data manipulation in above-mentioned second memory from above-mentioned second memory;

The 3rd control device, be used for when a data storage request produces, providing control signal to come the decision signal of response determine device to above-mentioned first and second memory access control apparatus, with box lunch corresponding to the data block of above-mentioned data storage request be replicated in the above-mentioned second memory time, the data in the above-mentioned data register are written in the second memory; It is characterized in that: described the 3rd control device provides control signal to respond from the next decision signal of above-mentioned decision maker to first and second control device when data storage request produces, when above-mentioned data block duplicate not in second memory the time, after data in above-mentioned data register were written in the second memory, duplicating of remaining data was written in the second memory in the above-mentioned data block that will read from first memory again.

According to the system of claim 1, it is characterized in that 2, described second memory has a data storage portions, this memory block has the capacity of a plurality of data blocks;

Above-mentioned decision maker has one the 4th device, be used for producing a positional information and specify in zone in the second memory, so as by the data block at the data designated place, address in the address register duplicate not in second memory the time the duplicating of above-mentioned data block that will from first memory, read store;

Above-mentioned second memory is in its scope of memory block that is begun to be written to the data the above-mentioned data register with from the remaining data in the data block of first memory that above-mentioned positional information determines as starting point by the address of the partial content of above-mentioned address register decision.

3, according to the system of claim 2, it is characterized in that: this system comprises that further the data length that is used for depositing according to storage proofreaies and correct from the device of the address value of above-mentioned address register output,

By this, above-mentioned first memory is the starting point remaining data (not comprising the data of storing from above-mentioned data device storage) the sense data piece sequentially from the above-mentioned address of proofreading and correct,

Above-mentioned second memory is followed the storage from the data of above-mentioned data register, will deposit in proper order from the data in the first memory.

4, according to the system of claim 2, it is characterized in that: above-mentioned decision maker has one the 5th device, in this device, whether stored a representative for the piece of each data in second memory needs above-mentioned data block is write indication information in the first memory, and when by the data block at the specific data place, address of address register duplicate not in second memory the time, this device output and the corresponding above-mentioned indication information of above-mentioned positional information data designated piece

Described the 3rd control device provides control signal according to above-mentioned indication information to above-mentioned first and second memory access control apparatus when data storage request produces, this control signal produces by this way, after the data block in second memory by above-mentioned positional information appointment is written to first memory, data in the data register are written to second memory, and data are written in the second memory from first memory then.

5, according to the system of claim 4, it is characterized in that also having a device, be used for the address value from address register output being proofreaied and correct according to the length of the data of require storage,

Above-mentioned first memory is the remaining data (not comprising the data of storing from data register) that starting point is sequentially read a data block with the address of above-mentioned correction,

The storage that above-mentioned second memory is followed from the data of above-mentioned data register will sequentially deposit in from the data of first memory.

6, an access method of storage that is used for signal conditioning package, this device have one and are divided into some first memory; With a second memory, be used for the duplicating of partial data of first memory being stored being the unit basis with the data block, this second memory can is characterized in that this access method of storage comprises with than the access of first memory faster speed:

The first step when a data storage request produces, is judged duplicating whether in second memory corresponding to the data block of memory address;

Second step, when in the first step, judge corresponding to the data block of memory address duplicate not in second memory the time, designated storage area stores duplicating of this data block in second memory;

In the 3rd step, before from first memory, being sent to this data block in the second memory, the data of above-mentioned memory requirement are written in the zone of appointment; With

In the 4th step, the remaining data of a data block of reading from first memory (data that do not comprise above-mentioned memory requirement) is written in the zone of appointment in the second memory.

7, according to the method for claim 6, wherein from first memory, only read out in the remaining data in the data block, thereby can begin to be sequentially written in the second memory from the data on the next address of the data of above-mentioned memory requirement.

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