[go: up one dir, main page]

CN2929733Y - test board - Google Patents

test board Download PDF

Info

Publication number
CN2929733Y
CN2929733Y CNU2006201212484U CN200620121248U CN2929733Y CN 2929733 Y CN2929733 Y CN 2929733Y CN U2006201212484 U CNU2006201212484 U CN U2006201212484U CN 200620121248 U CN200620121248 U CN 200620121248U CN 2929733 Y CN2929733 Y CN 2929733Y
Authority
CN
China
Prior art keywords
pin
electrically connected
test
test board
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNU2006201212484U
Other languages
Chinese (zh)
Inventor
林保炜
李清安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wistron Corp
Original Assignee
Wistron Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wistron Corp filed Critical Wistron Corp
Priority to CNU2006201212484U priority Critical patent/CN2929733Y/en
Application granted granted Critical
Publication of CN2929733Y publication Critical patent/CN2929733Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

The utility model relates to a survey test panel for the connection situation of the pin of the slot of test mainboard or connector. The utility model discloses a survey test panel includes a plurality of MOSFET components and a plurality of electrical property contact, wherein utilizes a plurality of electrical property contacts to be connected with the slot or the connector of survey test panel and mainboard to test the connection situation of the pin of slot or connector with a plurality of MOSFET components.

Description

测试板test board

技术领域technical field

本实用新型有关一种主机板的插槽或连接器的测试板,特别是有关于一种利用多个MOSFET元件作为测试元件的测试板。The utility model relates to a test board for a socket or a connector of a main board, in particular to a test board using a plurality of MOSFET elements as test elements.

背景技术Background technique

在主机板的制造过程当中,主机板的各部零件都需要事先测试是否正常,避免在出货之后才发生问题,而造成制造者的重大损失。During the manufacturing process of the mainboard, each part of the mainboard needs to be tested to see if it is normal in advance, so as to avoid problems occurring after shipment and cause heavy losses to the manufacturer.

在先前技术当中,当要测试主机板的插槽(或连接器)是否能正常运作时,例如测试是否有空焊、冷焊、断路、短路或其他类似异常情形时,通常是借助一测试工具(test jet)利用电容感应的方式进行测试。但是用此测试方式只能测试出插槽的信号接脚(signal pin),而电源接脚(power pin)与接地接脚(ground pin)都因为电路的设计上有并联的情况,因此除非所有的电源接脚或所有的接地接脚都异常,否则无法以电容感应的方式正确地测试出来。In the prior art, when it is necessary to test whether the slot (or connector) of the mainboard can operate normally, for example, to test whether there is empty soldering, cold soldering, open circuit, short circuit or other similar abnormal conditions, it is usually with the help of a test tool (test jet) is tested by capacitive sensing. However, this test method can only test the signal pin of the slot, and the power pin and ground pin are connected in parallel due to the circuit design, so unless all If the power pin or all the ground pins are abnormal, otherwise it cannot be correctly tested by capacitive sensing.

由于电源接脚及接地接脚的数量通常约占主机板的插槽所有接脚的半数,因此借助先前技术,大约只能够测试一半的接脚。同样地,在先前技术中,亦有使用高阻抗电阻或是二极管来代替电容感应方式以进行测试,然而此种测试方式同样会因电路并联的问题而无法正确地测试电源接脚及接地接脚。Since the number of power pins and ground pins usually accounts for about half of all the pins of the motherboard slot, only about half of the pins can be tested with the prior art. Similarly, in the prior art, high-impedance resistors or diodes are also used instead of capacitive sensing methods for testing. However, this test method also cannot correctly test the power pins and ground pins due to the problem of parallel connection of circuits. .

在先前技术当中还有一种测试主机板的插槽的方式,就是插上存储器模块或PCI界面卡等实际要在该插槽运作的模块,来对插槽实际地进行测试。但是这种测试方式由于需要使用实际的存储器模块或PCI界面卡,因此所需成本较高,而且存储器模块或PCI界面卡也有使用期限的问题,因此这种测试方式对于制造者来说会有许多的不便。In the prior art, there is also a method of testing the slot of the mainboard, which is to plug in a memory module or a PCI interface card, etc., which will actually operate in the slot, to actually test the slot. But this test mode needs to use actual memory module or PCI interface card, so required cost is higher, and memory module or PCI interface card also have the problem of service life, so this test mode will have many problems for manufacturer. the inconvenience.

因此实在有需要提供一种新型的测试工具来解决先前技术中的所发生的问颗。Therefore, it is really necessary to provide a novel test tool to solve the problems in the prior art.

实用新型内容Utility model content

本实用新型的目的是提供一种测试板,该测试板可以测试主机板的插槽或连接器的所有接脚。The purpose of the utility model is to provide a test board, which can test the slots of the motherboard or all pins of the connector.

为达成上述的目的,本实用新型提供一种测试板,用于测试一主机板的一插槽或一连接器的多个接脚的连接状况,其中该多个接脚包括至少一电源接脚、至少一接地接脚、至少一信号接脚以及至少一未连接接脚,该测试板包括:一电路板;多个金属氧化半导体场效应晶体管(MOSFET)元件,设置于该电路板上,其中每一MOSFET元件包括一栅极、一漏极及一源极;以及多个电性接点,设置于该电路板上,用以当该测试板插置于该插槽或该连接器中时,使得该多个MOSFET元件电性连接至该多个接脚,以供测试该多个接脚的连接状况。In order to achieve the above object, the utility model provides a test board for testing the connection status of a slot of a motherboard or a plurality of pins of a connector, wherein the plurality of pins include at least one power pin , at least one ground pin, at least one signal pin and at least one unconnected pin, the test board includes: a circuit board; a plurality of metal oxide semiconductor field effect transistor (MOSFET) elements, arranged on the circuit board, wherein Each MOSFET element includes a gate, a drain, and a source; and a plurality of electrical contacts arranged on the circuit board for when the test board is inserted into the slot or the connector, The plurality of MOSFET elements are electrically connected to the plurality of pins for testing the connection status of the plurality of pins.

举例而言,MOSFET元件的栅极可与作为控制接脚的未连接接脚电性连接;漏极与电源接脚电性连接;并且源极与信号接脚电性连接。或者,MOSFET元件的栅极与控制接脚电性连接;漏极与信号接脚电性连接;并且源极与接地接脚电性连接。又或者,MOSFET元件的栅极与控制接脚电性连接;漏极与较高电位的信号接脚电性连接;并且源极与较低电位的信号接脚电性连接。For example, the gate of the MOSFET element can be electrically connected to an unconnected pin as a control pin; the drain is electrically connected to a power pin; and the source is electrically connected to a signal pin. Alternatively, the gate of the MOSFET element is electrically connected to the control pin; the drain is electrically connected to the signal pin; and the source is electrically connected to the ground pin. Alternatively, the gate of the MOSFET element is electrically connected to the control pin; the drain is electrically connected to the higher potential signal pin; and the source is electrically connected to the lower potential signal pin.

此外,本实用新型的测试板可进一步包括至少一二极管元件来测试插槽或连接器的复数接脚的连接状况,其中每一二极管元件的一端是与控制接脚电性连接,而另一端是与信号接脚电性连接。In addition, the test board of the present invention may further include at least one diode element to test the connection status of multiple pins of the slot or connector, wherein one end of each diode element is electrically connected to the control pin, and the other end is electrically connected to the control pin. Electrically connected with the signal pin.

本实用新型的测试板是利用多个MOSFET元件来作为测试元件。本实用新型借助MOSFET元件的特性,经由电路设计使各个MOSFET元件分别与插槽的多个接脚中的电源接脚、信号接脚、未连接接脚或接地接脚电性连接,便可方便地实现测试插槽的所有接脚。The test board of the utility model utilizes a plurality of MOSFET elements as test elements. The utility model makes use of the characteristics of the MOSFET components to electrically connect each MOSFET component with the power supply pins, signal pins, unconnected pins or grounding pins in the multiple pins of the slot through circuit design, which can be convenient Ground implements all pins of the test socket.

附图说明Description of drawings

图1是本实用新型的一实施例的测试板的结构示意图。FIG. 1 is a schematic structural view of a test board according to an embodiment of the present invention.

图2是本实用新型的另一实施例的测试板的结构示意图。Fig. 2 is a schematic structural view of a test board according to another embodiment of the present invention.

图3是本实用新型的测试板与一外部测试机台的配置示意图。FIG. 3 is a schematic diagram of the configuration of the test board and an external test machine of the present invention.

图4是插槽的多个接脚的接脚类别示意图。FIG. 4 is a schematic diagram of pin types of multiple pins of a slot.

图5是本实用新型的MOSFET元件的一示意图。Fig. 5 is a schematic diagram of the MOSFET element of the present invention.

图6是本实用新型的MOSFET元件的一电路连接示意图。FIG. 6 is a schematic diagram of a circuit connection of the MOSFET element of the present invention.

图7是本实用新型的MOSFET元件的另一电路连接示意图。FIG. 7 is a schematic diagram of another circuit connection of the MOSFET element of the present invention.

图8是本实用新型的二极管元件的一电路连接示意图。FIG. 8 is a schematic diagram of a circuit connection of the diode element of the present invention.

具体实施方式Detailed ways

为让本实用新型的上述和其他目的、特征和优点能更明显易懂,现特举出利用本实用新型技术内容的实施例,并配合所附图进行详细说明如下。In order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the embodiments utilizing the technical contents of the present invention are specifically cited and described in detail as follows in conjunction with the accompanying drawings.

请先参考图1关于本实用新型的一实施例的测试板的结构示意图。如图1所示,在本实用新型的一实施例中,本实用新型的测试板10包括一电路板20。电路板20上设置有多个金属氧化半导体场效应晶体管(MOSFET)元件21、多个电性接点23以及规划好的多个MOSFET元件21的连接电路。Please refer to FIG. 1 for a schematic structural diagram of a test board according to an embodiment of the present invention. As shown in FIG. 1 , in an embodiment of the present invention, the test board 10 of the present invention includes a circuit board 20 . The circuit board 20 is provided with a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) elements 21 , a plurality of electrical contacts 23 and a planned connection circuit of the plurality of MOSFET elements 21 .

接着请参考图2关于本实用新型的另一实施例的测试板的结构示意图。如图2所示,本实用新型另提供一种测试板10’作为测试板10的替代实施例。测试板10’除了包括电路板20’、多个MOSFET元件21’以及多个电性接点23’外,也同时具有多个二极管元件22以作为测试元件。Next, please refer to FIG. 2 for a schematic structural diagram of a test board according to another embodiment of the present invention. As shown in Fig. 2, the utility model further provides a test board 10' as an alternative embodiment of the test board 10. In addition to the circuit board 10', a plurality of MOSFET elements 21' and a plurality of electrical contacts 23', the test board 10' also has a plurality of diode elements 22 as test elements.

接着请参考图3关于测试板10(或测试板10’)与一外部测试机台的配置示意图。如图3所示,主机板31上设置有连接装置,连接装置可以为插槽或是连接器,用来与存储器模块(图未示)或其他类似的界面卡相连接。在本实施例中,连接装置以插槽311为例,但本实用新型并不以此为限。同时,在本实用新型的一实施例中,测试板10的电路板20是配合插槽311的大小所制成。多个MOSFET元件21可用来测试主机板31的插槽311的多个接脚312的连接状况,例如测试是否有空焊、冷焊、断路、短路或其他类似异常情形。测试板10具有多个电性接点23,用来与主机板31的插槽311或是连接器相连接,使得多个MOSFET元件21可以电性连接到多个接脚312,以供测试多个接脚312的连接状况。在插槽311与测试板10相连接之后,测试机台32可利用探针321来测试插槽311的多个接脚312的脚座,如此一来就可以测试出插槽311各个接脚312的连接状况。但上述测试机台32利用探针321的测试功能或方式并非本实用新型的重点所在,因此不在此赘述。Next, please refer to FIG. 3 for a schematic configuration diagram of the test board 10 (or test board 10') and an external test machine. As shown in FIG. 3 , a connection device is provided on the motherboard 31 , which can be a slot or a connector for connecting with a memory module (not shown) or other similar interface cards. In this embodiment, the connecting device is the slot 311 as an example, but the present invention is not limited thereto. Meanwhile, in an embodiment of the present invention, the circuit board 20 of the test board 10 is made to match the size of the slot 311 . The plurality of MOSFET elements 21 can be used to test the connection status of the plurality of pins 312 of the socket 311 of the motherboard 31 , for example, to test whether there is no solder joint, cold solder joint, open circuit, short circuit or other similar abnormal conditions. The test board 10 has a plurality of electrical contacts 23, which are used to connect with the slots 311 or connectors of the motherboard 31, so that a plurality of MOSFET elements 21 can be electrically connected to a plurality of pins 312 for testing a plurality of The connection status of pin 312. After the socket 311 is connected to the test board 10, the testing machine 32 can use the probes 321 to test the sockets of the plurality of pins 312 of the socket 311, so that each pin 312 of the socket 311 can be tested. connection status. However, the test function or method of the test machine 32 using the probe 321 is not the key point of the present invention, so it will not be repeated here.

如图3所示,插槽311包括多个接脚312。然而,需注意的是,多个接脚312的脚数及用途在不同的插槽311中可能有所改变。举例而言,在本实用新型的一实施例中,如图4的接脚类别示意图所示,多个接脚312可以包括至少一信号接脚(signal pin)41、至少一电源接脚(power pin)42、至少一接地接脚(ground pin)43与至少一未连接接脚(non-connected pin)44。其中,未连接接脚44可以包括至少一控制接脚441,以用来传递控制信号。该控制信号为测试机台32所发出的信号,用以控制MOSFET元件21的导通或关闭。As shown in FIG. 3 , the socket 311 includes a plurality of pins 312 . However, it should be noted that the number and purpose of the plurality of pins 312 may vary in different slots 311 . For example, in one embodiment of the present invention, as shown in the schematic diagram of pin categories in FIG. 4 , the multiple pins 312 may include at least one signal pin (signal pin) 41, at least one power pin pin) 42, at least one ground pin (ground pin) 43 and at least one non-connected pin (non-connected pin) 44. Wherein, the unconnected pins 44 may include at least one control pin 441 for transmitting control signals. The control signal is a signal sent by the test machine 32 to control the MOSFET element 21 to be turned on or off.

接着请参考图5,其是本实用新型的各个MOSFET元件21的示意图。如图5所示,MOSFET元件21具有三个接脚,分别为栅极211、源极212及漏极213。Next, please refer to FIG. 5 , which is a schematic diagram of each MOSFET element 21 of the present invention. As shown in FIG. 5 , the MOSFET element 21 has three pins, namely a gate 211 , a source 212 and a drain 213 .

为了要让MOSFET元件21能够成为测试插槽311各多个接脚312的测试元件,设置于电路板20上的各个MOSFET元件21的连接电路需经过设计。亦即,各个MOSFET元件21的栅极211都与控制接脚441电性连接,用以接收控制信号。控制接脚441是利用插槽311的多个接脚312中的未连接接脚44来作为与栅极211的连接接脚。而各个MOSFET元件21的源极212及漏极213,就分别与插槽311的多个接脚312中的电源接脚42、接地接脚43或信号接脚41电性连接。在本实施例中,测试时只要测试机台32分别对MOSFET元件21发出导通或关闭的控制信号,再用探针321来测量多个接脚312的脚座,就可以得知插槽311的信号接脚41、电源接脚42或是接地接脚43是否连接正常。In order to allow the MOSFET element 21 to be a test element for testing the multiple pins 312 of the socket 311 , the connection circuit of each MOSFET element 21 disposed on the circuit board 20 needs to be designed. That is, the gate 211 of each MOSFET element 21 is electrically connected to the control pin 441 for receiving the control signal. The control pin 441 utilizes the unconnected pin 44 among the plurality of pins 312 of the socket 311 as a connection pin to the gate 211 . The source 212 and the drain 213 of each MOSFET element 21 are respectively electrically connected to the power pin 42 , the ground pin 43 or the signal pin 41 among the plurality of pins 312 of the socket 311 . In this embodiment, as long as the test machine 32 sends a control signal to turn on or turn off the MOSFET element 21 respectively during the test, and then uses the probe 321 to measure the sockets of the plurality of pins 312, the slot 311 can be known. Whether the signal pin 41, the power pin 42 or the ground pin 43 is connected properly.

需注意的是,在MOSFET元件21中,如果源极212的电位高于漏极213的电位,当栅极211关闭时,源极212与漏极213也可能会导通。若是在进行测量时有上述的状况就无法达到精确的测试结果,因此漏极213的电位必须高于源极212的电位。一般而言,在插槽311中的信号接脚41、电源接脚42或是接地接脚43之间的电位关系为电源接脚42的电位高于信号接脚41的电位;信号接脚41的电位又高于接地接脚43的电位。It should be noted that, in the MOSFET device 21 , if the potential of the source 212 is higher than that of the drain 213 , when the gate 211 is turned off, the source 212 and the drain 213 may also be turned on. If the above conditions exist during the measurement, accurate test results cannot be achieved, so the potential of the drain 213 must be higher than the potential of the source 212 . Generally speaking, the potential relationship among the signal pin 41 , the power pin 42 or the ground pin 43 in the slot 311 is that the potential of the power pin 42 is higher than that of the signal pin 41 ; the signal pin 41 The potential of the ground pin 43 is higher than the potential of the ground pin 43 .

因此,如图6的MOSFET元件21与多个接脚312的一电路连接示意图所示,当漏极213电性连接电源接脚42时,源极212必须要电性连接信号接脚41。或者,如图7的MOSFET元件21与多个接脚312的另一电路连接示意图所示,若漏极213电性连接信号接脚41,源极212就必须电性连接接地接脚43。Therefore, as shown in a schematic diagram of a circuit connection between the MOSFET element 21 and multiple pins 312 in FIG. 6 , when the drain 213 is electrically connected to the power pin 42 , the source 212 must be electrically connected to the signal pin 41 . Alternatively, as shown in another circuit connection diagram of the MOSFET element 21 and multiple pins 312 in FIG. 7 , if the drain 213 is electrically connected to the signal pin 41 , the source 212 must be electrically connected to the ground pin 43 .

需注意的是,如果漏极213电性连接电源接脚42并且源极212电性连接接地接脚43,则可能会因为电源接脚42与接地接脚43的电路在最初设计时,会分别有并联的问题而无法准确地进行测试。It should be noted that if the drain 213 is electrically connected to the power pin 42 and the source 212 is electrically connected to the ground pin 43, it may be because the circuits of the power pin 42 and the ground pin 43 are initially designed, respectively. There is a parallel problem and cannot be tested accurately.

在另一方面,若在确定两个信号接脚41之间的电位高低的情况下,MOSFET元件21的漏极213可与较高电位的信号接脚41电性连接;源极212可与较低电位的信号接脚41电性连接。若是无法确定两个信号接脚41之间的电位高低,则无法让漏极213与源极212同时电性连接两个信号接脚41,因为可能会发生上述源极212的电位高于漏极213的电位的情况。On the other hand, if the potential level between the two signal pins 41 is determined, the drain 213 of the MOSFET element 21 can be electrically connected to the higher potential signal pin 41; the source 212 can be connected to the higher potential The low potential signal pin 41 is electrically connected. If the potential level between the two signal pins 41 cannot be determined, the drain 213 and the source 212 cannot be electrically connected to the two signal pins 41 at the same time, because the potential of the source 212 may be higher than the drain. 213 potential situation.

此外,当使用如图2所示的测试板10’来进行测试时,在电路设计上可以先将多个MOSFET元件21与插槽311的多个信号接脚41、多个电源接脚42以及多个接地接脚43按照上述的方法做作配对电性连接。若配对电性连接后,仍有剩下的信号接脚41尚未连接,则剩下的信号接脚41即与多个二极管元件22电性连接,以进行测试。亦即,如图8的二极管元件与多个接脚的电路连接示意图所示,二极管元件22的两端分别电性连接插槽311的控制接脚441及信号接脚41。接着,再以测试机台32用同样的方式测试,即可得知接在二极管元件22上的信号接脚41是否正常导通。In addition, when using the test board 10' as shown in FIG. The plurality of grounding pins 43 are electrically connected in pairs according to the above-mentioned method. If there are still remaining signal pins 41 not connected after the paired electrical connection, then the remaining signal pins 41 are electrically connected to the plurality of diode elements 22 for testing. That is, as shown in the circuit connection schematic diagram of the diode element and multiple pins in FIG. 8 , both ends of the diode element 22 are electrically connected to the control pin 441 and the signal pin 41 of the socket 311 respectively. Then, test in the same way with the testing machine 32 to know whether the signal pin 41 connected to the diode element 22 is normally conducted.

因此,借助本实用新型的测试板10或测试板10’并利用上述的电路连接方式,配合测试机台32即可将插槽311的多个接脚312的连接状况全部测试出来,而解决先前技术所遇到的问题。Therefore, with the help of the test board 10 or the test board 10' of the present utility model and utilizing the above-mentioned circuit connection method, the connection status of the plurality of pins 312 of the slot 311 can be fully tested by cooperating with the test machine 32, so as to solve the previous problems. problems encountered by technology.

综上所述,本实用新型无论就目的、手段及功效,均显示其迥异于先前技术的特征。但应注意的是,上述诸多实施例仅是为便于说明而举的实例,本实用新型所主张的权利范围自应以本申请权利要求范围所述为准,而非仅限于上述实施例。To sum up, the utility model shows its characteristics that are very different from the prior art in terms of purpose, means and efficacy. However, it should be noted that the above-mentioned embodiments are only examples for the convenience of description, and the scope of rights claimed by the utility model should be based on the scope of the claims of this application, rather than being limited to the above-mentioned embodiments.

Claims (9)

1.一种测试板,用于测试一主机板的一插槽或一连接器的多个接脚的连接状况,其中该多个接脚包括至少一电源接脚、至少一接地接脚、至少一信号接脚以及至少一未连接接脚,其特征在于该测试板包括:1. A test board, used to test a socket of a motherboard or a connection condition of a plurality of pins of a connector, wherein the plurality of pins include at least one power pin, at least one ground pin, at least A signal pin and at least one unconnected pin, characterized in that the test board includes: 一电路板;a circuit board; 多个金属氧化半导体场效应晶体管(MOSFET)元件,设置于该电路板上,其中每一MOSFET元件包括一栅极、一漏极及一源极;以及a plurality of metal-oxide-semiconductor field-effect transistor (MOSFET) elements disposed on the circuit board, wherein each MOSFET element includes a gate, a drain, and a source; and 多个电性接点,设置于该电路板上,用以当该测试板插置于该插槽或该连接器中时,使得该多个MOSFET元件电性连接至该多个接脚,以供测试该多个接脚的连接状况。A plurality of electrical contacts are arranged on the circuit board, so that when the test board is inserted into the slot or the connector, the plurality of MOSFET elements are electrically connected to the plurality of pins for Test the connection status of the plurality of pins. 2.如权利要求1所述的测试板,其特征在于该至少一未连接接脚包含至少一控制接脚,并且该多个MOSFET元件的每一MOSFET元件的该栅极是与该控制接脚电性连接。2. The test board according to claim 1, wherein the at least one unconnected pin comprises at least one control pin, and the gate of each MOSFET element of the plurality of MOSFET elements is connected to the control pin electrical connection. 3.如权利要求2所述的测试板,其特征在于至少有一MOSFET元件的该漏极是与该至少一电源接脚电性连接,并且该源极是与该至少一信号接脚电性连接。3. The test board according to claim 2, wherein the drain of at least one MOSFET element is electrically connected to the at least one power pin, and the source is electrically connected to the at least one signal pin . 4.如权利要求2所述的测试板,其特征在于至少有一MOSFET元件的该漏极是与该至少一信号接脚电性连接,并且该源极是与该至少一接地接脚电性连接。4. The test board according to claim 2, wherein the drain of at least one MOSFET element is electrically connected to the at least one signal pin, and the source is electrically connected to the at least one ground pin . 5.如权利要求2所述的测试板,其特征在于至少有一MOSFET元件的该漏极是与该至少一信号接脚的一部分信号接脚电性连接,并且该源极是与该至少一信号接脚的另一部分信号接脚电性连接,并且与该漏极电性连接的该信号接脚的电位是大于与该源极电性连接的信号接脚的电位。5. The test board according to claim 2, wherein the drain of at least one MOSFET element is electrically connected to a part of the at least one signal pin, and the source is connected to the at least one signal pin. Another part of the pins is electrically connected to the signal pin, and the potential of the signal pin electrically connected to the drain is greater than the potential of the signal pin electrically connected to the source. 6.如权利要求1所述的测试板,其特征在于该至少一未连接接脚包含至少一控制接脚,并且该测试板进一步包括至少一二极管元件设置于该电路板上,其中每一二极管元件的一端是与该控制接脚电性连接,而另一端是与该至少一信号接脚的其中一信号接脚电性连接。6. The test board according to claim 1, wherein the at least one unconnected pin comprises at least one control pin, and the test board further comprises at least one diode element disposed on the circuit board, wherein each diode One end of the component is electrically connected to the control pin, and the other end is electrically connected to one of the at least one signal pin. 7.如权利要求2所述的测试板,其特征在于该至少一控制接脚传递控制信号,以控制该多个MOSFET元件的导通或关闭。7. The test board as claimed in claim 2, wherein the at least one control pin transmits a control signal to control the turn-on or turn-off of the plurality of MOSFET elements. 8.如权利要求6所述的测试板,其特征在于该至少一控制接脚传递控制信号,以控制该至少一二极管元件的导通或关闭。8. The test board as claimed in claim 6, wherein the at least one control pin transmits a control signal to control the at least one diode element to be turned on or off. 9.如权利要求7或8所述的测试板,其特征在于该控制信号是由一外部的测试机台所控制。9. The test board according to claim 7 or 8, wherein the control signal is controlled by an external test machine.
CNU2006201212484U 2006-06-19 2006-06-19 test board Expired - Fee Related CN2929733Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2006201212484U CN2929733Y (en) 2006-06-19 2006-06-19 test board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2006201212484U CN2929733Y (en) 2006-06-19 2006-06-19 test board

Publications (1)

Publication Number Publication Date
CN2929733Y true CN2929733Y (en) 2007-08-01

Family

ID=38308115

Family Applications (1)

Application Number Title Priority Date Filing Date
CNU2006201212484U Expired - Fee Related CN2929733Y (en) 2006-06-19 2006-06-19 test board

Country Status (1)

Country Link
CN (1) CN2929733Y (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101464490B (en) * 2007-12-17 2010-12-22 中芯国际集成电路制造(上海)有限公司 General-purpose test board and its use method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101464490B (en) * 2007-12-17 2010-12-22 中芯国际集成电路制造(上海)有限公司 General-purpose test board and its use method

Similar Documents

Publication Publication Date Title
US7789714B2 (en) Connector assembly
US20080315902A1 (en) Test device, test card, and test system
CN103207366A (en) Test system and test method of printed circuit board assembly
US8024630B2 (en) Debugging module for electronic device and method thereof
CN111104278B (en) SAS connector conduction detection system and method thereof
CN101859750B (en) The Apparatus and system of the dedicated pin on ic substrate
CN209418157U (en) It is a kind of for testing the test board and test equipment of storage card
CN100529765C (en) Reset device of test accesses terminal port of JTAG chain circuit used on board
CN112130098A (en) Connection detection device, mainboard and terminal
CN102339251A (en) Test system and USB (universal serial bus) interface test connection card thereof
CN101437133A (en) Test switching device
US7805599B2 (en) Expansion device for BIOS chip
CN2929733Y (en) test board
CN103033735B (en) Circuit test interface and test method
CN103901249A (en) Interface signal test device
CN102411528A (en) MXM (Mobile PCI-Express Module)-interface testing-connecting card and testing system provided with same
CN102141952B (en) Device for testing system management bus
CN108255655A (en) A kind of PCIe is stuck in position detection board
CN102567167A (en) Testing card and testing system for mSATA (serial advanced technology attachment) interface
CN101162254B (en) CPU socket test device
TWI413905B (en) Apparatus for testing usb ports
CN114077564B (en) C-type universal serial bus adapter plate
CN103901953A (en) Mainboard
CN102789440A (en) Data transmission system
CN219496452U (en) Integrated test circuit board and pulling load test fixture thereof

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
EE01 Entry into force of recordation of patent licensing contract

Assignee: Wistron (Kunshan) Co., Ltd.

Assignor: Weichuang Zitong Co., Ltd.

Contract record no.: 2010990000404

Denomination of utility model: Applied module of test plate

Granted publication date: 20070801

License type: Exclusive License

Record date: 20100622

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070801

Termination date: 20150619

EXPY Termination of patent right or utility model