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CN2768065Y - Blade Servo - Google Patents

Blade Servo Download PDF

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Publication number
CN2768065Y
CN2768065Y CN 200520002440 CN200520002440U CN2768065Y CN 2768065 Y CN2768065 Y CN 2768065Y CN 200520002440 CN200520002440 CN 200520002440 CN 200520002440 U CN200520002440 U CN 200520002440U CN 2768065 Y CN2768065 Y CN 2768065Y
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CN
China
Prior art keywords
pin
signal
pins
pci
channel differential
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Expired - Lifetime
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CN 200520002440
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Chinese (zh)
Inventor
倪孝祖
吴政翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quanta Computer Inc
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Quanta Computer Inc
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Priority to CN 200520002440 priority Critical patent/CN2768065Y/en
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Publication of CN2768065Y publication Critical patent/CN2768065Y/en
Anticipated expiration legal-status Critical
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Abstract

The blade servo system comprises a middle flat plate and a blade server. The blade server comprises a second connector for electrically connecting with the first connector of the middle panel. The second connector has a plurality of pins meeting specific specifications, wherein the specific specifications comprise specifications meeting the characteristics of VHDM-HSD 8 row, Female, Right-Angle and 92 pins; the specification of 8 single rows, 2 shielding rows, Femal, Right-Angle and 99 pin characteristics is met; meet the specification of High Speed, Male, double row and 84 pin characteristics; meet the specification of High Speed, Male, double row and 120 pin characteristics; and meet the specifications of High Speed, Male, double row and 40-pin characteristics.

Description

Blade-point servo system
Technical field
The utility model relates to a kind of blade-point servo system, and particularly relevant for a kind of blade-point servo system that the position and the function of all pins on the cutter point server are locked.
Background technology
Blade-point servo system now is a kind of high density (High-density) system, usually can hold several cutter point servers (Server Blade), and every cutter point server is electrically connected to middle dull and stereotyped (Middle Blade Board) by the connector with the design of high density pin.These pins system is in order to transmission power supply signal, high speed signal, low speed signal and universal serial bus (Universal SerialBus, USB) signal etc.
Yet the design of blade-point servo system often must obtain a balance in dull and stereotyped usage space at performance that promotes cutter point server and saving cutter point server.Therefore, utilize the connector with suitable pin definition to provide cutter point server required function in the finite space, its importance more is far more than provides high speed transmission of signals usefulness.
Moreover, imitating in order to prevent other manufacturer, the deviser is necessary all above-mentioned pin position and functions of locking on the connector of cutter point server, makes cutter point server counterfeit being suitable in addition that defines the pin manufacturing voluntarily.
Summary of the invention
In view of this, the purpose of this utility model is providing a kind of cutter point server exactly, is locked by position and function with all pins of cutter point server connector, imitates to avoid unworthy manufacturer.
According to the purpose of this utility model, a kind of blade-point servo system is proposed, flat board and cutter point server in the middle of it comprises.Middle flat board comprises first connector, and cutter point server comprises second connector, in order to electrically connect first connector.Second connector has the many branch connecting pins that meet VHDM-HSD 8 row, Female, Right-Angle and 92 pin characteristic specifications.Therefore, can avoid other manufacturer to copy blade-point servo system of the present utility model by the position and the function of these pins of locking.
According to the purpose of this utility model, a kind of blade-point servo system is proposed, flat board and cutter point server in the middle of it comprises.Middle flat board comprises first connector, and cutter point server comprises second connector, in order to electrically connect first connector.Second connector has the many branch connecting pins that meet 8 single rows, 2 shieldingrows, Female, Right-Angle and 99 pin characteristic specifications.Therefore, can avoid other manufacturer to copy blade-point servo system of the present utility model by the position and the function of these pins of locking.
According to the purpose of this utility model, a kind of blade-point servo system is proposed, flat board and cutter point server in the middle of it comprises.Middle flat board comprises first connector, and cutter point server comprises second connector, in order to electrically connect first connector.Second connector has the many branch connecting pins that meet High Speed, Male, double row and 84 pin characteristic specifications.Therefore, can avoid other manufacturer to copy blade-point servo system of the present utility model by the position and the function of these pins of locking.
According to the purpose of this utility model, a kind of blade-point servo system is proposed, flat board and cutter point server in the middle of it comprises.Middle flat board comprises first connector, and cutter point server comprises second connector, in order to electrically connect first connector.Second connector has the many branch connecting pins that meet High Speed, Male, double row and 120 pin characteristic specifications.Therefore, can avoid other manufacturer to copy blade-point servo system of the present utility model by the position and the function of these pins of locking.
According to the purpose of this utility model, a kind of blade-point servo system is proposed, flat board and cutter point server in the middle of it comprises.Middle flat board comprises first connector, and cutter point server comprises second connector, in order to electrically connect first connector.Second connector has the many branch connecting pins that meet High Speed, Male, double row and 40 pin characteristic specifications.Therefore, can avoid other manufacturer to copy blade-point servo system of the present utility model by the position and the function of these pins of locking.
Description of drawings
The 1st figure illustrates according to a preferred embodiment blade-point servo system structure calcspar of the present utility model;
2A figure illustrates the first specification pin arrangement plan of second connector among the 1st figure;
2B figure illustrates the second specification pin arrangement plan of second connector among the 1st figure;
2C figure illustrates the 3rd specification pin arrangement plan of second connector among the 1st figure;
2D figure illustrates the 4th specification pin arrangement plan of second connector among the 1st figure.
2E figure illustrates the 5th specification pin arrangement plan of second connector among the 1st figure
2F figure illustrates another pin arrangement plan of the 5th specification of second connector among the 1st figure.
[main element label declaration]
100: blade-point servo system
110: middle dull and stereotyped
112: the first connectors
114: slot
120: cutter point server
122: the second connectors
124: pin
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Please refer to the 1st figure, it illustrates according to a preferred embodiment blade-point servo system of the utility model structure side view.Flat board 110 and cutter point server 120 in the middle of blade-point servo system 100 comprises.Middle dull and stereotyped 110 comprise first connector 112, and cutter point server 120 comprises second connector 122, in order to electrically connect first connector 112.And second connector 122 have many branch connecting pins 124, in order to a plurality of slots 114 of first connector 112 of pegging graft.Next just be illustrated with the pin position and the function of all size of second connector 122.
Please refer to 2A figure, it illustrates the first specification pin arrangement plan of second connector 122 among the 1st figure.Above-mentioned first specification is the Low_EPT_CONN specification that meets STARCONN company: characteristic is the connector of HardMetric 2.0mm, 8 single rows, 2 shielding rows, Female, Right-Angle, DIP and 99 pins, for example connector of model EPT 246-31300-15.Wherein, EPT represent the precise electronic technology (Electronic Precision Technology, EPT).Second connector 122 has 88 branch connecting pins 124 such as A1～A11, B1～B11, C1～C11, D1～D11, E1～E11, F1～F11, G1～G11 and H1～H11.
The A1 pin is that cutter point server exists signal Present pin.A2 pin and A3 pin are small computer system interface (Small Computer System Interface, SCSI) request (Request) signal LVREQBM and LVREQBP pin.A4～A9 pin is that SCSI channel byte signal is to (Channel Byte Signal Pairs) LVSCDBP11, LVSCDBM11, LVSCDBM8, LVSCDBP8, LVSCDBM10, LVSCDBP10 pin.B8～B9 pin is that SCSI channel byte signal is to LVSCDBM9 and LVSCDBP9 pin.E1～E2 pin is that SCSI channel byte signal is to LVSCDBM5 and LVSCDBP5 pin.E4～E7 pin is that channel byte signal is to LVSCDBM6, LVSCDBP6, LVSCDBM7 and LVSCDBP7.F2～F11 pin is that channel byte signal is to LVSCDBM0, LVSCDBP0, LVSCDBM1, LVSCDBP1, LVSCDBM2, LVSCDBP2, LVSCDBM3, LVSCDBP3, LVSCDBM4 and LVSCDBP4.G2～G9 pin is that SCSI channel byte signal is to LVSCDBM12, LVSCDBP12, LVSCDBM13, LVSCDBP13, LVSCDBM14, LVSCDBP14, LVSCDBM15 and LVSCDBP15 pin.B4～B5 pin is SCSI input/output signal LVIOBM and LVIOBP pin.B6～B7 pin is to select (Select) signal LVSELBM and LVSELBP pin.C4～C5 pin is SCSI reset signal LVRSTBM and LVRSTBP pin.C6～C7 pin is SCSI information signal LVMSGBM and LVMSGBP pin.C8～C9 pin is scsi command/data (Command/Data) signal LVCDBP and LVCDBM pin.D4～D5 pin is SCSI caution (Attention) signal LVANTBM and LVANTBP pin.
D6～D7 pin is SCSI all-paths-busy (Busy) signal LVBSYBM and LVBSYBP pin.D8～D9 pin is that SCSI confirms (Acknowledge) LVACKBM and LVACKBP signal.The E3 pin is that the induction of SCSI differential wave detects (Differential Sense) input signal DIFSENB pin.E8～E9 pin is SCSI high byte parity checking (High Byte Parity) signal LVSCDBPHM and a LVSCDBPHP pin.G10～G11 pin is SCSI low byte parity checking (Low Byte Parity) signal LVSCDBPLM and a LVSCDBPLP pin.A10～A11 pin, B10～B11 pin, C10～C11 pin, D10～D11 pin and E11 pin are the 12V of system power supply signal pin.The B1 pin is a standby 5V power supply signal 5VSBY pin.The B2 pin is standby 5V pre-charge (Precharge) power supply signal 5VSBY_Pre pin.B3 pin, C2～C3 pin and D3 pin are cutter point server status identification BLD_ID1, BLD_ID0, BLD_ID2 and BLD_ID3 pin.C1 pin and D1 pin are the 5V of system power pin.
The D2 pin is the 12V of a system pre-charge power supply signal pin.The F1 pin is chassis management module (Chassis Management Module, CMM) a flow control cts signal CMM_CTS_M pin.The G1 pin is a CMM flow control RTS signal CMM_RTS_M pin.The H1 pin is a display interface I2C data signal bus D2DATA pin.The H2 pin is a display interface I2C bus clock signal D2CLK pin.The H3 pin is blue shows signal BLD_B pin.The H4 pin is green shows signal BLD_G pin.The H5 pin is red shows signal BLD_R pin.The H6 pin is to show vertical synchronizing signal VSYNC pin.The H7 pin is a reveal competence synchronizing signal HSVNC pin.The H8 pin is a USB negative signal USB-pin.The H9 pin is a USB positive signal USB+ pin.The H10 pin is an I2C bus clock signal I2C_SCL pin.The H11 pin is an I2C data signal bus I2C_SDA pin.In addition, E10 and Y1～Y11 pin is ground connection (GND) pin.
Please refer to 2B figure, it illustrates the second specification pin arrangement plan of second connector 122 among the 1st figure.Above-mentioned second specification is the Upper_5G_CONN specification that meets Teradyne company: characteristic is the connector of VHDM-HSD8 row, 2.0mm, Female, Right-Angle, DIP and 92 pins, for example connector of model MOLEX 74680-0229.Second connector 122 has 80 branch connecting pins 124 such as A1～A10, B1～B10, C1～C10, D1～D10, E1～E10, F1～F10, G1～G10 and H1～H10.
A1, B1 pin are the optical fiber/differential pairing of GIGA network (Differential Pair) 1 sender signal FC_GIGA_TD1N and FC_GIGA_TD1P pin.A2, B2 pin are differential pairing 1 receiver signal FC_GIGA_RD1N of optical fiber/GIGA network and FC_GIGA_RD1P pin.A3, B3 pin are differential pairing 1 receiver signal IB_RDN1_P in Infinite Band main channel and IB_RDP1_P pin.A4, B4 pin are differential pairing 2 receiver signal IB_RDN2_P in Infinite Band main channel and IB_RDP2_P pin.A5, B5 pin are differential pairing 3 receiver signal IB_RDN3_P in Infinite Band main channel and IB_RDP3_P pin.A6, B6 pin are differential pairing 4 receiver signal IB_RDN4_P in Infinite Band main channel and IB_RDP4_P pin.A7, B7 pin are differential pairing 1 receiver signal IB_RDN1_S of Infinite Band subchannel and IB_RDP1_S pin.A8, B8 pin are differential pairing 2 receiver signal IB_RDN2_S of Infinite Band subchannel and IB_RDP2_S pin.
A9, B9 pin are differential pairing 3 receiver signal IB_RDN3_S of Infinite Band subchannel and IB_RDP3_S pin.A10, B10 pin are differential pairing 4 receiver signal IB_RDN4_S of Infinite Band subchannel and IB_RDP4_S pin.C1～C10 pin is a ground connection GND pin.D1, E1 pin are the differential pairing 2 sender signal FC_GIGA_TD2N of optical fiber/GIGA network, FC_GIGA_TD2P pin.D2, E2 pin are the differential pairing 2 receiver signal FC_GIGA_RD2N of optical fiber/GIGA network, FC_GIGA_RD2P pin.D3, E3 pin are differential pairing 1 sender signal IB_TDN1_P in Infinite Band main channel and IB_TDP1_P pin.D4, E4 pin are differential pairing 2 sender signal IB_TDN2_P in Infinite Band main channel and IB_TDP2_P pin.D5, E5 pin are differential pairing 3 sender signal IB_TDN3_P in Infinite Band main channel and IB_TDP3_P pin.D6, E6 pin are differential pairing 4 sender signal IB_TDN4_P in Infinite Band main channel and IB_TDP4_P pin.
D7, E7 pin are differential pairing 1 sender signal IB_TDN1_S of Infinite Band subchannel and IB_TDP1_S pin.D8, E8 pin are differential pairing 2 sender signal IB_TDN2_S of Infinite Band subchannel and IB_TDP2_S pin.D9, E9 pin are differential pairing 3 sender signal IB_TDN3_S of Infinite Band subchannel and IB_TDP3_S pin.D10, E10 pin are differential pairing 4 sender signal IB_TDN4_S of Infinite Band subchannel and IB_TDP4_S pin.F1～F10 pin is a ground connection GND pin.The G1 pin is local bus (Local Bus) function activation 0 a signal F_EN0 pin.The G2 pin is local bus function activation 2 signal F_EN2 pins.G3～G7 pin is local bus data bit [0:4] signal S_AD0～S_AD4 pin.The G8 pin is a PS2 mouse clock signal MSCLK pin.The G9 pin is a PS2 keyboard clock signal KBCLK pin.
The G10 pin is the overall I/O in Infinite Band main channel (General PurposeInput/Output, GPIO) a signal IB_GPIO pin.The H1 pin is that cutter point server engages signal Mated pin.The H2 pin is local bus function activation 1 a signal F_EN1 pin.The H3 pin is a local bus data bit signal S_D0 pin.The H4 pin is local bus gating (Strobe) signal STROBE_B pin.The H5 pin is that (Chassis Management Module CMM) receives flow control signal BLD_RX pin to chassis management module.The H6 pin is a CMM delivery flow rate control signal BLD_TX pin.The H7 pin is that local bus is removed function signal CLEAR pin.The H8 pin is a PS2 mouse data signal MSDATA pin.The H9 pin is a PS2 keyboard data signal KBDATA pin.The H10 pin is an Infinite Band secondary channel GPIO signal IB_GPIO_S pin.
Please refer to 2C figure, it illustrates the 3rd specification pin arrangement plan of second connector 122 among the 1st figure.Above-mentioned the 3rd specification is to meet the Upper_Daughter specification: characteristic is the connector of High Speed, 0.8mm, Male, double row, differential pairs, SMD and 84 pins, for example connector of model SamtecQTE-042-03-F-D-DP-A.Second connector 122 has 84 branch connecting pins 124 such as the 1st pin to the 84 pins.
The 1st pin and the 3rd pin are differential pairing 1 sender signal FC_GIGA_TDN1 of optical fiber/GIGA network and FC_GIGA_TDP1 pin.The 2nd pin and the 4th pin are differential pairing 1 receiver signal FC_GIGA_RDN1 of optical fiber/GIGA network and FC_GIGA_RDP1 pin.The 5th pin and the 7th pin are differential pairing 2 sender signal FC_GIGA_TDN2 of optical fiber/GIGA network and FC_GIGA_TDP2 pin.The 6th pin and the 8th pin are differential pairing 2 receiver signal FC_GIGA_RDN2 of optical fiber/GIGA network and FC_GIGA_RDP2 pin.The 9th pin and the 11st pin are differential pairing 4 receiver signal IB_RDN4_P in Infinite Band main channel and IB_RDP4_P pin.The 10th pin and the 12nd pin are differential pairing 4 receiver signal IB_RDN4_S of Infinite Band subchannel and IB_RDP4_S pin.The 13rd pin and the 15th pin are differential pairing 3 receiver signal IB_RDN3_P in InfiniteBand main channel and IB_RDP3_P pin.The 14th pin and the 16th pin are differential pairing 3 receiver signal IB_RDN3_S of Infinite Band subchannel and IB_RDP3_S pin.
The 17th pin and the 19th pin are differential pairing 2 receiver signal IB_RDN2_P in Infinite Band main channel and IB_RDP2_P pin.The 18th pin and the 20th pin are differential pairing 2 receiver signal IB_RDN2_S of InfiniteBand subchannel and IB_RDP2_S pin.The 21st pin to the 23 pins are differential pairing 1 receiver signal IB_RDN1_P in Infinite Band main channel and IB_RDP1_P pin.The 22nd pin and the 24th pin are differential pairing 1 receiver signal IB_RDN1_S of Infinite Band subchannel and IB_RDP1_S pin.The 25th pin and the 27th pin are differential pairing 4 sender signal IB_TDN4_P in Infinite Band main channel and IB_TDP4_P pin.The 26th pin and the 28th pin are differential pairing 4 sender signal IB_TDN4_S of Infinite Band subchannel and IB_TDP4_S pin.The 29th pin and the 31st pin are differential pairing 3 sender signal IB_TDN3_P in InfiniteBand main channel and IB_TDP3_P pin.The 30th pin and the 32nd pin are differential pairing 3 sender signal IB_TDN3_S of Infinite Band subchannel and IB_TDP3_S pin.
The 33rd pin and the 35th pin are differential pairing 2 sender signal IB_TDN2_P in Infinite Band main channel and IB_TDP2_P pin.The 34th pin and the 36th pin are differential pairing 2 sender signal IB_TDN2_S of InfiniteBand subchannel and IB_TDP2_S pin.The 37th pin and the 39th pin are differential pairing 1 sender signal IB_TDN1_P in Infinite Band main channel and IB_TDP1_P pin.The 38th pin and the 40th pin are differential pairing 1 sender signal IB_TDN1_S of Infinite Band subchannel and IB_TDP1_S pin.The 41st pin is a GIGA network running indicator signal GB_LED pin.The 42nd pin is an Infinite Band main channel GPIO signal IB_GPIO_P pin.The 43rd pin is an optical fiber running indicator signal FC_LED pin.The 44th pin is an Infinite Band secondary channel GPIO signal IB_GPIO_S pin.The 45th pin and the 47th pin are PCI (Express) B channel clock differential pairing received signal EXPB_100MHz_CLK_P and EXPB_100MHz_CLK_N pin fast.The 46th pin is a System Management Bus clock signal SMB4_CLK pin.
The 48th pin is a System Management Bus data-signal SMB4_DTA pin.The 49th pin and the 51st pin are differential pairing 0 receiver signal EXPB_RXP0 of PCI fast B passage and EXPB_RXN0 pin.The 50th pin and the 52nd pin are differential pairing 0 sender signal EXPB_TXP0 of PCI fast B passage and EXPB_TXN0 pin.The 53rd pin and the 55th pin are differential pairing 1 receiver signal EXPB_RXP1 of PCI fast B passage and EXPB_RXN1 pin.The 54th pin and the 56th pin are differential pairing 1 sender signal EXPB_TXP1 of PCI fast B passage and EXPB_TXN1 pin.The 57th pin and the 59th pin are differential pairing 2 receiver signal EXPB_RXP2 of PCI fast B passage and EXPB_RXN2 pin.The 58th pin and the 60th pin are differential pairing 2 sender signal EXPB_TXP2 of PCI fast B passage and EXPB_TXN2 pin.The 61st pin and the 63rd pin are differential pairing 3 receiver signal EXPB_RXP3 of PCI fast B passage and EXPB_RXN3 pin.The 62nd pin and the 64th pin are differential pairing 3 sender signal EXPB_TXP3 of PCI fast B passage and EXPB_TXN3 pin.
The 65th pin and the 67th pin are differential pairing 4 receiver signal EXPB_RXP4 of PCI fast B passage and EXPB_RXN4 pin.The 66th pin and the 68th pin are differential pairing 4 sender signal EXPB_TXP4 of PCI fast B passage and EXPB_TXN4 pin.The 69th pin and the 71st pin are differential pairing 5 receiver signal EXPB_RXP5 of PCI fast B passage and EXPB_RXN5 pin.The 70th pin and the 72nd pin are differential pairing 5 sender signal EXPB_TXP5 of PCI fast B passage and EXPB_TXN5 pin.The 73rd pin and the 75th pin are differential pairing 6 receiver signal EXPB_RXP6 of PCI fast B passage and EXPB_RXN6 pin.The 74th pin and the 76th pin are differential pairing 6 sender signal EXPB_TXP6 of PCI fast B passage and EXPB_TXN6 pin.The 77th pin and the 79th pin are differential pairing 7 receiver signal EXPB_RXP7 of PCI fast B passage and EXPB_RXN7 pin.The 78th pin and the 80th pin are differential pairing 7 sender signal EXPB_TXP7 of PCI fast B passage and EXPB_TXN7 pin.The 81st pin is a system power supply good signal SYS_PWRGD2 pin.The 82nd pin is that the LAN function is waken (Wake UP) signal WAKE_N pin up.The 83rd pin and the 84th pin are ground connection GND pin.And the G1～G12 pin is ground connection (GND) pin.
Please refer to 2D figure, it illustrates the 4th specification pin arrangement plan of second connector 122 among the 1st figure.Above-mentioned the 4th specification is to meet the Down_Daughter specification: characteristic is the connector of High Speed, 0.8mm, Male, double row, SMD and 120 pins, for example connector of model SamtecQTE-060-03-F-D-D-A.Second connector 122 has 120 branch connecting pins 124 such as the 1st pin to the 120 pins.
The 1st pin to the 9 pins are respectively PCI address/data signal P2_AD27, P2_AD31, P2_AD26, P2_AD30, P2_AD25, P2_AD29, P2_AD24, P2_AD28 and P2_AD23 pin.The 11st pin, the 13rd pin, the 15th pin, the 17th pin, the 19th pin, the 21st pin, the 23rd pin, the 25th pin, the 27th pin and the 29th pin are respectively PCI address/data signal P2_AD22, P2_AD21, P2_AD20, P2_AD19, P2_AD18, P2_AD17, P2_AD16, P2_AD15, P2_AD14 and P2_AD13 pin.The 31st pin, the 33rd pin, the 35th pin, the 37th pin, the 39th pin, the 41st pin, the 43rd pin, the 45th pin, the 47th pin and the 49th pin are respectively PCI address/data signal P2_AD12, P2_AD11, P2_AD10, P2_AD9, P2_AD8, P2_AD7, P2_AD6, P2_AD5, P2_AD4 and P2_AD3 pin.
The 51st pin, the 53rd pin, the 55th pin, the 57th pin, the 59th pin, the 61st pin, the 63rd pin, the 65th pin, the 67th pin and the 69th pin are respectively PCI address/data signal P2_AD2, P2_AD1, P2_AD0, P2_AD63, P2_AD62, P2_AD61, P2_AD60, P2_AD59, P2_AD58 and P2_AD57 pin.The 71st pin, the 73rd pin, the 75th pin, the 77th pin, the 79th pin, the 81st pin, the 83rd pin, the 85th pin, the 87th pin and the 89th pin are respectively PCI address/data signal P2_AD56, P2_AD55, P2_AD54, P2_AD53, P2_AD52, P2_AD51, P2_AD50, P2_AD49, P2_AD48 and P2_AD47 pin.
The 91st pin, the 93rd pin, the 95th pin, the 97th pin, the 99th pin, the 101st pin, the 103rd pin, the 105th pin, the 107th pin, the 109th pin, the 111st pin, the 113rd pin, the 115th pin, the 117th pin and the 119th pin are respectively PCI address/data signal P2_AD46, P2_AD45, P2_AD44, P2_AD43, P2_AD42, P2_AD41, P2_AD40, P2_AD39, P2_AD 38, P2_AD37, P2_AD36, P2_AD35, P2_AD34, P2_AD33 and P2_AD32 pin.G1 pin to G12 pin is a ground connection GND pin.The 10th pin is that optical fiber exists signal FC_PRESENT_N pin.The 12nd pin, the 14th pin, the 84th pin and the 86th pin are PCI look-at-me PCIIRQ-L7, PCIIRQ-L6, PCIIRQ-L10, PCIIRQ-L9 pin.
The 16th pin is a pci clock signal PCIX_CLK1 pin.The 18th pin is a PCI reset signal PCIX_RST-L pin.The 20th pin is that PCI allows (Grant) bus 0 signal P2_PGNT-L0 pin.The 22nd pin is PCI request (Request) bus 0 signal P_REQ-L0 pin.The 24th pin is PCI parity checking (Parity) signal P2_PAR pin.The 26th pin is a PCI stop signal P2_STOP-L pin.The 28th pin is selected signal P2_DEVSEL-L pin for the PCI device.The 30th pin is a PCI target ready signal P2_TRDY-L pin.The 32nd pin is a PCI start-up routine ready signal P2_IRDY-L pin.The 34th pin is pci data frame (Frame) signal P2_FREAME-L pin.
The 36th pin is a pci system rub-out signal P2_SERR-L pin.The 38th pin is PCI parity error (Parity Error) signal P2_PERR-L pin.The 40th pin is an I2C clock signal SMBO_SCL pin.The 42nd pin, the 44th pin, the 46th pin, the 48th pin, the 60th pin, the 62nd pin, the 64th pin and the 66th pin are pci bus order (Bus Command) and byte activation (Byte Enable) signal P2_CBE-L3, P2_CBE-L2, P2_CBE-L1, P2_CBE-L0, P2_CBE-L7, P2_CBE-L6, P2_CBE-L5, P2_CBE-L4 pin.The 50th pin is a 66Mhz enable signal P2_M66EN pin.The 52nd pin is that (Acknowledge) signal P2_ACK64-L pin is confirmed in 64 transmission (Transfer).
The 54th pin is 64 transmission requests (Request) signal P2_REQ64 pin.The 56th pin is 64 bit parity check signal P2_PAR64 pins.The 58th pin is an I2C data-signal SMBO_SDA pin.The 68th pin is a PIC-X tenability signal PCIXCAP pin.The 70th pin is PCI request bus 2 signal P_REQ-L2 pins.The 72nd pin is that PCI allows (Grant) bus 2 signal P2_PGNT-L2 pins.The 74th pin is a pci clock signal PCIX_CLK2 pin.The 76th pin is that initialization (Initialization) element is selected 2 signal IDSEL2 pins.The 78th pin is selected 1 signal IDSEL1 pin for the initialization element.The 80th pin is a PCI locking signal P2_LOCK-L pin.
The 82nd pin is PCI power events management (PME) signal RESERVE_PME-L pin.The 88th pin is that SCSI interrupts B signal SCSI_IRQB-L pin.The 90th pin is that SCSI interrupts a-signal SCSI_IRQA-L pin.The 92nd pin is in order to exist signal ZCR_PRESENT-L pin as a ZCR.The 94th pin is that ZCR allows bus signals ZCR_GNT-L pin.The 96th pin is a standby 5V power supply signal VCC5SBY pin.The 98th pin is a standby 3.3V power supply signal VCC3_3SBY pin.The 100th pin, the 102nd pin, the 104th pin and the 106th pin are the 5V of system power supply signal VCC5 pin.The 108th pin, the 110th pin, the 112nd pin, the 114th pin, the 116th pin and the 118th pin are the 3.3V of system power supply signal VCC3_3 pin.The 120th pin is the 12V of a system power supply signal pin.
Please refer to 2E figure, it illustrates the 5th specification pin arrangement plan of second connector 122 among the 1st figure.Above-mentioned the 5th specification is accord with PCI _ Base_Conn specification: characteristic is the connector of High Speed, 0.8mm, Male, double row, SMD and 40 pins, for example connector of model Samtec QTE-020-03-F-D-A.Second connector 122 has 40 branch connecting pins 124 such as the 1st pin to the 40 pins.
The 1st pin is a pci system rub-out signal SERR pin.The 2nd pin is PCI parity checking (Parity) rub-out signal PERR pin.The 4th pin is a System Management Bus clock signal SMB_CLK2 pin.The 6th pin is a System Management Bus data-signal SMB_DATA2 pin.The 3rd pin, the 5th pin, the 7th pin, the 8th pin, the 13rd pin to the 16 pins, the 22nd pin, the 23rd pin and the 31st pin to the 35 pins are ground connection GND pin.
The 9th pin to the 12 pins are the 12V of system power supply signal pin.The 17th pin to the 21 pins are the 3.3V of system power supply signal pin.The 24th pin, the 26th pin, the 28th pin and the 30th pin are the 5V of system power supply signal pin.The 25th pin, the 27th pin and the 29th pin are the 1.5V of system power supply signal pin.The 36th pin and the 38th pin are standby 3.3V power supply signal 3V3STB pin.The 37th pin is that PCI exists 1 signal PRESENT1 pin.The 39th pin is that PCI exists 2 signal PRESENT2 pins.The 40th pin is PCI power management event (PME) signal PME pin.
Please refer to 2F figure, it illustrates another pin arrangement plan of the 5th specification of second connector 122 among the 1st figure.Above-mentioned the 5th specification is accord with PCI _ Base_Conn specification: characteristic is the connector of High Speed, 0.8mm, Male, double row, SMD and 40 pins, for example connector of model SamtecQTE-020-03-F-D-A.Second connector 122 has 40 branch connecting pins 124 such as the 1st pin to the 40 pins.
The 1st pin and the 3rd pin are differential pairing 1 sender signal EXPA_TX_N1 of PCI quick A passage and EXPA_TX_P1 pin.The 2nd pin is that PCI substrate (Base Board) exists signal PRESENT pin.The 4th pin is a pci bus reset signal PCI_RST pin.The 5th pin, the 11st pin, the 17th pin, the 23rd pin, the 29th pin, the 30th pin, the 35th pin, the 36th pin are ground connection GND pin.The 6th pin is a system power supply normal signal SYSTEM_PWR_OK pin.The 7th pin and the 9th pin are differential pairing 3 receiver signal EXPA_RX_P3 of PCI quick A passage and EXPA_RX_N3 pin.The 8th pin is a System Management Bus clock signal SMB_CLK pin.The 10th pin is a System Management Bus data-signal SMB_DATA pin.The 12nd pin is the 12V of a system power supply signal pin.The 14th pin is the 5V of a system power supply signal pin.The 13rd pin and the 15th pin are differential pairing 3 sender signal EXPA_TX_P3 of PCI quick A passage and EXPA_TX_N3 pin.The 16th pin, the 18th pin, the 20th pin and the 22nd pin are the 3.3V of system power supply signal pin.The 19th pin and the 21st pin are differential pairing 2 receiver signal EXPA_RX_N2 of PCI quick A passage and EXPA_RX_P2 pin.The 24th pin is a standby 3.3V power supply signal 3V3STB pin.The 25th pin and the 27th pin are differential pairing 0 sender signal EXPA_TX_P0 of PCI quick A passage and EXPA_TX_N0 pin.The 26th pin and the 28th pin are the 1.5V of system power supply signal pin.The 31st pin and the 33rd pin are differential pairing 0 receiver signal EXPA_RX_N0 of PCI quick A passage and EXPA_RX_P0 pin.The 32nd pin and the 34th pin are differential pairing 2 sender signal EXPA_TX_N2 of PCI quick A passage and EXPA_TX_P2 pin.The 37th pin and the 39th pin are differential pairing 1 receiver signal EXPA_RX_N1 of PCI quick A passage and EXPA_RX_P1 pin.The 38th pin and the 40th pin are PCI quick A channel clock differential pairing received signal EXPA_CLOCK_N and EXPA_CLOCK_P pin.
According to above-mentioned preferred embodiment, the advantage of the utility model blade-point servo system is to be locked as the specific function pin by all pins of cutter point server connector, Yan Zhi cutter point server is dull and stereotyped in the middle of being connected to by connector voluntarily, the required function of dull and stereotyped generation in the middle of must correctly being connected to, thereby can't be suitable for the designed system of the utility model, effectively avoid the imitated of unworthy manufacturer.
In sum; though the utility model discloses as above with a preferred embodiment; right its is not in order to limit the utility model; the any technician in this area; in not breaking away from spirit and scope of the present utility model; when being used for a variety of modifications and variations, therefore protection domain of the present utility model is as the criterion when looking appended the claim scope person of defining.

Claims (12)

1.一种刀锋伺服系统，包括：1. A blade servo system, comprising: 中间平板(Middle Plane Board)，包括第一连接器；以及Middle Plane Board, including the first connector; and 刀锋服务器(Server Blade)，包括第二连接器，用以电性连接该第一连接器，该第二连接器具有符合特定规格的多支接脚，该些接脚包括：A blade server (Server Blade) includes a second connector for electrically connecting the first connector, the second connector has a plurality of pins meeting specific specifications, and the pins include: A1接脚，用以作为刀锋服务器存在信号接脚；The A1 pin is used as the existence signal pin of the blade server; A2接脚以及A3接脚，用以作为小型计算机系统接口(Small ComputerSystem Interface，SCSI)请求(Request)信号接脚；The A2 pin and the A3 pin are used as small computer system interface (Small Computer System Interface, SCSI) request (Request) signal pins; A4接脚至A9接脚、B8接脚、B9接脚、E1接脚、E2接脚、E4接脚至E7接脚，F2接脚至F11接脚以及G2接脚至G9接脚，用以作为SCSI信道字节信号对(Channel Byte Signal Pairs)接脚；A4 pin to A9 pin, B8 pin, B9 pin, E1 pin, E2 pin, E4 pin to E7 pin, F2 pin to F11 pin and G2 pin to G9 pin for As a SCSI channel byte signal pair (Channel Byte Signal Pairs) pin; B4接脚以及B5接脚，用以作为SCSI输入/输出信号接脚；The B4 pin and the B5 pin are used as SCSI input/output signal pins; B6接脚以及B7接脚，用以作为选择信号接脚；The B6 pin and the B7 pin are used as selection signal pins; C4接脚以及C5接脚，用以作为SCSI重置信号接脚；The C4 pin and the C5 pin are used as SCSI reset signal pins; C6接脚以及C7接脚，用以作为SCSI信息信号接脚；The C6 pin and the C7 pin are used as SCSI information signal pins; C8接脚以及C9接脚，用以作为SCSI命令/数据(Command/Data)信号接脚；The C8 pin and the C9 pin are used as SCSI command/data (Command/Data) signal pins; D4接脚以及D5接脚，用以作为SCSI警示(Attention)信号接脚；The D4 pin and the D5 pin are used as SCSI warning (Attention) signal pins; D6接脚以及D7接脚，用以作为SCSI通路全忙(Busy)信号接脚；The D6 pin and the D7 pin are used as SCSI channel full busy (Busy) signal pins; D8接脚以及D9接脚，用以作为SCSI确认(Acknowledge)信号；The D8 pin and the D9 pin are used as SCSI acknowledgment (Acknowledge) signals; E3接脚，用以作为SCSI差动信号感应检测(Differential Sense)输入信号接脚；The E3 pin is used as the input signal pin of the SCSI differential signal sensing detection (Differential Sense); E8接脚以及E9接脚，用以作为SCSI高字节奇偶校验(High Byte Parity)信号接脚；The E8 pin and the E9 pin are used as SCSI high byte parity (High Byte Parity) signal pins; G10接脚以及G11接脚，用以作为SCSI低字节奇偶校验(Low Byte Parity)信号接脚；The G10 pin and the G11 pin are used as SCSI low byte parity (Low Byte Parity) signal pins; A10接脚、A11接脚、B10接脚、B11接脚、C10接脚、C11接脚、D10接脚、D11接脚以及E11接脚，用以作为系统12V电源信号接脚；A10 pin, A11 pin, B10 pin, B11 pin, C10 pin, C11 pin, D10 pin, D11 pin and E11 pin are used as system 12V power supply signal pins; B1接脚，用以作为待机5V电源信号接脚；The B1 pin is used as a standby 5V power supply signal pin; B2接脚，用以作为待机5V预先充电(Precharge)电源信号接脚；The B2 pin is used as a standby 5V precharge (Precharge) power signal pin; B3接脚、C2接脚、C3接脚以及D3接脚，用以作为刀锋服务器ID脚位；The B3 pin, the C2 pin, the C3 pin and the D3 pin are used as the ID pins of the blade server; C1接脚以及D1接脚，用以作为系统5V电源接脚；C1 pin and D1 pin are used as system 5V power supply pins; D2接脚，用以作为系统12V预先充电电源信号接脚；The D2 pin is used as the system 12V pre-charging power signal pin; F1接脚，用以作为机箱管理模块(Chassis Management Module，CMM)流量控制CTS接脚；The F1 pin is used as a chassis management module (Chassis Management Module, CMM) flow control CTS pin; G1接脚，用以作为CMM流量控制RTS接脚；The G1 pin is used as the CMM flow control RTS pin; H1接脚，用以作为显示接口I2C总线数据信号接脚；The H1 pin is used as a display interface I2C bus data signal pin; H2接脚，用以作为显示接口I2C总线时钟信号接脚；The H2 pin is used as a display interface I2C bus clock signal pin; H3接脚，用以作为蓝显示信号接脚；The H3 pin is used as the blue display signal pin; H4接脚，用以作为绿显示信号接脚；The H4 pin is used as a green display signal pin; H5接脚，用以作为红显示信号接脚；The H5 pin is used as a red display signal pin; H6接脚，用以作为显示垂直同步信号接脚；The H6 pin is used as a display vertical synchronization signal pin; H7接脚，用以作为显示水平同步信号接脚；The H7 pin is used as a display horizontal synchronization signal pin; H8接脚，用以作为通用序列总线(USB)负信号接脚；The H8 pin is used as a universal serial bus (USB) negative signal pin; H9接脚，用以作为USB正信号接脚；The H9 pin is used as a USB positive signal pin; H10接脚，用以作为I2C总线时钟信号接脚；The H10 pin is used as the I2C bus clock signal pin; E10接脚与多个第Y1至第Y11接脚，用以作为接地接脚；以及The E10 pin and a plurality of Y1 to Y11 pins are used as grounding pins; and H11接脚，用以作为I2C总线数据信号接脚。The H11 pin is used as an I2C bus data signal pin. 2.根据权利要求1所述的刀锋伺服系统，其中该特定规格系符合一Low_EPT_CONN规格：特性为Hard Metric 2.0mm、8single rows、2 shieldingrows、Female、Right-Angle、DIP以及99支接脚。2. The blade servo system according to claim 1, wherein the specific specification conforms to a Low_EPT_CONN specification: the characteristics are Hard Metric 2.0mm, 8single rows, 2 shieldingrows, Female, Right-Angle, DIP and 99 pins. 3.一种刀锋伺服系统，包括：3. A blade servo system, comprising: 中间平板，包括第一连接器；以及an intermediate plane including a first connector; and 刀锋服务器，包括第二连接器，用以电性连接该第一连接器，该第二连接器具有符合特定规格的多支接脚，该些接脚包括：The blade server includes a second connector for electrically connecting the first connector, the second connector has a plurality of pins meeting specific specifications, and the pins include: A1接脚以及B1接脚，用以作为光纤/GIGA网络差动配对(DifferentialPair)1发送器信号接脚；The A1 pin and the B1 pin are used as the optical fiber/GIGA network differential pair (DifferentialPair) 1 transmitter signal pin; A2接脚以及B2接脚，用以作为光纤/GIGA网络差动配对1接收器信号接脚；The A2 pin and the B2 pin are used as the optical fiber/GIGA network differential pairing 1 receiver signal pin; A3接脚以及B3接脚，用以作为Infinite Band主通道差动配对1接收器信号接脚；A3 pin and B3 pin are used as Infinite Band main channel differential pairing 1 receiver signal pin; A4接脚以及B4接脚，用以作为Infinite Band主通道差动配对2接收器信号接脚；A4 pin and B4 pin are used as Infinite Band main channel differential pair 2 receiver signal pins; A5接脚以及B5接脚，用以作为Infinite Band主通道差动配对3接收器信号接脚；A5 pin and B5 pin are used as Infinite Band main channel differential pairing 3 receiver signal pins; A6接脚以及B6接脚，用以作为Infinite Band主通道差动配对4接收器信号接脚；A6 pin and B6 pin are used as Infinite Band main channel differential pairing 4 receiver signal pins; A7接脚以及B7接脚，用以作为Infinite Band次通道差动配对1接收器信号接脚；A7 pin and B7 pin are used as Infinite Band sub-channel differential pairing 1 receiver signal pins; A8接脚以及B8接脚，用以作为Infinite Band次通道差动配对2接收器信号接脚；A8 pin and B8 pin are used as Infinite Band sub-channel differential pairing 2 receiver signal pins; A9接脚以及B9接脚，用以作为Infinite Band次通道差动配对3接收器信号接脚；A9 pin and B9 pin are used as Infinite Band sub-channel differential pairing 3 receiver signal pins; A10接脚以及B10接脚，用以作为Infinite Band次通道差动配对4接收器信号接脚；A10 pin and B10 pin are used as Infinite Band sub-channel differential pairing 4 receiver signal pins; C1接脚至C10接脚，用以作为接地接脚；C1 pin to C10 pin are used as ground pins; D1接脚以及E1接脚，用以作为光纤/GIGA网络差动配对2发送器信号接脚；The D1 pin and the E1 pin are used as the optical fiber/GIGA network differential pairing 2 transmitter signal pins; D2接脚以及E2接脚，用以作为光纤/GIGA网络差动配对2接收器信号接脚；D2 pin and E2 pin are used as optical fiber/GIGA network differential pairing 2 receiver signal pins; D3接脚以及E3接脚，用以作为Infinite Band主通道差动配对1发送器信号接脚；D3 pin and E3 pin are used as Infinite Band main channel differential pairing 1 transmitter signal pin; D4接脚以及E4接脚，用以作为Infinite Band主通道差动配对2发送器信号接脚；D4 pin and E4 pin are used as Infinite Band main channel differential pairing 2 transmitter signal pins; D5接脚以及E5接脚，用以作为Infinite Band主通道差动配对3发送器信号接脚；D5 pin and E5 pin are used as Infinite Band main channel differential pairing 3 transmitter signal pins; D6接脚以及E6接脚，用以作为Infinite Band主通道差动配对4发送器信号接脚；D6 pin and E6 pin are used as Infinite Band main channel differential pairing 4 transmitter signal pins; D7接脚以及E7接脚，用以作为Infinite Band次通道差动配对1发送器信号接脚；D7 pin and E7 pin are used as Infinite Band secondary channel differential pairing 1 transmitter signal pin; D8接脚以及E8接脚，用以作为Infinite Band次通道差动配对2发送器信号接脚；D8 pin and E8 pin are used as Infinite Band sub-channel differential pairing 2 transmitter signal pins; D9接脚以及E9接脚，用以作为Infinite Band次通道差动配对3发送器信号接脚；D9 pin and E9 pin are used as Infinite Band secondary channel differential pairing 3 transmitter signal pins; D10接脚以及E10接脚，用以作为Infinite Band次通道差动配对4发送器信号接脚；D10 pin and E10 pin are used as Infinite Band secondary channel differential pairing 4 transmitter signal pins; F1接脚至F10接脚，用以作为接地接脚；The F1 pin to the F10 pin are used as ground pins; G1接脚，用以作为局部总线(Local Bus)功能致能0信号接脚；The G1 pin is used as a local bus (Local Bus) function enable 0 signal pin; G2接脚，用以作为局部总线功能致能2信号接脚；The G2 pin is used as a local bus function enable 2 signal pin; G3接脚至G7接脚，用以作为局部总线数据位[0:4]信号接脚；The G3 pin to the G7 pin are used as local bus data bits [0:4] signal pins; G8接脚，用以作为PS2鼠标时钟信号接脚；The G8 pin is used as the PS2 mouse clock signal pin; G9接脚，用以作为PS2键盘时钟信号接脚；The G9 pin is used as the PS2 keyboard clock signal pin; G10接脚，用以作为Infinite Band主通道总体输入/输出(GeneralPurpose Input/Output，GPIO)接脚；The G10 pin is used as the general purpose input/output (GPIO) pin of the Infinite Band main channel; H1接脚，用以作为刀锋服务器接合信号接脚；The H1 pin is used as a blade server connecting signal pin; H2接脚，用以作为局部总线功能致能1信号接脚；The H2 pin is used as a local bus function enable 1 signal pin; H3接脚，用以作为局部总线数据位信号接脚；The H3 pin is used as a local bus data bit signal pin; H4接脚，用以作为局部总线选通(Strobe)信号接脚；The H4 pin is used as a local bus strobe (Strobe) signal pin; H5接脚，用以作为机箱管理模块(Chassis Management Module，CMM)接收流量控制接脚；The H5 pin is used as a chassis management module (Chassis Management Module, CMM) receiving flow control pin; H6接脚，用以作为CMM传输流量控制接脚；The H6 pin is used as a CMM transmission flow control pin; H7接脚，用以作为局部总线清除功能接脚；The H7 pin is used as a local bus clear function pin; H8接脚，用以作为PS2鼠标数据接脚；H8 pin, used as PS2 mouse data pin; H9接脚，用以作为PS2键盘数据接脚；以及The H9 pin is used as a PS2 keyboard data pin; and H10接脚，用以作为Infinite Band次通道GPIO接脚。The H10 pin is used as the GPIO pin of the Infinite Band secondary channel. 4.根据权利要求3所述的刀锋伺服系统，其中该特定规格系符合Upper_5G_CONN规格：特性为VHDM-HSD 8 row、2.0mm、Female、Right-Angle、DIP以及92支接脚。4. The blade servo system according to claim 3, wherein the specific specification conforms to the Upper_5G_CONN specification: the characteristics are VHDM-HSD 8 row, 2.0mm, Female, Right-Angle, DIP and 92 pins. 5.一种刀锋伺服系统，包括：5. A blade servo system, comprising: 中间平板，包括第一连接器；以及an intermediate plane including a first connector; and 刀锋服务器，包括第二连接器，用以电性连接该第一连接器，该第二连接器具有符合特定规格的多支接脚，该些接脚包括：The blade server includes a second connector for electrically connecting the first connector, the second connector has a plurality of pins meeting specific specifications, and the pins include: 第1接脚以及第3接脚，用以作为光纤/GIGA网络差动配对(Differential Pair)1发送器信号接脚；The 1st pin and the 3rd pin are used as the optical fiber/GIGA network differential pair (Differential Pair) 1 transmitter signal pin; 第2接脚以及第4接脚，用以作为光纤/GIGA网络差动配对1接收器信号接脚；The 2nd pin and the 4th pin are used as the optical fiber/GIGA network differential pair 1 receiver signal pin; 第5接脚以及第7接脚，用以作为光纤/GIGA网络差动配对2发送器信号接脚；The 5th pin and the 7th pin are used as the optical fiber/GIGA network differential pairing 2 transmitter signal pins; 第6接脚以及第8接脚，用以作为光纤/GIGA网络差动配对2接收器信号接脚；The 6th pin and the 8th pin are used as optical fiber/GIGA network differential pairing 2 receiver signal pins; 第9接脚以及第11接脚，用以作为Infinite Band主通道差动配对4接收器信号接脚；The 9th pin and the 11th pin are used as Infinite Band main channel differential pairing 4 receiver signal pins; 第10接脚以及第12接脚，用以作为Infinite Band次通道差动配对4接收器信号接脚；The 10th pin and the 12th pin are used as Infinite Band sub-channel differential pairing 4 receiver signal pins; 第13接脚以及第15接脚，用以作为Infinite Band主通道差动配对3接收器信号接脚；The 13th pin and the 15th pin are used as Infinite Band main channel differential pairing 3 receiver signal pins; 第14接脚以及第16接脚，用以作为Infinite Band次通道差动配对3接收器信号接脚；The 14th pin and the 16th pin are used as Infinite Band sub-channel differential pairing 3 receiver signal pins; 第17接脚以及第19接脚，用以作为Infinite Band主通道差动配对2接收器信号接脚；The 17th pin and the 19th pin are used as Infinite Band main channel differential pairing 2 receiver signal pins; 第18接脚以及第20接脚，用以作为Infinite Band次通道差动配对2接收器信号接脚；The 18th pin and the 20th pin are used as Infinite Band secondary channel differential pairing 2 receiver signal pins; 第21接脚至第23接脚，用以作为Infinite Band主通道差动配对1接收器信号接脚；The 21st to 23rd pins are used as Infinite Band main channel differential pairing 1 receiver signal pins; 第22接脚以及第24接脚，用以作为Infinite Band次通道差动配对1接收器信号接脚；The 22nd pin and the 24th pin are used as Infinite Band secondary channel differential pairing 1 receiver signal pins; 第25接脚以及第27接脚，用以作为Infinite Band主通道差动配对4发送器信号接脚；The 25th and 27th pins are used as Infinite Band main channel differential pairing 4 transmitter signal pins; 第26接脚以及第28接脚，用以作为Infinite Band次通道差动配对4发送器信号接脚；The 26th pin and the 28th pin are used as Infinite Band secondary channel differential pairing 4 transmitter signal pins; 第29接脚以及第31接脚，用以作为Infinite Band主通道差动配对3发送器信号接脚；The 29th pin and the 31st pin are used as the signal pins of the Infinite Band main channel differential pairing 3 transmitters; 第30接脚以及第32接脚，用以作为Infinite Band次通道差动配对3发送器信号接脚；The 30th pin and the 32nd pin are used as the signal pins of the Infinite Band sub-channel differential pairing 3 transmitters; 第33接脚以及第35接脚，用以作为Infinite Band主通道差动配对2发送器信号接脚；The 33rd pin and the 35th pin are used as Infinite Band main channel differential pairing 2 transmitter signal pins; 第34接脚以及第36接脚，用以作为Infinite Band次通道差动配对2发送器信号接脚；The 34th pin and the 36th pin are used as the signal pins of the Infinite Band sub-channel differential pairing 2 transmitters; 第37接脚以及第39接脚，用以作为Infinite Band主通道差动配对1发送器信号接脚；The 37th pin and the 39th pin are used as the signal pins of the Infinite Band main channel differential pairing 1 transmitter; 第38接脚以及第40接脚，用以作为Infinite Band次通道差动配对1发送器信号接脚；The 38th pin and the 40th pin are used as the signal pins of the Infinite Band sub-channel differential pairing 1 transmitter; 第41接脚，用以作为GIGA网络运转指示信号接脚；The 41st pin is used as the GIGA network operation indication signal pin; 第42接脚，用以作为Infinite Band主信道GPIO信号接脚；The 42nd pin is used as the GPIO signal pin of the Infinite Band main channel; 第43接脚，用以作为光纤运转指示信号接脚；The 43rd pin is used as the optical fiber operation indication signal pin; 第44接脚，用以作为Infinite Band次信道GPIO信号接脚；The 44th pin is used as the GPIO signal pin of the Infinite Band secondary channel; 第45接脚以及第47接脚，用以作为PCI快速B通道时钟差动配对接收接脚；The 45th pin and the 47th pin are used as PCI fast B-channel clock differential pairing receiving pins; 第46接脚，用以作为系统管理总线时钟信号接脚；The 46th pin is used as a system management bus clock signal pin; 第48接脚，用以作为系统管理总线数据信号接脚；The 48th pin is used as a system management bus data signal pin; 第49接脚以及第51接脚，用以作为PCI快速B通道差动配对0接收器接脚；The 49th pin and the 51st pin are used as PCI Express B-channel differential pairing 0 receiver pins; 第50接脚以及第52接脚，用以作为PCI快速B通道差动配对0发送器接脚；The 50th pin and the 52nd pin are used as PCI Express B channel differential pair 0 transmitter pins; 第53接脚以及第55接脚，用以作为PCI快速B通道差动配对1接收器接脚；The 53rd pin and the 55th pin are used as PCI Express B-channel differential pairing 1 receiver pins; 第54接脚以及第56接脚，用以作为PCI快速B通道差动配对1发送器接脚；The 54th pin and the 56th pin are used as PCI Express B-channel differential pairing 1 transmitter pins; 第57接脚以及第59接脚，用以作为PCI快速B通道差动配对2接收器接脚；The 57th pin and the 59th pin are used as PCI Express B-channel differential pairing 2 receiver pins; 第58接脚以及第60接脚，用以作为PCI快速B通道差动配对2发送器接脚；The 58th pin and the 60th pin are used as PCI Express B-channel differential pairing 2 transmitter pins; 第61接脚以及第63接脚，用以作为PCI快速B通道差动配对3接收器接脚；The 61st pin and the 63rd pin are used as PCI Express B-channel differential pair 3 receiver pins; 第62接脚以及第64接脚，用以作为PCI快速B通道差动配对3发送器接脚；The 62nd pin and the 64th pin are used as PCI Express B-channel differential pair 3 transmitter pins; 第65接脚以及第67接脚，用以作为PCI快速B通道差动配对4接收器接脚；The 65th pin and the 67th pin are used as PCI Express B-channel differential pairing 4 receiver pins; 第66接脚以及第68接脚，用以作为PCI快速B通道差动配对4发送器接脚；The 66th pin and the 68th pin are used as PCI Express B-channel differential pairing 4 transmitter pins; 第69接脚以及第71接脚，用以作为PCI快速B通道差动配对5接收器接脚；The 69th pin and the 71st pin are used as PCI Express B-channel differential pairing 5 receiver pins; 第70接脚以及第72接脚，用以作为PCI快速B通道差动配对5发送器接脚；The 70th pin and the 72nd pin are used as PCI Express B-channel differential pairing 5 transmitter pins; 第73接脚以及第75接脚，用以作为PCI快速B通道差动配对6接收器接脚；The 73rd pin and the 75th pin are used as PCI Express B-channel differential pairing 6 receiver pins; 第74接脚以及第76接脚，用以作为PCI快速B通道差动配对6发送器接脚；The 74th pin and the 76th pin are used as PCI Express B-channel differential pairing 6 transmitter pins; 第77接脚以及第79接脚，用以作为PCI快速B通道差动配对7接收器接脚；The 77th pin and the 79th pin are used as PCI Express B-channel differential pairing 7 receiver pins; 第78接脚以及第80接脚，用以作为PCI快速B通道差动配对7发送器接脚；The 78th pin and the 80th pin are used as PCI Express B-channel differential pairing 7 transmitter pins; 第81接脚，用以作为系统电源良好信号接脚；The 81st pin is used as a system power good signal pin; 第82接脚，用以作为LAN功能唤醒信号接脚；The 82nd pin is used as the wake-up signal pin of the LAN function; 第83接脚以及第84接脚，用以作为接地接脚；以及The 83rd pin and the 84th pin are used as ground pins; and 多个第G1接脚至第G12接脚，用以作为接地接脚。A plurality of pins G1 to G12 are used as ground pins. 6.根据权利要求5所述的刀锋伺服系统，其中该特定规格系符合Upper_Daughter规格：特性为High Speed、0.8mm、Male、double row、differential pairs、SMD以及84支接脚。6. The blade servo system according to claim 5, wherein the specific specification conforms to the Upper_Daughter specification: the characteristics are High Speed, 0.8mm, Male, double row, differential pairs, SMD and 84 pins. 7.一种刀锋伺服系统，包括：7. A blade servo system, comprising: 中间平板，包括第一连接器；以及an intermediate plane including a first connector; and 刀锋服务器，包括第二连接器，用以电性连接该第一连接器，该第二连接器具有符合特定规格的多支接脚，该些接脚包括：The blade server includes a second connector for electrically connecting the first connector, the second connector has a plurality of pins meeting specific specifications, and the pins include: 第1接脚至第9接脚、第11接脚、第13接脚、第15接脚、第17接脚、第19接脚、第21接脚、第23接脚、第25接脚、第27接脚、第29接脚、第31接脚、第33接脚、第35接脚、第37接脚、第39接脚、第41接脚、第43接脚、第45接脚、第47接脚、第49接脚、第51接脚、第53接脚、第55接脚、第57接脚、第59接脚、第61接脚、第63接脚、第65接脚、第67接脚、第69接脚、第71接脚、第73接脚、第75接脚、第77接脚、第79接脚、第81接脚、第83接脚、第85接脚、第87接脚、第89接脚、第91接脚、第93接脚、第95接脚、第97接脚、第99接脚、第101接脚、第103接脚、第105接脚、第107接脚、第109接脚、第111接脚、第113接脚、第115接脚、第117接脚以及第119接脚，用以作为PCI地址/数据接脚；Pin 1 to Pin 9, Pin 11, Pin 13, Pin 15, Pin 17, Pin 19, Pin 21, Pin 23, Pin 25, 27th pin, 29th pin, 31st pin, 33rd pin, 35th pin, 37th pin, 39th pin, 41st pin, 43rd pin, 45th pin, 47th pin, 49th pin, 51st pin, 53rd pin, 55th pin, 57th pin, 59th pin, 61st pin, 63rd pin, 65th pin, 67th pin, 69th pin, 71st pin, 73rd pin, 75th pin, 77th pin, 79th pin, 81st pin, 83rd pin, 85th pin, Pin 87, Pin 89, Pin 91, Pin 93, Pin 95, Pin 97, Pin 99, Pin 101, Pin 103, Pin 105, The 107th pin, the 109th pin, the 111th pin, the 113th pin, the 115th pin, the 117th pin and the 119th pin are used as PCI address/data pins; G1接脚至G12接脚，用以作为接地接脚；The G1 pin to the G12 pin are used as ground pins; 第10接脚，用以作为光纤存在信号接脚；The tenth pin is used as an optical fiber presence signal pin; 第12接脚、第14接脚、第84接脚以及第86接脚，用以作为PCI中断信号接脚；The 12th pin, the 14th pin, the 84th pin and the 86th pin are used as PCI interrupt signal pins; 第16接脚，用以作为PCI时钟信号接脚；The 16th pin is used as a PCI clock signal pin; 第18接脚，用以作为PCI重置信号接脚；The 18th pin is used as a PCI reset signal pin; 第20接脚，用以作为PCI允许总线0信号接脚；The 20th pin is used as the PCI enable bus 0 signal pin; 第22接脚，用以作为PCI请求总线0信号接脚；The 22nd pin is used as the PCI request bus 0 signal pin; 第24接脚，用以作为PCI奇偶校验信号接脚；The 24th pin is used as a PCI parity check signal pin; 第26接脚，用以作为PCI停止信号接脚；The 26th pin is used as a PCI stop signal pin; 第28接脚，用以作为PCI装置选择信号接脚；The 28th pin is used as a PCI device selection signal pin; 第30接脚，用以作为PCI目标准备信号接脚；The 30th pin is used as a PCI target preparation signal pin; 第32接脚，用以作为PCI启动程序准备信号接脚；The 32nd pin is used as a signal pin for PCI boot process preparation; 第34接脚，用以作为PCI数据框(Frame)信号接脚；The 34th pin is used as a PCI data frame (Frame) signal pin; 第36接脚，用以作为PCI系统错误信号接脚；The 36th pin is used as a PCI system error signal pin; 第38接脚，用以作为PCI奇偶校验错误信号接脚；The 38th pin is used as a PCI parity error signal pin; 第40接脚，用以作为I2C时钟信号接脚；The 40th pin is used as the I2C clock signal pin; 第42接脚、第44接脚、第46接脚、第48接脚、第60接脚、第62接脚、第64接脚及第66接脚，用以作为PCI总线命令及字节致能(Byte Enable)信号接脚；The 42nd pin, the 44th pin, the 46th pin, the 48th pin, the 60th pin, the 62nd pin, the 64th pin and the 66th pin are used as PCI bus command and byte Can (Byte Enable) signal pin; 第50接脚，用以作为66Mhz致能信号接脚；The 50th pin is used as a 66Mhz enable signal pin; 第52接脚，用以作为64位传输确认信号接脚；The 52nd pin is used as a 64-bit transmission confirmation signal pin; 第54接脚，用以作为64位传输请求信号接脚；The 54th pin is used as a 64-bit transmission request signal pin; 第56接脚，用以作为64位奇偶校验信号接脚；The 56th pin is used as a 64-bit parity signal pin; 第58接脚，用以作为I2C数据信号接脚；The 58th pin is used as an I2C data signal pin; 第68接脚，用以作为PIC-X支持能力信号接脚；The 68th pin is used as a PIC-X support capability signal pin; 第70接脚，用以作为PCI请求总线2信号接脚；The 70th pin is used as the PCI request bus 2 signal pin; 第72接脚，用以作为PCI允许总线2信号接脚；The 72nd pin is used as the PCI enable bus 2 signal pin; 第74接脚，用以作为PCI时钟信号接脚；The 74th pin is used as a PCI clock signal pin; 第76接脚，用以作为初始化元件选择2信号接脚；The 76th pin is used as an initialization element selection 2 signal pin; 第78接脚，用以作为初始化元件选择1信号接脚；The 78th pin is used as an initialization element selection 1 signal pin; 第80接脚，用以作为PCI锁定信号接脚；The 80th pin is used as a PCI lock signal pin; 第82接脚，用以作为PCI电源事件管理信号接脚；The 82nd pin is used as a PCI power event management signal pin; 第88接脚，用以作为SCSI中断B信号接脚；The 88th pin is used as the SCSI interrupt B signal pin; 第90接脚，用以作为SCSI中断A信号接脚；The 90th pin is used as the SCSI interrupt A signal pin; 第92接脚，用以作为ZCR存在信号接脚；The 92nd pin is used as a ZCR presence signal pin; 第94接脚，用以作为ZCR允许总线信号接脚；The 94th pin is used as ZCR to allow the bus signal pin; 第96接脚，用以作为待机5V电源信号接脚；The 96th pin is used as a standby 5V power supply signal pin; 第98接脚，用以作为待机3.3V电源信号接脚；The 98th pin is used as a standby 3.3V power signal pin; 第100接脚、第102接脚、第104接脚及第106接脚，用以作为系统5V电源信号接脚；The 100th pin, the 102nd pin, the 104th pin and the 106th pin are used as system 5V power supply signal pins; 第108接脚、第110接脚、第112接脚、第114接脚、第116接脚及第118接脚，用以作为系统3.3V电源信号接脚；以及The 108th pin, the 110th pin, the 112th pin, the 114th pin, the 116th pin and the 118th pin are used as system 3.3V power signal pins; and 第120接脚，用以作为系统12V电源信号接脚。The 120th pin is used as the system 12V power signal pin. 8.根据权利要求7所述的刀锋伺服系统，其中该特定规格系符合Down_Daughter规格：特性为High Speed、0.8mm、Male、double row、SMD以及120接脚。8. The blade servo system according to claim 7, wherein the specific specification conforms to the Down_Daughter specification: the characteristics are High Speed, 0.8mm, Male, double row, SMD and 120 pins. 9.一种刀锋伺服系统，包括：9. A blade servo system, comprising: 中间平板，包括第一连接器；以及an intermediate plane including a first connector; and 刀锋服务器，包括第二连接器，用以电性连接该第一连接器，该第二连接器具有符合特定规格的多支接脚，该些接脚包括：The blade server includes a second connector for electrically connecting the first connector, the second connector has a plurality of pins meeting specific specifications, and the pins include: 第1接脚，用以作为PCI系统错误信号接脚；The first pin is used as a PCI system error signal pin; 第2接脚，用以作为PCI奇偶校验错误信号接脚；The second pin is used as a PCI parity error signal pin; 第4接脚，用以作为系统管理总线时钟信号接脚；The fourth pin is used as a system management bus clock signal pin; 第6接脚，用以作为系统管理总线数据信号接脚；The sixth pin is used as a system management bus data signal pin; 第3接脚、第5接脚、第7接脚、第8接脚、第13接脚至第16接脚、第22接脚、第23接脚以及第31接脚至第35接脚，用以作为接地接脚；Pin 3, Pin 5, Pin 7, Pin 8, Pin 13 to Pin 16, Pin 22, Pin 23, Pin 31 to Pin 35, used as a ground pin; 第9接脚至第12接脚，用以作为系统12V电源信号接脚；The 9th pin to the 12th pin are used as the system 12V power supply signal pins; 第17接脚至第21接脚，用以作为系统3.3V电源信号接脚；The 17th pin to the 21st pin are used as the system 3.3V power supply signal pins; 第24接脚、第26接脚、第28接脚以及第30接脚，用以作为系统5V电源信号接脚；The 24th pin, the 26th pin, the 28th pin and the 30th pin are used as system 5V power supply signal pins; 第25接脚、第27接脚以及第29接脚，用以作为系统1.5V电源信号接脚；The 25th pin, the 27th pin and the 29th pin are used as system 1.5V power supply signal pins; 第36接脚以及第38接脚，用以作为待机3.3V电源信号接脚；The 36th pin and the 38th pin are used as standby 3.3V power signal pins; 第37接脚，用以作为PCI存在1信号接脚；The 37th pin is used as the PCI presence 1 signal pin; 第39接脚，用以作为PCI存在2信号接脚；以及The 39th pin is used as a PCI presence 2 signal pin; and 第40接脚，用以作为PCI电源管理事件信号接脚。The 40th pin is used as a PCI power management event signal pin. 10.根据权利要求9所述的刀锋伺服系统，其中该特定规格系符合PCI_Base_Conn规格：特性为High Speed、0.8mm、Male、double row、SMD以及40支接脚。10. The blade servo system according to claim 9, wherein the specific specification conforms to the PCI_Base_Conn specification: the characteristics are High Speed, 0.8mm, Male, double row, SMD and 40 pins. 11.一种刀锋伺服系统，包括：11. A blade servo system, comprising: 中间平板，包括第一连接器；以及an intermediate plane including a first connector; and 刀锋服务器，包括第二连接器，用以电性连接该第一连接器，该第二连接器具有符合特定规格的多支接脚，该些接脚包括：The blade server includes a second connector for electrically connecting the first connector, the second connector has a plurality of pins meeting specific specifications, and the pins include: 第1接脚以及第3接脚，用以作为PCI快速A通道差动配对1发送器信号接脚；The 1st pin and the 3rd pin are used as PCI Express A-channel differential pairing 1 transmitter signal pins; 第2接脚，用以作为PCI基板存在信号接脚；The second pin is used as a signal pin on the PCI substrate; 第4接脚，用以作为PCI总线重置信号接脚；The fourth pin is used as a PCI bus reset signal pin; 第5接脚、第11接脚、第17接脚、第23接脚、第29接脚、第30接脚、第35接脚、第36接脚，用以作为接地接脚；The 5th pin, the 11th pin, the 17th pin, the 23rd pin, the 29th pin, the 30th pin, the 35th pin, and the 36th pin are used as grounding pins; 第6接脚，用以作为系统电源正常信号接脚；The sixth pin is used as the system power normal signal pin; 第7接脚以及第9接脚，用以作为PCI快速A通道差动配对3接收器信号接脚；The 7th pin and the 9th pin are used as PCI Express A channel differential pair 3 receiver signal pins; 第8接脚，用以作为系统管理总线时钟信号接脚；The eighth pin is used as a system management bus clock signal pin; 第10接脚，用以作为系统管理总线数据信号接脚；The tenth pin is used as a system management bus data signal pin; 第12接脚，用以作为系统12V电源信号接脚；The 12th pin is used as the system 12V power supply signal pin; 第13接脚以及第15接脚，用以作为PCI快速A通道差动配对3发送器信号接脚；The 13th pin and the 15th pin are used as PCI Express A channel differential pair 3 transmitter signal pins; 第14接脚，用以作为系统5V电源信号接脚；The 14th pin is used as the system 5V power supply signal pin; 第16接脚、第18接脚、第20接脚以及第22接脚，用以作为系统3.3V电源信号接脚；The 16th pin, the 18th pin, the 20th pin and the 22nd pin are used as system 3.3V power supply signal pins; 第19接脚以及第21接脚，用以作为PCI快速A通道差动配对2接收器信号接脚；The 19th pin and the 21st pin are used as PCI Express A channel differential pair 2 receiver signal pins; 第24接脚，用以作为待机3.3V电源信号接脚；The 24th pin is used as a standby 3.3V power signal pin; 第25接脚以及第27接脚，用以作为PCI快速A通道差动配对0发送器信号接脚；The 25th pin and the 27th pin are used as PCI Express A channel differential pair 0 transmitter signal pins; 第26接脚以及第28接脚，用以作为系统1.5V电源信号接脚；The 26th pin and the 28th pin are used as system 1.5V power supply signal pins; 第31接脚以及第33接脚，用以作为PCI快速A通道差动配对0接收器信号接脚；The 31st pin and the 33rd pin are used as PCI Express A channel differential pair 0 receiver signal pins; 第32接脚以及第34接脚，用以作为PCI快速A通道差动配对2发送器信号接脚；The 32nd pin and the 34th pin are used as PCI Express A-channel differential pairing 2 transmitter signal pins; 第37接脚以及第39接脚，用以作为PCI快速A通道差动配对1接收器信号接脚；以及The 37th pin and the 39th pin are used as PCI Express A channel differential pair 1 receiver signal pins; and 第38接脚以及第40接脚，用以作为PCI快速A通道时钟差动配对接收信号接脚。The 38th pin and the 40th pin are used as PCI Express A channel clock differential pair receiving signal pins. 12.根据权利要求11所述的刀锋伺服系统，其中该特定规格系符合PCI_Base_Conn规格：特性为High Speed、0.8mm、Male、double row、SMD以及40支接脚。12. The blade servo system according to claim 11, wherein the specific specification conforms to the PCI_Base_Conn specification: the characteristics are High Speed, 0.8mm, Male, double row, SMD and 40 pins.
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