CN2754070Y - Background current inhibition reading-out circuit for infrared focal plane array - Google Patents

Abstract

Background current suppression readout circuit for infrared focal plane array, the circuit includes: buffer direct injection structure, current memory of background current and dark current and related double sampling circuit, the improvement lies in the control terminal of background current and dark current memory 100 That is, the gate of the NMOS transistor 106 is sequentially connected to the PMOS transistor 108, the analog-to-digital/digital-to-analog converter 109 and the non-volatile memory 110, thereby forming a circuit for storing and automatically refreshing the saved background current and dark current. The circuit of the utility model uses the current memory to automatically suppress the background current, and uses analog-to-digital and digital-to-analog converters and non-volatile memory to keep the voltage on the capacitor in the current memory from decaying, which overcomes the existing high background current The disadvantage of requiring regular calibration with mechatronic means in use of the readout circuit is suppressed, and the circuit has a high charge handling capability.

Description

Background Current Suppression Readout Circuit for Infrared Focal Plane Array

technical field

The utility model relates to a background suppression circuit of an infrared detector, in particular to a novel background current suppression readout circuit for an infrared focal plane array, which belongs to the technical field of infrared detection.

Background technique

Currently, the performance of high background current infrared detectors such as quantum well infrared photodetectors (QWIP) mainly depends on the charge handling capability of the readout circuit. Since the background current and dark current of the infrared detector are quite large (for example, the dark current of QWIP has hundreds of nanoamps), a large integral capacitor is needed to store these charges. But in fact, in order to realize the unit circuit in a pixel with a limited size, the integrating capacitor can only be made relatively small, and the large background current will make the integrating capacitor in the readout circuit saturate very quickly; moreover, the target signal is far from It is much smaller than the background signal (for example, the target current of QWIP is only 0.01%-0.1% of the background current), therefore, it is very difficult to realize that the readout circuit has low noise and the ability to amplify large signals. Suppressing the background current is a good way to overcome this problem. By suppressing the re-integration of the background current, a smaller integration capacitor can be used in the pixel and avoid its saturation, while increasing the detection sensitivity, improving the dynamic range and SNR.

Currently there is a BGMI structure (Document 1, Chih-Cheng Hsieh, et al, High-performance CMOS Bufferedgate modulation input (BGMI) readout circuits for IR FPA, IEEE Journal of Solid-State Circuits, Vol 33, No.8, Aug, 1998, P.1188-1198) and adopt current memory structure (document 2, Yang Guang, et al, Ahigh dynamic-range, low-noise focal plane readout for VLWIR applications implemented with current mode background subtraction, Proceedings of SPIE-The International Society for Optical Engineering, Vol 3360, 1998, P.42-51) and U.S. Patent (Patent No.: US6,373,050 B1, April 16, 2002) and other methods for background current suppression. Each column of the BGMI structure shares an integral capacitor. Before integrating, the current signal output from the SCI structure is subtracted from a current generated by a threshold compensation current source. The current can be adjusted by adjusting its source voltage Vtun. However, the BGMI circuit has very high requirements for the adjustment accuracy of the source voltage of the background suppression circuit, which is usually stable to less than 1 millivolt, or even higher accuracy; and because the entire focal plane shares a background suppression circuit, the non-uniformity of the detector array The characteristic will bring very serious row or column noise, and the background suppression cannot be well realized; in addition, the driving signal of the circuit is complicated, and the output signal is not a box wave, which is also a disadvantage. Another method of background suppression is to use the current memory structure. The background suppression circuit is composed of the following parts: BDI input stage, current memory, gating tube, correlated double sampling circuit (CDS) and so on. By sampling the background current during calibration, and using a current memory to store the current, and then during the imaging period, subtracting the background current from the signal current output by the infrared detector and performing integration and correlated double sampling, the circuit increases the The ability of the readout circuit to handle large currents. Since there is a current memory in each pixel, the influence of the non-uniformity of the detector array is overcome, but the voltage on the current memory in this structure will decay with time (that is, the background current stored in the current memory will decrease with time). Attenuation), making the detection accuracy worse and worse, or even impossible to detect, so the detector needs to be calibrated every once in a while, and some mechanical devices need to be added during the calibration process (providing a uniform background object for calibration), This will destroy the continuous use performance of the infrared detector (the infrared detector cannot work during calibration), and reduce the reliability of the infrared detector.

Contents of utility models

The purpose of this utility model is to propose a background current suppression readout circuit for infrared focal plane arrays. This circuit does not need to be calibrated repeatedly after one correction, and can maintain the effect of background suppression well and continuously, reducing the mechanical strength of the detector. and time overhead, and greatly improve the reliability of the detector.

The purpose of this utility model is achieved like this: the background current that is used for infrared focal plane array suppresses readout circuit, and this circuit comprises: the electric current storer and relevant double sampling circuit of buffering direct injection structure, background current and dark current, and its improvement is The output terminal of the buffer direct injection structure circuit is connected to the background current and dark current memory 100, and is connected to the output Vout through the PMOS transistor 111 to the integrating circuit, the buffer 114, and the related double sampling circuit 115; the control terminal of the background current and the dark current memory 100 is The gate of the NMOS transistor 106 is sequentially connected to the PMOS transistor 108, the analog-to-digital/digital-to-analog converter 109 and the non-volatile memory 110, thereby forming a circuit for storing and automatically refreshing the saved background current and dark current.

The buffer direct injection structure circuit is composed of an operational amplifier 101 and a PMOS tube 102. The positive input terminal of the operational amplifier 101 is connected to the DC bias power supply Vbd, the negative input terminal is connected to the output terminal of the infrared detector 116, and the other end of the infrared detector 116 is connected to the detector bias power supply Vdet; the output terminal of the operational amplifier 101 is connected to the grid of the PMOS transistor 102; the source of the PMOS transistor 102 is connected to the output terminal of the infrared detector 116.

The current memory 100 is composed of a capacitor 103 and NMOS transistors 104, 105, 106 and 107; the drain of the NMOS transistor 105 is connected to the drain of the PMOS transistor 102, the source of the NMOS transistor 105 is connected to the drain of the NMOS transistor 104, and the NMOS transistor 105 is connected to the drain of the NMOS transistor 104. The source of 104 is connected to DC power supply Vbcm via capacitor 103, the gates of NMOS transistors 105 and 104 are respectively connected to clock signals Φmem and _Φmem , the source and drain of NMOS transistor 104 are short-circuited; the drain of NMOS transistor 107 is connected to PMOS transistor The drain of 102, the source of NMOS tube 107 is connected to the drain of NMOS tube 106; the source of NMOS tube 106 is connected to DC power supply Vbcm; the grid of NMOS tube 107 is connected to DC power supply Vbn, and the grid of NMOS tube 106 is connected to NMOS tube The drain of 104 is connected to the contact of capacitor 103, and connected to the drain of PMOS transistor 108; the control terminal of current memory 100, that is, the gate of NMOS transistor 106 is connected to the drain of PMOS transistor 108, and the source of PMOS transistor 108 is passed through the mold The digital/digital-to-analog converter 109 is connected to the non-volatile memory 110; the gate of the PMOS transistor 108 is connected to the signal Sel.

The integration circuit is composed of a capacitor 113 and a PMOS transistor 112 connected in parallel, and the gate of the PMOS transistor 112 is connected to the reset signal Rst. The circuit of the utility model uses the current memory to automatically suppress the background current, and uses analog-to-digital and digital-to-analog converters and non-volatile memory to keep the voltage on the capacitor in the current memory from decaying, which overcomes the existing high background current Suppress the disadvantage that the readout circuit needs to be regularly calibrated by mechanical and electronic devices during use. The circuit does not need to be calibrated repeatedly after one calibration, which can maintain the effect of background suppression well and continuously, reduce the mechanical and time overhead of the detector, and Greatly improve the reliability of the detector. And the circuit has a high charge handling capability.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment, the utility model is further described.

Figure 1 is a schematic diagram of the novel background current suppression circuit.

Figure 2 is a schematic diagram of the control pulse timing of the circuit.

Detailed ways

The utility model is composed of the following parts: traditional buffer direct injection BDI level, background current and dark current memory, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) and memory (EPROM), integral circuit, CDS circuit wait. 116 in FIG. 1 represents an infrared detector with a large background current such as a quantum well or mercury cadmium telluride. The operational amplifier 101 and the PMOS transistor 102 form a buffer direct injection structure BDI, and the current memory is composed of a capacitor 103 and NMOS transistors 104, 105, 106, and 107. When the clock signal Φmem is high and _Φmem is low, the current memory stores the current. PMOS transistor 108 , ADC and DAC 109 , EPROM 110 and current memory 100 constitute the core part of the background suppression correction circuit, and NMOS transistor 104 shorted from source to drain is used to reduce switching noise and improve suppression accuracy. Digital-to-analog converters and analog-to-digital converters can be implemented on-chip or off-chip. The signal Sel applied to the PMOS transistor 108 is used to control the transmission of the correction voltage, and the EPROM 110 is used to store the control voltage signal corresponding to the background current of each detection unit. The drain of the PMOS tube 102 is connected to the drain of the NMOS tube 107 of the current memory 100 and the source of the PMOS tube 111, and 113 is an integrating capacitor Cint, which can be reset by the PMOS switch 112, and the on and off of the PMOS switch 112 Off is controlled by a reset signal Rst applied to its gate. After the integrated signal passes through the buffer Buf 114, it is sent to the correlated double sampling circuit CDS 115 for processing. CDS 115 can adopt the "New Structure Correlated Double Sample and Hold Circuit" with the patent No. ZL 02 2 45464.0. CDS can achieve the purpose of eliminating and reducing 1/f noise, switching noise, KTC noise and fixed pattern noise.

As shown in Figure 1, the BDI input stage provides a stable bias voltage for the detector. Because of its low input impedance, it is beneficial to improve injection efficiency. The greater the open-loop gain of the operational amplifier in the BDI input stage, the greater the input impedance The smaller the value, the higher the injection efficiency. The gate voltage Vbn of the NMOS transistor 107 in the current memory 100 is a DC bias voltage, and the source of the NMOS transistor 106 is connected to the DC voltage Vbcm.

In Fig. 2, t1 to t3 is the detector calibration period, during which there is no infrared radiation signal, and after t3 is the detector readout period. During the period from t1 to t2, no infrared signal is injected, and the background current of the detector reaches point A through the BDI input stage. Since Φmem is at a high level at this time, the NMOS tube 105 is turned on, and the background current of the detector charges the capacitor 103, and the NMOS tube The gate voltage of 106 (that is, the voltage on capacitor 103 ) rises, and when the gate voltage of NMOS transistor 106 is greater than its threshold voltage, NMOS transistors 106 and 107 are turned on. With the charging of the capacitor 103, the charging current flowing through the capacitor 103 decreases continuously, while the current flowing through the NMOS transistors 106 and 107 increases continuously, until all the current from the detector flows through the NMOS transistors 106 and 107, and the capacitor Voltage on 103 no longer increases. During the period from t2 to t3, the strobe signal Sel is at a low level, so that the PMOS transistor 108 is turned on, and the ADC converts the voltage signal on the capacitor 103 into a digital signal and stores it in the EPROM 110 . From t3 to t5 is the imaging readout period. At this time, Φmem is at a low level, and the signal Read at the gate of the PMOS transistor 111 is at a DC level. After deducting the background current Imem stored in the current memory 100, the detector current signal Idet from the BDI passes through the PMOS transistor 111 and flows into the integration capacitor 113 for integration. The current flowing into the integration capacitor is (Idet-Imem), and the integration period Rst is high level, the PMOS transistor 112 is turned off. The integrated voltage enters the correlated double sampling circuit 115 after passing through the buffer 114 . When Rst is at a low level, the PMOS transistor 112 is turned on to reset the capacitor 113 . Vout1 is the signal output at the first sampling after reset, and Vout2 is the signal output at the second sampling at the end of integration. Due to the existence of leakage current, the voltage on the capacitor 103 in the current memory 100 will decay after a period of time, affecting the background current suppression accuracy. At this time, through the corresponding control signal, use the voltage value stored in the memory to restore the voltage on the capacitor 103 to the value after the first correction. This process is the period from t5 to t6 in FIG. 2 . Se1 is low again during t5 to t6, and the 12-bit digital signal of the original voltage stored in the EPROM 110 is converted into a corresponding analog voltage output by the DAC, so that the voltage on the capacitor 103 is restored to the value after the first correction. Relying on DAC and EPROM to periodically refresh the voltage value on the capacitor 103 [automatically completed by the sequential circuit without any mechanical action, and the refresh time is very short (millisecond order)], like this, the detector after a correction can be continuously Accurately perform background current suppression in the infrared scene to be tested without the need for recalibration.

The digital-to-analog/analog-to-digital converter 109 and the memory 110 can be implemented on-chip, or external devices can be used. When the digital-to-analog/analog-to-digital converter 109 and the memory 110 are implemented off-chip, the analog-to-digital converter ADC can be selected from ADS803, the digital-to-analog converter DAC can be selected from TLV5619, and the memory can be selected from AM29LV400. The selected devices are not limited to the above models.

The utility model is not limited to the above-mentioned embodiment, no matter any changes are made in its structure, whenever the background current is automatically suppressed by using the current memory, and the analog-to-digital and digital-to-analog converters and non-volatile memory are used to keep the current in the current memory Circuits in which the voltage on the capacitor does not attenuate all fall within the protection scope of the present invention.

Claims (4)

1. A background current suppression readout circuit for infrared focal plane arrays, the circuit includes: a buffer direct injection structure, a current memory for background current and dark current and a related double sampling circuit, characterized in that: the output of the buffer direct injection structure circuit Terminate background current and dark current memory (100), and connect output Vout to integration circuit, buffer (114), relevant double sampling circuit (115) through PMOS tube (111); Background current and dark current memory (100) The control terminal is the gate of the NMOS transistor (106), which is sequentially connected to the PMOS transistor (108), the analog-to-digital/digital-to-analog converter (109) and the non-volatile memory (110), thereby forming the background saved by storage and automatic refresh Current and dark current circuits. 2. The background current suppression readout circuit according to claim 1, characterized in that: the buffer direct injection structure circuit is composed of an operational amplifier (101) and a PMOS transistor (102), and the positive input terminal of the operational amplifier (101) Connect the DC bias power supply Vbd, the negative input terminal is connected to the output terminal of the infrared detector (116), and the other end of the infrared detector (116) is connected to the detector bias power supply Vdet; the output terminal of the operational amplifier (101) is connected to the PMOS tube ( 102) grid; the source of the PMOS tube (102) is connected to the output of the infrared detector (116). 3. The background current suppression readout circuit according to claim 1 or 2, characterized in that: the current memory (100) is composed of a capacitor (103) and an NMOS transistor (104-107); the NMOS transistor (105) The drain is connected to the drain of the PMOS tube (102), the source of the NMOS tube (105) is connected to the drain of the NMOS tube (104), the source of the NMOS tube (104) is connected to the DC power supply Vbcm through the capacitor (103), and the NMOS tube The gates of (105, 104) are respectively connected to the clock signal Φmem, _Φmem , and the source and drain of the NMOS transistor (104) are short-circuited; the drain of the NMOS transistor (107) is connected to the drain of the PMOS transistor (102), and the NMOS The source of the tube (107) is connected to the drain of the NMOS tube (106); the source of the NMOS tube (106) is connected to the DC power supply Vbcm; the grid of the NMOS tube (107) is connected to the DC power supply Vbn, and the grid of the NMOS tube (106) pole is connected with the drain of the NMOS tube (104) and the junction of the capacitor (103), and connected to the drain of the PMOS tube (108); The drain of (108), the source of the PMOS tube (108) is connected to the nonvolatile memory (110) through the analog-to-digital/digital-to-analog converter (109); the gate of the PMOS tube 108 is connected to the signal Sel. 4. The background current suppression readout circuit according to claim 1, characterized in that: the integration circuit is composed of a capacitor (113) and a PMOS transistor (112) connected in parallel, and the gate of the PMOS transistor (112) is connected to the reset signal Rst .