CN2741188Y - Structure of Antifuse Memory Components - Google Patents

Abstract

A structure of an antifuse-type memory element, comprising: the fuse structure comprises a metal silicide layer, a first type conducting layer, an antifuse layer and a second type conducting layer, wherein the first type conducting layer is arranged on the metal silicide layer, the antifuse layer is arranged on the first type conducting layer, and the second type conducting layer is arranged on the antifuse layer. According to the structure of the present invention, since a polysilicon layer is reduced as compared with the prior art, the total resistance of the polysilicon layer and the silicide layer is low, and the driving current of the antifuse-type memory device can be increased.

Description

Structure of Antifuse Memory Components

technical field

The utility model relates to a structure improvement of a semiconductor component, in particular to a structure for improving the polysilicon and metal silicide process of an anti-fuse type memory component.

Background technique

The antifuse type memory component is a three-dimensional memory component, and its memory unit is an antifuse layer arranged between the anode and cathode of the diode for control. When the antifuse layer is intact, its anode and cathode are disconnected from each other, but when the antifuse layer is damaged, its anode and cathode form a diode, and its wiring is designed so that the materials of the anode and cathode are orthogonal to each other. Compared with the traditional two-dimensional structure memory, the three-dimensional anti-fuse memory component requires a smaller silicon footprint than the traditional memory. Therefore, the activeness of the memory can be increased and the cost per unit area can be reduced. In addition, the anti-fuse type memory device can provide better protection in terms of confidentiality due to its one-time programming (OTP) feature.

Please refer to FIG. 1A to FIG. 1D , which are schematic cross-sectional views of the polysilicon metal silicide manufacturing process of the conventional antifuse type memory device. As shown in FIG. 1A, the metal wire and its inter-wire dielectric layer have been fabricated on the semiconductor substrate 100, which is omitted here for a simplified illustration, and a doped P+ is deposited on the metal wire and its inter-wire dielectric layer. The polysilicon layer is used as the bottom polysilicon layer 110 . Thereafter, an undoped polysilicon or amorphous silicon layer is deposited on the bottom polysilicon layer 110 as the reactive polysilicon layer 111 . Next, a titanium metal layer 119 and subsequent titanium nitride layer 120 are deposited on the undoped polysilicon or amorphous silicon layer 111 .

Next, as shown in FIG. 1B , a rapid tempering process is used to react the polysilicon layer with the titanium metal layer 119 and part of the titanium nitride layer 120 to form a titanium silicon compound layer 130 . The formed titanium-silicon compound layer 130 has low electrical conductivity and good thermal stability, which can reduce the resistance between wires. Afterwards, a P+ doped polysilicon layer is deposited on the titanium silicon compound as the first type conductive layer 135 .

Subsequently, as shown in FIG. 1C , a thermal oxidation process is performed to form an antifuse layer 136 on the first-type conductive layer 135 . The formed antifuse layer 136 is the main component for controlling the antifuse type memory cells. Thereafter, the previously formed antifuse layer 136, titanium silicon compound layer 130, first-type conductive layer 135 and bottom polysilicon layer 110 are defined to form word lines, which includes lithography, etching and forming wires and filling between wires The dielectric material and the subsequent CMP process are generally known techniques and will not be described in detail here. Finally, as shown in FIG. 1D , an N-doped polysilicon layer is deposited as the second-type conductive layer 140 , and the second-type conductive layer 140 is defined to form a bit line.

Please refer to FIG. 3 , which is a three-dimensional view of the polysilicon metal silicide manufacturing process of the existing antifuse memory component. The bottom polysilicon layer 110 is formed on the semiconductor substrate 100, and there are bottom polysilicon layer 110, titanium silicon compound in sequence thereon. layer 130 , titanium nitride layer 120 , first type conductive layer 135 . The bottom polysilicon layer 110, the titanium-silicon compound layer 130 and the first-type conductive layer 135 serve as word lines (WL). The second-type conductive layer 140 serves as a bit line (BL) and an antifuse layer 136 is sandwiched between it and the first-type conductive layer 135 .

In this process, when forming the titanium metal silicide, a P+ polysilicon layer and a subsequent non-doped polysilicon or amorphous silicon layer need to be deposited. The deposited titanium metal layer is heated so that the titanium metal layer reacts with the underlying undoped polysilicon or amorphous silicon layer to form a titanium metal silicide layer. Thereafter, a layer of polysilicon doped with P+ is deposited. The steps for forming the first-type conductive layer are quite cumbersome, and the multi-layer polysilicon deposition must continuously take out the entire batch of wafers from the previous reactor and put them into the pre-reaction reactor, which is not only complicated, but also takes a long time Waiting for vacuuming to reach the standard reaction chamber pressure consumes a lot of process time.

U.S. Patent Application No. 09/560626 discloses a memory cell with low leakage current, in which an antifuse layer is placed between the positive and negative diodes, and when the antifuse layer is intact, the positive and negative electrodes are disconnected from each other , but when the anti-fuse layer is destroyed, its anode and cathode are connected in a small area of the anti-fuse layer, and thus a diode is formed, and because of its small area of fuse, the diode has a small range area , and therefore it has a relatively small leakage current. In addition, U.S. Patent No. 6,525,953 discloses a three-dimensional, programmable, non-volatile memory cell by means of a self-aligned column containing the anode and cathode components of a diode, and an antifuse therebetween The filament layer, and the pillars form its memory cells. Its operating principle is also based on whether the antifuse layer is intact or damaged, forming a circuit and determining the stored data.

Therefore, in order to overcome the above-mentioned existing method, that is, the shortcomings of using doped polysilicon in the positive and negative components of the diode, the utility model is produced.

Utility model content

In view of this, in order to solve the above problems, an object of the present invention is to provide a simplified anti-fuse memory component structure, which can reduce the deposition steps of polysilicon, to simplify the process of forming metal silicide, and reduce the process time , and reduce manufacturing costs.

Another object of the present utility model is to provide a structure of an antifuse type memory component, which can reduce the overall resistance of polysilicon and silicide layers by reducing a polysilicon layer, and thus increase the antifuse type memory component drive current.

The utility model proposes a polysilicon and silicide structure of an antifuse type memory component, which includes: a metal silicide layer, a first-type conductive layer on the metal silicide layer, and an antifuse layer on the second On the first-type conductive layer, and on the second-type conductive layer on the anti-fuse layer. According to the structure of the utility model, because it reduces a polysilicon layer compared with the prior art, the overall resistance of the polysilicon and silicide layers is lower, and the driving current of the anti-fuse memory component can be increased.

Description of drawings

1A to 1D are schematic cross-sectional views of polysilicon and metal silicide manufacturing processes of existing antifuse memory components;

2A to 2D are schematic cross-sectional schematic diagrams of the polysilicon and metal silicide manufacturing process of the antifuse memory component of the embodiment of the present invention;

3 is a perspective view of a metal silicide manufacturing process of polysilicon in an existing antifuse type memory component;

FIG. 4 is a perspective view of the polysilicon metal silicide manufacturing process of the antifuse memory element of the present invention.

Symbol Description:

current technology:

100. Semiconductor substrate 110. Bottom polysilicon layer 111. Reactive polysilicon layer

119. Titanium metal layer 120. Titanium nitride layer 130. Titanium silicon compound layer

135. First type conductive layer 136. Antifuse layer 140. Second type conductive layer

The utility model technology:

200. Semiconductor substrate 210. Titanium nitride layer 212. Titanium metal layer

220. Reactive polysilicon layer 230. First-type conductive layer 240. Titanium metal silicide layer

235. Antifuse layer 250. Second-type conductive layer

Detailed ways

In order to make the technical problems, features, and advantages of the present utility model more obvious and easy to understand, a preferred embodiment is specially cited below, together with the accompanying drawings, as follows:

Please refer to FIG. 2A to FIG. 2D , which are process cross-sectional views of an embodiment of a simplified manufacturing method of an anti-fuse memory device according to the present invention. In the description of this embodiment, the substrate includes components formed on the semiconductor wafer, such as gates and the like.

First, as shown in FIG. 2A, a semiconductor substrate 200 is provided, and metal wires and dielectric layers between wires have been formed on the semiconductor substrate 200. The metal wires can be copper metal or tungsten metal, and the dielectric layers between the wires are The layers may be undoped silica glass, silicon dioxide with tetraethoxysilane as the silicon source, or other dielectric materials. Thereafter, a titanium nitride layer 210 and a subsequent titanium metal layer 212 are deposited. Titanium nitride can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Titanium metal is formed by physical vapor deposition. method (PVD) deposition. The thickness of titanium nitride is 25-250 angstroms, which is used as the bonding layer between the titanium silicon compound and the underlying metal wires, and the thickness of titanium metal is 200-800 angstroms, which is used as the source of the titanium silicon compound formed later.

Thereafter, deposit an undoped polysilicon layer or amorphous silicon layer as the reaction polysilicon layer 220 on the titanium metal layer 212, which uses a chemical vapor deposition method (CVD), at a reaction temperature of 450°C-800°C, The reaction pressure is deposited under the condition of 0.1Torr-10Torr, and the thickness of the reaction polysilicon layer 220 is 200-1500 angstroms, which is to react with the underlying titanium metal layer 212 and part of the titanium nitride layer 210 to form subsequent titanium silicon compound layer. Next, deposit a first-type conductive layer 230 on the reactive polysilicon layer, which may be a P+-doped polysilicon layer, which is also formed by chemical vapor deposition (CVD), but this polysilicon layer is used for conduction and diode formation, It needs to have a lower resistivity, so the resistivity is reduced by doping, and the doped impurity is boron or other trivalent elements. Moreover, after the chemical vapor deposition (CVD) reaction of the polysilicon, impurities can be drawn in by a high-temperature diffusion method, or ion implantation can be used after deposition, and the impurities can be implanted into the polysilicon in the form of ions. , or during the deposition reaction of polysilicon, impurities are infiltrated simultaneously (In-situ), and the thickness of the first-type conductive layer 230 formed therein is 300-2000 angstroms.

Subsequently, as shown in Figure 2B, a thermal process, which can be a rapid heating process or a furnace tube process, is introduced at a temperature of 400°C-1200°C with an inert gas to make the previously formed titanium/titanium nitride layer 210 reacts with the reactive polysilicon layer 220 to form a titanium silicide layer 240 , and the formed titanium silicide layer 240 has characteristics of low resistance and thermal stability.

Thereafter, as shown in FIG. 2C, a thermal process is carried out, which can be a rapid heating process or a furnace tube process. At a temperature of 400°C-1200°C, oxygen is introduced to generate silicon dioxide on the surface of the first-type conductive layer. layer, the thickness of the silicon dioxide layer is 5-200 angstroms, as the antifuse layer 235 controlling the antifuse type memory device, so the quality and uniformity control of the antifuse layer 235 is quite important.

Next, define the previously formed antifuse layer 235 , the titanium-silicon compound layer 240 and the first-type conductive layer 230 to form word lines, which include lithography and etching and other prior art techniques that will not be described in detail here. After the wires are formed, a dielectric material is filled between the wires. It can be silicon dioxide formed by a high-density plasma (HDP) chemical vapor deposition method. The ion concentration in the plasma is higher than that of the general plasma excited chemical The vapor deposition method is concentrated, so the method of deposition/etching/deposition can be used, and it has better trench filling ability, and can be filled into the gap after the wire is formed. Next, the redundant dielectric layer is removed and planarized by chemical mechanical polishing (CMP).

Next, as shown in FIG. 2D, the second-type conductive layer 250 is deposited on the antifuse layer 235, which can be a polysilicon layer doped with N+, and a chemical vapor deposition method (CVD) is applied at a reaction temperature of 450 °C-800 °C, the reaction pressure is deposited under the condition of 0.1 Torr-10 Torr, and the thickness is 1000-6500 Angstroms. The second-type conductive layer is used for conduction and forms a diode function with the previously formed first-type conductive layer, so it also needs a lower resistivity, and the doped impurity is arsenic or other pentavalent elements. The method of its implantation can also use the high temperature diffusion method to attract impurities, or use the ion implantation method. It should be noted that the type of the second-type conductive layer 250 needs to be opposite to that of the previously formed first-type conductive layer 230. In other words, the polysilicon layer deposited in this step can also be of the P+ type, while the previously deposited polysilicon is N+ type.

Thereafter, the second-type conductive layer 250 is defined to form bit lines, which includes masking, developing, and etching. After the wires are formed, a dielectric material is filled between the wires, which is also silicon dioxide formed by a high-density plasma (HDP) chemical vapor deposition method, and filled into the gaps after the wires are formed. After that, chemical Mechanical polishing (CMP) removes and planarizes the excess dielectric layer.

Please refer to FIG. 4 , which is a perspective view showing the polysilicon metal silicide manufacturing process of the antifuse type memory component of the present invention. The titanium metal silicide layer 240 is formed on the semiconductor substrate 200, and it is formed with the first type conductive layer 230. is a word line (WL) and the second type conductive layer 250 is used as a bit line (BL). There is a titanium nitride layer 210 between the titanium metal silicide layer 240 and the semiconductor substrate 200 for adhesion, and an antifuse layer 235 is between the first-type conductive layer 230 and the second-type conductive layer 250 .

Therefore, the utility model reduces the overall resistivity of the polysilicon and silicide layers by reducing a polysilicon layer, thereby increasing the driving current of the anti-fuse type memory device. In addition, because the anti-fuse type memory component provided by the utility model has one less polysilicon layer than the prior art, the purpose of cost reduction can also be achieved.

Although the present utility model has been disclosed above with preferred embodiments, it is not intended to limit the present utility model. Anyone skilled in the art can make some changes and modifications without departing from the concept and scope of the present utility model. , so the scope of protection of the present utility model should be defined by the claims.

Claims (12)

1. A structure of an antifuse type memory component, characterized in that, comprising: a metal silicide layer; a first type conductive layer on the metal silicide layer; an antifuse layer on the first type conductive layer; and A second type conductive layer is on the antifuse layer. 2. The structure of the anti-fuse memory device according to claim 1, wherein the first type conductive layer is P-type and the second type conductive layer is N-type. 3. The structure of the anti-fuse memory element according to claim 1, wherein the first type conductive layer is N-type and the second type conductive layer is P-type. 4. The structure of the antifuse memory device according to claim 1, wherein the metal silicide layer is composed of titanium silicon compound, cobalt silicon compound, or nickel silicon compound. 5. The structure of the antifuse type memory device according to claim 1, wherein the antifuse layer is silicon dioxide or silicon nitride. 6. A structure of an antifuse type memory component, comprising: a first conductor; an adhesive layer is located on the first wire; A metal silicide layer is located on the adhesive layer; A first-type conductive layer is located on the first wire; an antifuse layer is located on the first type conductive layer; and A second-type conductive layer is located under a second wire, the first wire and the second wire are perpendicular to each other, and the antifuse layer between the first-type conductive layer and the second-type conductive layer is a rectangular area, And only when the antifuse layer is broken, the first-type conductive layer and the second-type conductive layer can form a diode. 7. The structure of the anti-fuse memory device according to claim 6, wherein the first wire and the second wire are made of tungsten, aluminum, or copper. 8. The structure of the anti-fuse memory device according to claim 6, wherein the metal silicide layer is composed of titanium silicon compound, cobalt silicon compound, or nickel silicon compound. 9. The structure of the anti-fuse memory device according to claim 6, wherein the first type conductive layer and the second type conductive layer are P-type or N-type. 10 . The structure of the antifuse memory device according to claim 6 , wherein the first-type conductive layer and the second-type conductive layer are different from each other. 11 . 11. The structure of the antifuse type memory device according to claim 6, wherein the antifuse layer is silicon dioxide or silicon nitride. 12. The structure of the antifuse memory device according to claim 6, wherein the adhesive layer is titanium nitride, cobalt nitride or nickel nitride.

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