CN2685925Y - pixel structure - Google Patents

Abstract

A pixel structure is formed by forming a conductive layer simultaneously with a data line and source/drain electrodes, the conductive layer having a coupling portion as an upper electrode of a pixel storage capacitor and a connection portion connecting the coupling portion and the drain electrodes together. Then, a contact window opening is limited above the connecting part, so that the pixel electrode formed subsequently can be electrically contacted with the connecting part of the conducting layer through the contact window opening. In this way, the pixel electrode, the conductive layer (including the coupling portion) and the drain electrode are electrically connected to each other. Because the contact window of the present invention is not formed directly over the pixel storage capacitor, the pixel storage capacitor does not leak electricity even though the etching process of the contact window may etch through the gate insulating layer.

Description

pixel structure

technical field

The utility model relates to a pixel structure of a thin film transistor array (Thin Film TransistorArray) substrate, and in particular to a pixel structure capable of preventing leakage of pixel storage capacitors.

Background technique

The thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer, wherein the thin film transistor array substrate is composed of a plurality of thin film transistors arranged in an array and a pixel electrode ( Pixel Electrode) to form multiple pixel structures. The above thin film transistor includes a gate, a channel layer, a drain and a source, which are used as switching elements of the liquid crystal display unit.

Please refer to FIG. 1 , which is a schematic top view of a pixel structure of a conventional thin film transistor array substrate. The pixel structure is disposed on a substrate (not shown), which includes a scan line 102 , a data line 104 , a thin film transistor 130 , a pixel storage capacitor 116 and a pixel electrode 112 .

Wherein, the thin film transistor 130 includes a gate 106, a channel layer 108 and a source/drain 110a/110b, and the gate 106 is electrically connected to the scanning line 102, the source 110a is electrically connected to the data line 104, and the drain 110b It is electrically connected to the pixel electrode 112 through the contact window 114 .

In addition, the pixel storage capacitor 116 includes a lower electrode 118 , an upper electrode 120 and a capacitive dielectric layer between the lower electrode 118 and the upper electrode 120 , and the upper electrode 120 is electrically connected to the pixel electrode 112 through the contact window 122 . Wherein, the lower electrode 118 is a common line, which belongs to the first metal layer ( M1 ) like the scan line 102 and the gate 106 . The upper electrode 120 and the data line 104 and the source/drain 110 a / 110 b also belong to the second metal layer ( M2 ). A gate insulating layer (not shown) is arranged between the first metal layer and the second metal layer, and a protective layer (not shown) is arranged between the second metal layer and the pixel electrode 112 .

It is particularly worth mentioning that generally two edges of the substrate are provided with terminal portions (not shown) for electrical connection with the driving circuit, wherein the terminal portion is a part of the first metal layer (M1), and The data lines 104 and the scan lines 102 extending to the edge of the substrate are electrically connected to the terminals.

In order to expose the terminal portion so that it can be electrically connected with the driving circuit, it is necessary to etch away the gate insulating layer and the protection layer above the terminal portion. However, for the contact windows 114 and 122, only the protective layer needs to be etched away, especially for the contact window 122 on the pixel storage capacitor 116, only the protective layer can be etched away, and this place must be kept. The gate insulating layer is used to avoid leakage between the upper and lower electrodes 118 and 120 of the pixel storage capacitor 116 . Therefore, the etching step of the protective layer and the gate insulating layer is a critical and difficult technique for the manufacture of thin film transistors.

In the prior art, in order to overcome the above problems, one method is to form an additional layer of amorphous silicon layer under the contact window, which is defined at the same time as the channel layer of the thin film transistor. In other words, the amorphous silicon layer is used as a barrier layer to prevent the gate insulating layer under the contact window from being etched through. However, this method must adjust the etch selectivity ratio between the amorphous silicon and the gate insulating layer, so it is not easy to implement.

Another existing method is to first form an opening in the lower electrode under the contact window, that is, hollow out the place corresponding to the lower electrode under the contact window, so that even if the gate insulating layer under the contact window is Etching will not cause leakage between the upper electrode and the lower electrode. However, this method still has its disadvantages, that is, after digging the openings in the lower electrodes, it is still difficult to align the openings of the contact windows with the openings in the lower electrodes.

Utility model content

Therefore, the purpose of this utility model is to provide a pixel structure to solve the problem of the upper and lower electrodes of the pixel storage capacitor of the pixel structure that is prone to occur in the etching step of the gate insulating layer and the protective layer in the manufacture of the prior art thin film transistor. Leakage problem.

The utility model proposes a pixel structure, which includes: a scanning line configured on a substrate; a common line configured on the substrate as a lower electrode of a pixel storage capacitor; a grid insulating layer configured on the substrate on, covering the scanning line and the common line; a data line, arranged on the gate insulating layer; a switching element, arranged on the substrate, wherein the switching element is electrically connected with the scanning line and the data line; a conductive layer, arranged on the gate On the pole insulating layer, wherein the conductive layer has a coupling part and a connecting part, the coupling part is located above the common line, which is used as the upper electrode of the pixel storage capacitor, and the connecting part connects the coupling part and the switching element; a protective layer, Covering the data line, the switch element and the conductive layer; a contact window configured in the protective layer above the connecting portion; and a pixel electrode configured on the protective layer, wherein the pixel electrode is connected to the switch element and the conductive layer through the contact window The coupling part is electrically connected.

In a preferred embodiment, the connection part of the conductive layer is designed as a multi-channel structure, which includes a first part used to connect with the switching element, a second part used to connect with the coupling part, and a channel between the first part and the second part. The third part between the parts, the third part is the design of the multi-channel structure. The protective layer covers the data line, the switch element and the conductive layer, and the flat layer is disposed on the protective layer. In addition, the contact window is configured in the planar layer and the protective layer on the connecting portion. In a preferred embodiment, the contact window is configured in the planar layer and the protective layer on a channel in the multi-channel structure of the connecting portion. The pixel electrodes are disposed on the surface of the planar layer, wherein the pixel electrodes are electrically connected to the connecting portion of the conductive layer through the contact window. Since the switching element is connected to the conductive layer, and the pixel electrode is electrically connected to the connecting portion of the conductive layer, the pixel electrode, the entire conductive layer (including the coupling portion) and the switching element are electrically connected to each other.

Since the pixel structure of the present invention is electrically connected to the pixel electrode, the drain electrode, and the upper electrode of the pixel storage capacitor through the same contact window, the pixel structure of the present invention is different from the existing one. pixel structure design.

Since the contact window of the pixel structure of the present invention is not arranged above the pixel storage capacitor, even if the etching step of the protective layer and the gate insulating layer will etch through the gate insulating layer, it will not cause the upper pixel storage capacitor. , Leakage occurs between the lower electrodes.

Description of drawings

FIG. 1 is a schematic top view of a pixel structure in an existing thin film transistor array substrate;

2 is a schematic top view of a pixel structure in a thin film transistor array substrate according to a preferred embodiment of the present invention;

Fig. 3 is the schematic sectional view of Fig. 2 by I-I '; And

FIG. 4 is a top view of the conductive layer in FIG. 2 .

Detailed ways

In order to make the above and other objectives, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

Please refer to FIG. 2 and FIG. 3, FIG. 2 is a top view of a pixel structure in a thin film transistor array substrate according to a preferred embodiment of the present invention, and FIG. 3 is a schematic cross-sectional view from I-I' in FIG. 2. The manufacturing method of the pixel structure of the present invention first provides a substrate 200, wherein the substrate 200 is, for example, a glass substrate or a plastic substrate. Afterwards, a gate 206, a scan line 202 electrically connected to the gate 206, and a common line 218 parallel to the scan line 202 are formed on the substrate 200, and the common line 218 is subsequently used as the lower electrode of the pixel storage capacitor 216 . The gate 206 , the scan line 202 and the common line 218 belong to the first metal layer ( M1 ).

Here, the first metal layer further includes a plurality of terminal portions (not shown), which are formed at two edges of the substrate 200 , and the scan lines 202 formed above and the data lines formed subsequently extend to the substrate 200 The edge of each will be electrically connected with the terminal part.

Next, a gate insulating layer 205 is formed on the substrate 200 to cover the first metal layer (including the gate 206 , the scanning line 202 and the common line 218 ). In a preferred embodiment, the material of the gate insulating layer 205 is, for example, silicon nitride or silicon oxide.

Afterwards, a channel layer 208 is formed on the gate insulating layer 205 above the gate 206 . In a preferred embodiment, the material of the channel layer 208 is, for example, amorphous silicon, and an ohmic contact layer (not shown) is formed on the surface of the channel layer 208 to improve the connection between the channel layer 208 and the subsequently formed source electrode. / Electrical contact between the drain.

Subsequently, a data line 204 and a conductive layer 250 are formed on the gate insulating layer 205 (as shown in FIG. 250 and source/drain 210a/210b belong to the second metal layer (M2). Wherein, the source 210a is electrically connected to the data line 204, and the gate 206, the channel layer 208 and the source/drain 210a/210b form a thin film transistor.

The conductive layer 250 formed above has a coupling portion 220 and a connecting portion 240, wherein the coupling portion 220 is formed above the common line 218, which serves as the upper electrode of the pixel storage capacitor 216, and the connecting portion 240 connects the coupling portion 220 to the drain. Pole 210b is connected.

Especially, in a preferred embodiment, the connection portion 240 of the conductive layer 250 can be defined as a multi-channel structure. As shown in FIG. The second part 226b connected, and the third part 224 between the first part 226a and the second part 226b, the third part 224 is a multi-channel structure, three channels 224a, 224b, 224c are shown in the figure as an example To illustrate, but not to limit the utility model. The purpose of making such a multi-channel structure is that when the opening of the contact window is subsequently defined, it will be defined above one of the channels, for example, above the middle channel 224b. The other passages 224a, 224c serve as conduction carriers. If one of the passages (such as the passage 224a) fails to conduct due to manufacturing factors or other factors, the remaining passages (such as the 224c) can continue Take on the task of the conduction carrier without making the entire pixel structure inoperable due to the above reasons.

It is particularly worth mentioning that a light-shielding layer 222 can be formed under the third portion 224 of the connecting portion 240, and this light-shielding layer 222 is part of the first metal layer. , the scan line 202 and the common line 218 are simultaneously defined. The purpose of forming the light-shielding layer 222 here is to shield the light scattering phenomenon caused by the subsequent formation of the contact window thereon.

After forming the second metal layer (including the data line 204, the conductive layer 250 and the source/drain 210a/210b), a protection layer 211 is formed on the substrate 200 to cover the second metal layer, wherein the protection layer 211 The material is, for example, silicon nitride or silicon oxide. Subsequently, a flat layer 213 is formed on the protection layer 211 , wherein the material of the flat layer 213 is, for example, an organic photosensitive material.

Afterwards, the planarization layer 213 and the passivation layer 211 are patterned to form a contact window opening 228 in the planarization layer 213 and the passivation layer 211 to expose a part of the connection portion 240 of the conductive layer 250 . In a preferred embodiment, the contact window opening 228 exposes one of the channels 224b of the connecting portion 240 . Here, if the second metal layer uses a titanium/aluminum double-layer metal layer as its material, then during the etching process for defining the contact window opening 228, it may be desirable to remove the aluminum layer on the upper layer of the channel 224b at the same time, leaving the lower layer Therefore, the thickness of the channel 224b in FIG. 3 is obviously smaller than that of the channels 224a and 224c.

It is particularly worth mentioning that since the contact opening 228 of the present invention is not defined directly above the pixel storage capacitor 216, even the etching step for defining the contact opening 228 will etch through the gate insulating layer 205, It will not cause leakage between the upper and lower electrodes 218 and 220 of the pixel storage capacitor 216 . Moreover, if this etching step will etch through the gate insulating layer 205, since the light-shielding layer 222 is disposed under the contact window opening 228, which is a film layer that is not electrically connected to other conductive material layers, it still does not Will have adverse effects on the entire component.

Afterwards, a pixel electrode 212 is formed on the surface of the planar layer 213 , wherein the pixel electrode 212 is electrically connected to the connection portion 240 (ie, the channel 224 b ) of the conductive layer 250 through the contact window opening 228 .

Since the coupling portion 220 of the conductive layer 250 is connected to the drain 210b of the thin film transistor 230 through the connection portion 240, and the pixel electrode 212 is electrically connected to the connection portion 240, the pixel electrode 212, the conductive layer 250 (including The coupling part 220 and the connecting part 240) and the drain 210b of the thin film transistor 230 are electrically connected to each other.

The pixel structure of the present utility model includes a scanning line 202, a common line 218, a gate insulating layer 205, a data line 204, a switching element 230 (such as a thin film transistor), a conductive layer 250, a protective layer 211, A flat layer 213 , a contact window 228 and a pixel electrode 212 .

Wherein, the scan line 202 is disposed on a substrate 200 , and the common line 218 is also disposed on the substrate 200 , which serves as the lower electrode of the pixel storage capacitor 216 , and the common line 218 is disposed parallel to the scan line 202 .

The gate insulating layer 205 is disposed on the substrate 200 and covers the scan lines 202 and the common lines 218 . The data line 204 is disposed on the gate insulating layer 205 .

In addition, the switching element 230 is, for example, a thin film transistor, which is disposed on the substrate 200. The thin film transistor 230 has a gate 206, a channel layer 208, and a source/drain 210a/210b, wherein the gate 206 is connected to the scan line 202 is electrically connected, the channel layer 208 is disposed on the gate insulating layer 205 above the gate 206 , the source/drain 210 a / 210 b is disposed on the channel layer 208 , and the source 210 a is electrically connected to the data line 204 .

In addition, the conductive layer 250 is disposed on the gate insulating layer 205, and the conductive layer 250 has a coupling portion 220 and a connecting portion 240, wherein the coupling portion 220 is located above the common line 218, which serves as the upper electrode of the pixel storage capacitor 216, The connection part 240 connects the coupling part 220 and the drain 210 b of the thin film transistor 230 . In the preferred embodiment shown in FIG. 4, the connection portion 240 of the conductive layer 250 is, for example, a multi-channel structure, and the connection portion 240 includes a first portion 226a connected to the drain 210b, a second portion 226b connected to the coupling portion 220, and The third part 224 located between the first part 226a and the second part 226b, the third part 224 is designed as a multi-channel structure. Moreover, a light-shielding layer 222 is further configured under the third portion 224 of the connection portion 240, and the light-shielding layer 222 belongs to the first metal layer like the gate 206, the scanning line 202 and the common line 218, and the light-shielding layer 222 It is used to shield the subsequent light scattering phenomenon caused by the contact window formed thereon.

Furthermore, the protective layer 211 covers the data line 204 , the thin film transistor 230 and the conductive layer 250 . In addition, the flat layer 213 is disposed on the protective layer 211 .

The contact window 228 is disposed in the flat layer 213 and the protection layer 211 above the connection portion 240 , and the contact window 228 is electrically connected to the connection portion 240 of the conductive layer 250 . In a preferred embodiment, the contact window 228 is disposed in the planar layer 213 and the protection layer 211 above the channel 224 b of the connecting portion 240 , and is electrically connected to the channel 224 b of the connecting portion 240 .

The pixel electrode 212 is disposed on the surface of the planar layer 213, wherein the pixel electrode 212 is electrically connected to the connection portion 240 of the conductive layer 250 through the contact window 228. More specifically, the pixel electrode 212 is connected to the connection portion 240 through the contact window 228. The channel 224b is electrically connected. Through the electrical contact between the channel 224 b and the pixel electrode 212 , the pixel electrode 212 and the entire conductive layer 250 are electrically connected to each other. In addition, since the drain electrode 210b is connected to the conductive layer 250, the pixel electrode 212, the conductive layer 250, and the drain electrode 210b are electrically connected to each other.

Therefore, in the pixel structure of the present invention, the pixel electrode, the drain electrode and the upper electrode of the pixel storage capacitor are electrically connected through the same contact window, so the pixel structure of the present invention is a kind of Some pixel structure design.

In addition, since the contact window of the pixel structure of the present invention is not arranged above the pixel storage capacitor, even if the etching step of the protection layer and the gate insulating layer will etch through the gate insulating layer, the pixel storage capacitor will not be damaged. Leakage occurs between the upper and lower electrodes.

Although the present utility model has been disclosed above with preferred embodiments, it is not intended to limit the present utility model. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present utility model. , so the scope of protection of the present utility model should be defined by the claims.

Claims (7)

1. dot structure comprises:

The one scan line is configured on the substrate;

One bridging line is configured on this substrate, and it is as the lower electrode of a pixel storage capacitor device;

One gate insulator is configured on this substrate, covers this sweep trace and this bridging line;

One data line is configured on this gate insulator;

One on-off element is configured on this substrate, and wherein this on-off element and this sweep trace and this data line electrically connect;

One conductive layer, be configured on this gate insulator, wherein this conductive layer has a coupling part and a junction, and this coupling part is in the top of this bridging line, it is as the upper electrode of this pixel storage capacitor device, and this connecting portion couples together this coupling part and this on-off element;

One protective seam covers this data line, this on-off element and this conductive layer;

One contact hole is configured in this protective seam of this connecting portion top; And

One pixel electrode is configured on this protective seam, and wherein this pixel electrode electrically connects with this coupling part of this on-off element and this conductive layer by this contact hole.

2. dot structure as claimed in claim 1 is characterized in that, this connecting portion of this conductive layer is a multi-channel structure, and it comprises:

One first, it is connected with this coupling part;

One second portion, it is connected with this on-off element; And

One third part, between this first and this second portion, and this third part has again a plurality of passages.

3. dot structure as claimed in claim 2 is characterized in that, this contact hole is configured in this protective seam of those passage tops of one in this third part, and electrically connects with this passage.

4. dot structure as claimed in claim 1 is characterized in that, under this connecting portion that disposes this contact hole place, also disposes a light shield layer.

5. dot structure as claimed in claim 1 is characterized in that, between this protective seam and this pixel electrode, also disposes a flatness layer.

6. dot structure as claimed in claim 1 is characterized in that this on-off element is a thin film transistor (TFT), and it comprises:

One grid, this grid and this sweep trace electrically connect;

One channel layer, this channel layer are configured on this gate insulator of this grid top; And

Source, this source/drain is configured on this channel layer, and this source electrode and the electric connection of this data line, and this drain electrode is connected with this connecting portion of this conductive layer.

7. dot structure as claimed in claim 1 is characterized in that, this sweep trace and this bridging line configured in parallel.

Images