CN2684375Y - Chip packaging structure - Google Patents

Abstract

The utility model discloses a chip packaging structure, which is mainly composed of a carrier, a chip, at least one passive element, at least one first lead wire and sealing glue. It is characterized in that the passive component is straddled between a power contact and a ground contact of the carrier, and the two ends of the first lead can be directly connected to a soldering pad of the chip and a soldering end of the passive component, therefore The length of the first lead can be effectively shortened, and the signal transmission path through the first lead is shortened, which will improve the electrical performance of the chip and increase the wiring space adjacent to the lead. In addition, the structure may further include at least one second lead, and one end of the second lead may cross over the passive component and be welded to a contact point on the outermost periphery of the carrier.

Description

Chip package structure

technical field

The utility model relates to a chip packaging structure, in particular to a chip packaging structure with a wire bonding type of passive components.

Background technique

Due to the development of semiconductor technology and the increase in market demand, the semiconductor industry has continuously developed more sophisticated and faster electronic components. In terms of current semiconductor packaging technology, such as chip construction technology, chip carrier (chip carrier) The production of semiconductors and the assembly of passive components (passive components) all occupy an indispensable position in the semiconductor industry.

As far as the technology of chip assembly is concerned, each bare chip (die) formed by wafer dicing, for example, is configured by wire bonding or flip chip bonding. On the surface of a carrier (carrier), where the carrier is, for example, a lead frame (leadframe) or a substrate (substrate), and the chip has a plurality of bonding pads, and the bonding pads of the chip can be electrically connected through the transmission lines and contacts of the carrier. Connect to external electronic devices. In addition, for a chip using wire bonding, after the bonding pad is electrically connected to the contact point of the substrate, an encapsulant material is formed to cover the chip and the lead to protect the chip and the lead, thus completing a chip package structure.

Please refer to FIG. 1A and FIG. 1B , wherein FIG. 1A shows a partial cross-sectional view of a conventional wire-bonded chip package structure, and FIG. 1B shows a top view schematic diagram of a conventional wire-bonded chip package structure. The chip packaging structure 100 is mainly composed of a carrier 110 , a chip 120 , a plurality of leads 134 , 136 , 138 and an encapsulant (not shown). The surface of the carrier 110 has a chip bonding area 112, and the back surface 122 of the chip 120 is attached on the chip bonding area 112, and the active surface 124 of the chip 120 has a plurality of bonding pads 126, which correspond to the carrier 110 respectively. The contact points on the surface are, for example, the ground contact 114 , the power contact 116 , and the signal contact 118 in order from inside to outside. In addition, two ends of each lead 134 , 136 , 138 are respectively connected to one of the bonding pads 126 of the chip 120 and its corresponding ground contact 114 , power contact 116 and signal contact 118 .

It is worth noting that, in order to effectively improve the electrical characteristics of the chip package structure 100, the surface mount technology (Surface Mount Technology, SMT) is usually used to attach the small passive component 130 to the surface of the carrier 110, so as to reduce the signal switching time. When the noise generated by the crosstalk (crosstalk), and maintain the quality of signal transmission. Wherein, the passive component 130 is, for example, an inductor or a capacitor, and the passive component 130 is straddled between the power contact 116 and the ground contact 114 of the carrier 110, and the two welding of the passive component 130 The terminals 132a, 132b are respectively connected to the power contact 116 and the ground contact 114 .

However, when the wire bonding process is performed between the chip 120 and the carrier 110, the wires 136 corresponding to the bonding pads 126 of the chip 120 and the power contacts 116 of the carrier 110 must first pass over the passive component 130, and then It is then soldered to the surface of the power contact 116 . Since the lead wire 136 must first elongate the arc before it can cross the top of the passive component 130, the length of the lead wire 136 itself is relatively increased, and the transmission path of the signal through the lead wire 136 is increased, which will reduce the electrical performance of the chip 120, and Affects the routing space of adjacent leads.

Utility model content

Therefore, the purpose of this utility model is to provide a chip packaging structure, which is used to shorten the length of the leads and increase the wiring space of the leads.

Another object of the present invention is to provide a wire bonding package structure, which is used to shorten the length of the leads and increase the wiring space of the leads.

In order to achieve the above purpose of the utility model, the utility model provides a chip packaging structure, at least including a carrier, the carrier has a surface, a power contact and a ground contact, and the surface has a chip bonding area, and the power contact and the ground contact are arranged on the surface, and the power contact and the ground contact are located outside the chip bonding area. In addition, the chip is arranged on the surface of the carrier, and the chip has an active surface and a corresponding back surface, and the back surface of the chip is attached to the chip welding area, and the chip also has a plurality of welding pads, which are arranged on the active surface. In addition, at least one passive component is straddled between the power contact and the ground contact of the carrier, and the passive component has at least two welding terminals, which are respectively electrically connected to the power contact and the ground contact. Furthermore, two ends of the at least one first lead are respectively connected to one of the bonding pads and one of the bonding ends of the chip. Furthermore, the sealing glue covers the chip, the passive components and the first lead.

In the above-mentioned chip packaging structure of the utility model, one end of the lead wire can be directly connected to the welding end of the passive component, so the length of the lead wire can be effectively shortened, and the transmission path of the signal through the lead wire is shortened, which will make the electrical performance of the chip improve, and increase the routing space adjacent to the leads.

In order to achieve the above purpose of the utility model, the utility model also provides a wire bonding packaging structure, which is suitable for electrically connecting a chip to a carrier, and is characterized in that the surface of the carrier has a chip bonding area, and the chip It has an active surface and a corresponding back surface, and the chip is attached to the chip bonding area through the back surface. The wire bonding package structure at least includes: a power contact, arranged on the surface of the carrier; a ground contact, arranged On the surface of the carrier; a signal contact, arranged on the surface of the carrier, wherein the power contact and the ground contact are located on the same side outside the chip bonding area, and the signal contact is located on the outside of the power contact and the ground contact farther away from the chip bonding area ; a passive component, straddling between the power contact and the ground contact of the carrier, and the passive component has at least two welding terminals, which are respectively electrically connected to the power contact and the ground contact; a plurality of welding pads, configured on the chip Active surface; a first lead, electrically connected to one of the solder pads and one of the solder ends; and a second lead, electrically connected to the other of the solder pads and the signal contact, and the second lead spans above the passive components. In the above-mentioned wire bonding package structure of the present invention, one end of the lead wire can be directly connected to the welding end of the passive component, so the length of the lead wire can be effectively shortened, and the transmission path of the signal through the lead wire is shortened, which will make the chip's The electrical performance is improved and the routing space adjacent to the leads is increased.

In order to make the above and other purposes, features, and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below with accompanying drawings.

Description of drawings

FIG. 1A shows a partial cross-sectional view of an existing chip package structure of a wire bonding type;

FIG. 1B shows a schematic top view of an existing chip package structure of a wire bonding type;

FIG. 2A shows a partial cross-sectional view of a chip package structure of a wire bonding type according to a preferred embodiment of the present invention;

FIG. 2B is a schematic top view of a chip packaging structure of a wire bonding type according to a preferred embodiment of the present invention.

Explanation of reference signs

100 chip package structure 110 carrier

112 Chip bonding area 114 Ground contact

116 Power Contacts 118 Signal Contacts

120 chip 122 back

124 Active Surface 126 Solder Pad

130 Passive components 132a Solder terminal

132b Solder terminal 134 Lead wire

136 Lead wire 138 Lead wire

200 chip package structure 210 carrier

212 Chip soldering area 214 Ground contact

216 Power Contacts 218 Signal Contacts

220 chip 222 back

224 Active Surface 226a Solder Pad

226b Solder Pad 226c Solder Pad

230 Passive components 232a Solder terminal

232b Solder Terminal 234 First Lead

236 First Lead 238 Second Lead

240 Solder mask layer 242 Metal layer

Detailed ways

Please refer to FIGS. 2A and 2B, wherein FIG. 2A shows a partial cross-sectional view of a wire bonding chip package structure of a preferred embodiment of the present invention, and FIG. 2B shows a lead of a preferred embodiment of the present invention A schematic top view of a bonded chip package structure. The chip packaging structure 200 is mainly composed of a carrier 210, a chip 220, a passive component 230, a plurality of first leads 234, 236, at least one second lead 238 and an encapsulant (not shown), wherein the carrier 210 is, for example, a substrate, which has a chip bonding area 212 on its surface, and the back surface 222 of the chip 220 is attached on the chip bonding area 212, and the active surface 224 of the chip 220 has a plurality of bonding pads 226, which respectively correspond to the carrier The contacts on the device 210 are, for example, ground contacts 214 , power contacts 216 , and signal contacts 218 . In this embodiment, as shown in FIG. 2B , the power contact 216 and the ground contact 214 are, for example, located on the same side outside the chip bonding area 212, and the two are, for example, formed by a power ring surrounding the periphery of the chip bonding area 212. (not shown) and a local line segment of a ground ring (not shown), and a part of the surface of the power ring and a part of the surface of the ground ring are exposed in the opening of a patterned solder mask layer 240, as a connecting first Leads 234 , 236 or power contacts 216 or ground contacts 214 for passive components 230 .

2A and 2B, the signal contact 218 is located on the same side of the power contact 216 and the ground contact 214, and the signal contact 218 is relatively far away from the chip bonding area 212 and located outside the power contact 216 and the ground contact 214. In addition, the signal contacts 218 and the die pads 212 can also be exposed in the openings of the patterned solder mask layer 240 .

In addition, please refer to FIG. 2A , the passive component 230 is straddled between the power contact 216 and the ground contact 214, and the passive component 230 has at least two soldering ends 232a, 232b, which are welded on the surface mount technology (SMT) respectively. The surfaces of the power contact 216 and the ground contact 214 are used to effectively suppress the mutual inductive coupling generated between the first leads 234 , 236 and the second lead 238 . Wherein, the passive element 230 is, for example, a small inductance element or a capacitance element, and the surface of the soldering end 232a, 232b of the passive element 230 also has a metal layer 242, and the metal layer 242 is formed by electroplating, for example, and the metal layer 242 The material can be nickel, gold or other alloys, which are used to increase the solderability between the first leads 234, 236 and the soldering ends 232a, 232b during the subsequent wire bonding process.

It is worth noting that, in order to shorten the length of the leads 234, 236, in this embodiment, one end of at least one first lead 236 is directly welded to the welding end 232a of the passive component 230, wherein the two ends of the first lead 236 can be connected correspondingly To a soldering pad 226a of the chip 220 and a soldering end 232a of the passive component 220 away from the chip 220, and the two ends of the other first lead 234 can be correspondingly connected to another soldering pad 226b of the chip 220 and the soldering end 232a of the passive component 230 The soldering end 232b of the adjacent chip 220 or the ground contact 214 (not shown). Since the first lead 236 of the outer layer does not need to elongate the arc to cross over the passive element 230, but is directly welded on the welding end 232a of the passive element 230, the length of the first lead 236 of the outer layer will be It can be effectively shortened, and the shortened signal transmission path through the first lead 236 will improve the electrical performance of the chip 220 and increase the layout space of adjacent leads. In addition, the two ends of the second lead 238 can correspond to another bonding pad 226c connecting the chip 220 and the outermost signal contact 218 of the carrier 210, and the second lead 238 can also cross over the passive component 230 without Any soldering end 232a, 232b of the passive component 230 will be contacted.

As can be seen from the above description, the chip packaging structure of the present invention straddles at least one passive component between the power contact and the ground contact of the carrier, and the two welding ends of the passive component are electrically connected to the power contact and the ground contact respectively, Then correspondingly connect a first lead to a soldering pad of the chip and a soldering end of the passive component, and then connect a second lead to another soldering pad and signal contact of the chip correspondingly, and then form an encapsulation glue The chip, the passive element, and the first and second leads are covered to protect the chip and the first and second leads, so that a chip package structure can be completed.

In summary, the chip packaging structure of the present invention has the following advantages:

(1) One end of the lead wire can be directly connected to a welding end of the passive component, so the length of the lead wire will be effectively shortened, and the signal transmission path through the lead wire will be shortened, which will improve the electrical performance of the chip and increase the number of adjacent leads. wiring space.

(2) One end of the lead wire can cross over the passive component and be welded to the outermost contact of the carrier without touching any soldering end of the passive component.

Although the utility model has been disclosed above in conjunction with a preferred embodiment, it is not intended to limit the utility model, and those skilled in the art may make some modifications and changes without departing from the spirit and scope of the utility model. Modification, so the scope of protection of the present utility model is defined by the claims.

Claims (9)

1. A chip packaging structure, comprising at least: A carrier has a surface, a power contact and a ground contact, and the surface has a chip bonding area, and the power contact and the ground contact are arranged on the surface, and the power contact and the ground contact are located on the chip the same side as the weld zone; A chip is configured on the surface of the carrier, and the chip has an active surface and a corresponding back surface, and the chip is attached to the chip bonding area with the back surface, and the chip also has a plurality of bonding pads, it is disposed on the active surface; At least one passive component straddles between the power contact and the ground contact of the carrier, and the passive component has at least two soldering ends electrically connected to the power contact and the ground contact respectively; at least one first lead electrically connected to one of the bonding pads and one of the bonding terminals of the chip; and Sealing glue, covering the chip, the passive element and the first lead. 2 . The chip package structure according to claim 1 , wherein the carrier further has a signal contact, and the signal contact is located on the outer side of the power contact and the ground contact farther away from the chip bonding area. 3 . 3. The chip packaging structure according to claim 2, further comprising at least one second lead, the two ends of which are respectively connected to the other one of the solder pads of the chip and the signal contact, and the second lead straddles the above the passive components. 4. The chip packaging structure according to claim 3, wherein the encapsulant also covers the second lead. 5. The chip package structure according to claim 1, wherein the surfaces of the soldering ends have a metal layer, and the material of the metal layer is selected from a group consisting of nickel, gold and these alloys. Material. 6. The chip package structure as claimed in claim 1, wherein the passive element is one of an inductance element and a capacitance element. 7. A wire bonding package structure suitable for electrically connecting a chip to a carrier, characterized in that the surface of the carrier has a chip bonding area, and the chip has an active surface and a corresponding back surface, And the chip is attached to the chip bonding area with the back surface, and the wire bonding package structure at least includes: a power contact configured on the surface of the carrier; a ground contact configured on the surface of the carrier; A signal contact, arranged on the surface of the carrier, wherein the power contact and the ground contact are located on the same side outside the chip bonding area, and the signal contact is located farther away from the chip bonding area than the power contact and the ground contact outside of a passive component straddled between the power contact and the ground contact of the carrier, and the passive component has at least two soldering ends electrically connected to the power contact and the ground contact respectively; a plurality of welding pads configured on the active surface of the chip; a first lead, electrically connected to one of the solder pads and one of the solder terminals; and A second lead is electrically connected to the other one of the welding pads and the signal contact, and the second lead crosses over the passive component. 8. The wire bonding package structure according to claim 7, wherein the surface of the soldering ends has a metal layer, and the material of the metal layer is selected from the group consisting of nickel, gold and these alloys a material. 9. The wire bonding package structure as claimed in claim 7, wherein the passive element is one of an inductance element and a capacitance element.

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