CN2591779Y - Leadless Semiconductor Components - Google Patents
Leadless Semiconductor Components Download PDFInfo
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- CN2591779Y CN2591779Y CN02292733.6U CN02292733U CN2591779Y CN 2591779 Y CN2591779 Y CN 2591779Y CN 02292733 U CN02292733 U CN 02292733U CN 2591779 Y CN2591779 Y CN 2591779Y
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Abstract
Description
【技术领域】【Technical field】
本实用新型是关于一种无引脚半导体组件。The utility model relates to a leadless semiconductor assembly.
【背景技术】【Background technique】
现在习见的无引脚半导体组件封装结构,如图3所示,其具有一包括多数引脚(41)的金属导线架(40),各引脚(41)内侧端朝上形成高起状,再将芯片(50)以I/O接点朝下的型态藉双面胶带(52)粘设于导线架(40)中央的引脚(41)内侧端高起部上,另以金线(51)连接于芯片(50)各I/O接点与导线架(40)对应的引脚(41)内侧端底面处,再于外侧配合模具封固一胶体(60)后成形,而构成一引脚(41)外侧端外露的无引脚半导体组件。Now common leadless semiconductor component package structure, as shown in Figure 3, it has a metal lead frame (40) that includes a plurality of pins (41), and each pin (41) inner end forms a raised shape upwards, Then the chip (50) is glued on the raised part of the inner side of the pin (41) in the center of the lead frame (40) by double-sided adhesive tape (52) with the I/O contact facing down, and gold wire ( 51) Connect each I/O contact point of the chip (50) to the inner end bottom surface of the pin (41) corresponding to the lead frame (40), and then form a colloid (60) on the outer side with a mold sealing to form a lead frame (40). A leadless semiconductor component exposed at the outer end of the pin (41).
又,前揭无引脚半导体组件因其芯片系完全被封固于胶体的中,芯片工作时所产生的高温有不易散发的问题,故有人另作出如图4所示的双导线架结构,其主要具有一包括多数引脚(71)的金属第一导线架(70),其引脚(71)内侧端朝上形成高起状,复将芯片(80)以I/O接点朝下的型态藉双面胶带(82)粘设于第一导线架(70)中央引脚(71)内侧端上,另以金线(81)连接于芯片(80)各I/O接点与第一导线架(70)对应的引脚(71)内侧端底面处,于芯片(80)上以银胶或双面胶带粘着一具芯片焊垫(101)的第二导线架(100),再于外侧配合模具封固一胶体(90)后成形,而构成一芯片焊垫(101)及引脚(71)外侧端外露的无引脚半导体组件。In addition, because the chip of the non-lead semiconductor component disclosed above is completely sealed in the colloid, the high temperature generated during the operation of the chip is difficult to dissipate. Therefore, someone made another double lead frame structure as shown in Figure 4. It mainly has a metal first lead frame (70) including a plurality of pins (71), the inner side of the pins (71) faces upwards to form a raised shape, and the chip (80) is placed downwards with the I/O contacts The pattern is glued on the inner side of the central pin (71) of the first lead frame (70) by double-sided adhesive tape (82), and is connected to each I/O contact of the chip (80) and the first lead frame (70) with a gold wire (81). At the bottom surface of the inner side of the pin (71) corresponding to the lead frame (70), a second lead frame (100) of a chip welding pad (101) is adhered on the chip (80) with silver glue or double-sided adhesive tape, and then placed on the chip (80) A colloid (90) is molded on the outer side to form a colloid (90) to form a chip pad (101) and a leadless semiconductor component with the outer end of the pin (71) exposed.
前揭二习用无引脚半导体组件虽以其引脚外露端呈平直状,藉以降低组件成品的整体厚度,并能直接平贴焊设于电路板上,而图4所示的半导体组件更藉由芯片上外露于胶体外的金属焊垫设计,使组件中的芯片工作时产生的高温可以直接经由金属焊垫散热。Although the conventional pinless semiconductor components disclosed above are straight, the exposed ends of the pins are straight, so as to reduce the overall thickness of the finished components, and can be directly mounted on the circuit board by flat soldering, and the semiconductor components shown in Figure 4 are even more With the design of the metal pad on the chip exposed outside the colloid, the high temperature generated by the chip in the module can be dissipated directly through the metal pad.
但,前揭习用二无引脚半导体组件的结构虽较既有引脚弯折凸伸的半导体组件具有轻薄短小的特点,然而,其结构中尚存在以下的缺点:However, although the structure of the previously disclosed leadless semiconductor component has the characteristics of being thinner and shorter than the existing semiconductor component with bent and protruding pins, it still has the following disadvantages in its structure:
1、导线架的模具费用高:该习用二无引脚半导体组件为使提供连于芯片与引脚间的金属线的容置空间,需结合模具以冲制方式令导线架引脚内侧端形成一高起部,而需增加模具费用的支出及加工成本。1. The mold cost of the lead frame is high: In order to provide accommodating space for the metal wires connected between the chip and the pins of the conventional two-lead semiconductor component, it is necessary to combine the mold to form the inner end of the lead frame pins by punching. A high-rise part requires an increase in mold expenses and processing costs.
2、组件成品偏厚:同上所述,该习用二无引脚半导体组件系结合模具以冲制方式令导线架引脚内侧端形成一高起部,来提供连接芯片与引脚间金属线的容置空间,故使该二半导体组件整体的厚度较高。2. The finished component is thicker: As mentioned above, the conventional two-lead semiconductor component is combined with a mold to form a raised part on the inner side of the lead frame pin by punching, so as to provide a connection between the chip and the metal wire between the pins. The accommodating space makes the overall thickness of the two semiconductor components relatively high.
【实用新型内容】【Content of utility model】
有鉴于此,为改善前揭习用无引脚半导体组件的封装结构缺点,本实用新型的目的即在于提供一种可节省模具费用、制造简便且可降低产品厚度,而具有轻薄短小等优点的无引脚半导体组件。In view of this, in order to improve the disadvantages of the packaging structure of the previously disclosed leadless semiconductor assembly, the purpose of the utility model is to provide a non-leading semiconductor assembly that can save mold costs, is easy to manufacture, and can reduce product thickness. pin semiconductor components.
为达成前揭目的,本实用新型所提出的一种无引脚半导体组件,其特征在于:其包括:In order to achieve the purpose disclosed above, a leadless semiconductor component proposed by the utility model is characterized in that it includes:
一金属导线架,其具有多数平直状的引脚,其相邻引脚间以及相对引脚间具有隔离间隙,且各引脚内侧端底面形成凹部;A metal lead frame, which has a plurality of straight pins, there are isolation gaps between adjacent pins and opposite pins, and a concave portion is formed on the bottom surface of the inner end of each pin;
一芯片,是固设于导线架中央的引脚内侧端上且使I/O接点朝下,该芯片各I/O接点与导线架对应的引脚间以金属线构成电性连接;以及A chip is fixed on the inner side of the pins in the center of the lead frame with the I/O contacts facing down, and each I/O contact of the chip is electrically connected to the corresponding pins of the lead frame with metal wires; and
一胶体,是成型固设于导线架上覆设于芯片外侧,并充填于该导线架中引脚间的隔离间隙及凹部中,将连接于芯片与导线架引脚间的金属线密封于内,导线架各引脚外侧端底面显露于外。A colloid, which is formed and fixed on the lead frame to cover the outside of the chip, and fills the isolation gap and recess between the pins in the lead frame, and seals the metal wire connected between the chip and the lead frame pins inside , the bottom surface of the outer end of each pin of the lead frame is exposed outside.
本实用新型的无引脚半导体组件还可以具有下述附加的技术特征:The leadless semiconductor assembly of the present utility model can also have the following additional technical features:
该导线架的引脚可分布于两边呈对应状。The pins of the lead frame can be distributed on both sides in a corresponding shape.
该导线架的引脚也可分布于四边呈两相对应状。The pins of the lead frame can also be distributed on four sides to form two corresponding shapes.
设于导线架引脚底面的凹部的高度不超过导线架厚度的二分之一。The height of the concave part arranged on the bottom surface of the pin of the lead frame is no more than half of the thickness of the lead frame.
该胶体可将芯片完全包覆于内。The colloid can completely cover the chip inside.
该胶体也可包覆于芯片周缘及底面,且让芯片上表面显露于外。The colloid can also be coated on the periphery and the bottom surface of the chip, and the upper surface of the chip is exposed outside.
该胶体外缘与导线架引脚外端缘平齐。The outer edge of the glue is flush with the outer edge of the lead frame pin.
该导线架引脚外端缘凸伸于胶体外缘。The outer edge of the pin of the lead frame protrudes from the outer edge of the glue.
该导线架的凹部处可镀设一层银或镍-钯-金的合金。A layer of silver or nickel-palladium-gold alloy can be plated on the recess of the lead frame.
经由前述说明后,且与习用二无引脚半导体组件相比较,当可得知本实用新型的特点至少包括:After the foregoing description, and compared with the conventional two leadless semiconductor components, it can be known that the features of the present invention include at least:
1、可节省制造导线架的模具费用:本实用新型的导线架可利用蚀刻方式直接制造成型,无需于蚀刻或冲制成雏型导线架后,再藉模具于引脚内侧端冲压出高起部的繁琐程序,而能节省制造导线架的模具费用。1. It can save the cost of the mold for manufacturing the lead frame: the lead frame of the utility model can be directly manufactured and formed by etching, and there is no need to use the mold to punch out the high rise on the inner side of the pin after etching or punching the prototype lead frame The cumbersome procedures of the department can save the cost of molds for manufacturing lead frames.
2、可降低产品厚度,达到轻薄短小的目的:本实用新型半导体组件系利用导线架平直的引脚内侧端半蚀刻形成的凹部,直接提供连接芯片与引脚间金属线的容置空间,而无需利用导线架引脚内侧端弯折成高起状所提供容置空间,故可降低组件的厚度,而呈现出最轻薄短小的型体。2. The thickness of the product can be reduced to achieve the purpose of lightness, thinness and shortness: the semiconductor component of this utility model uses the concave part formed by half-etching the inner side of the straight pin of the lead frame to directly provide accommodating space for connecting the metal wire between the chip and the pin. There is no need to use the accommodating space provided by bending the inner end of the lead frame pin into a raised shape, so the thickness of the component can be reduced, and the thinnest and shortest shape is presented.
3、具高散热性:本实用新型半导体组件因其平直的金属引脚占组件底面大部份的外露面积,且芯片直接固设于引脚上,又组件的芯片背面可为外露式的型态,故芯片工作时所产生的热量可直接经由引脚或芯片背面传导至外界,因而具备极佳的散热效果。3. High heat dissipation: the semiconductor component of this utility model occupies most of the exposed area of the bottom surface of the component because of its straight metal pins, and the chip is directly fixed on the pin, and the back of the chip of the component can be exposed Therefore, the heat generated when the chip is working can be directly conducted to the outside through the pins or the back of the chip, so it has an excellent heat dissipation effect.
4、可减少信号传递延迟现象:本实用新型半导体组件的电性连接系由导线架平直的引脚直接导出,其信号传递路径相较于习用半导体组件中曲折状引脚较短,故可减少信号传递延迟现象。4. Can reduce signal transmission delay phenomenon: the electrical connection of the semiconductor component of the utility model is directly derived from the straight pins of the lead frame, and its signal transmission path is shorter than that of the zigzag pins in the conventional semiconductor component, so it can Reduce signal transmission delay phenomenon.
为能进一步了解本实用新型的结构特征及其它目的,兹附以图式详细说明如后:In order to further understand the structural features and other purposes of the present utility model, the drawings are attached in detail as follows:
【附图说明】【Description of drawings】
图1是本实用新型一实施例的平面结构示意图。Fig. 1 is a schematic plan view of an embodiment of the utility model.
图2是本实用新型另一实施例的平面结构示意图。Fig. 2 is a schematic plan view of another embodiment of the utility model.
图3为习用第一种无引脚半导体组件的平面示意图。FIG. 3 is a schematic plan view of the first conventional leadless semiconductor component.
图4为习用第二种无引脚半导体组件的平面示意图。FIG. 4 is a schematic plan view of a second conventional leadless semiconductor component.
【具体实施方式】【Detailed ways】
有关本实用新型无引脚半导体组件的具体实施例,如图1、2所示,其包括:Concrete embodiments of the leadless semiconductor assembly of the present invention, as shown in Figures 1 and 2, include:
一金属导线架(10),其具有多数平直状的引脚(11),该导线架(10)的引脚(11)可分布于两相对侧边处或分布于四周边处等型态,其相邻引脚(11)间以及相对引脚(11)间具有隔离间隙(12),又各引脚(11)内侧端底面利用半蚀刻方式形成凹部(13),该凹部(13)高度以不超过导线架(10)厚度二分的一为最佳;A metal lead frame (10), which has a plurality of straight pins (11), the pins (11) of the lead frame (10) can be distributed on two opposite sides or around the periphery, etc. There is an isolation gap (12) between adjacent pins (11) and between opposite pins (11), and a recess (13) is formed on the bottom surface of the inner side of each pin (11) by half etching, and the recess (13) The height is best no more than one half of the thickness of the lead frame (10);
一芯片(20),系以I/O接点朝下的型态藉双面胶带(22)固设于导线架(10)中央处相对引脚(11)内侧端上,芯片(20)I/O接点正对导线架(10)相对引脚(11)间的隔离间隙(12),另以金属线(21)连接于芯片(20)各I/O接点与导线架(10)对应的引脚(11)间构成电性连接;以及A chip (20) is fixed on the inner side of the pin (11) at the center of the lead frame (10) by means of a double-sided adhesive tape (22) with the I/O contacts facing down, and the chip (20) I/O The O contact is facing the isolation gap (12) between the opposite pins (11) of the lead frame (10), and is connected to each I/O contact of the chip (20) and the corresponding lead of the lead frame (10) with a metal wire (21). An electrical connection is formed between the pins (11); and
一胶体(30),系配合模具成型固设于导线架(10)上并包覆于芯片(20)外侧,且充填于导线架(10)中引脚(11)间的隔离间隙(12)及凹部(13)中,以便将连接于芯片(20)与导线架(10)引脚间的金属线(21)密封于内,且让导线架(10)各引脚(11)外侧端底面显露于外,而构成一无引脚半导体组件封装结构。A colloid (30), which is molded and fixed on the lead frame (10) and coated on the outside of the chip (20), and fills the isolation gap (12) between the pins (11) in the lead frame (10) and in the recess (13), so that the metal wire (21) connected between the chip (20) and the pin of the lead frame (10) is sealed inside, and the bottom surface of the outer end of each pin (11) of the lead frame (10) exposed outside to form a package structure of a leadless semiconductor component.
前述胶体(30)可如图1所示让芯片(20)上表面显露于外,以利于散热,或如图2所示,可将芯片(20)完全包覆于内;又胶体(30)外缘可与导线架(10)引脚(11)外端缘平齐,或导线架(10)引脚(11)外端部略凸伸于胶体(30)外缘;又导线架(10)的凹部(13)处镀设一层银或镍-钯-金的合金,供金属线(21)连接于引脚(11)上之用。Aforesaid colloid (30) can allow chip (20) upper surface to be exposed outside as shown in Figure 1, to facilitate heat dissipation, or as shown in Figure 2, chip (20) can be fully coated in the inside; again colloid (30) The outer edge can be flush with the outer edge of the lead frame (10) pin (11), or the outer end of the lead frame (10) pin (11) protrudes slightly on the outer edge of the colloid (30); ) is plated with a layer of silver or nickel-palladium-gold alloy at the recess (13) for the metal wire (21) to be connected to the pin (11).
该半导体组件可结合其它电子组件装配于电路板上,且藉其平直状的引脚可直接平贴焊设于电路板上的线路上构成电性连接,以提供其特定的工作性能,并能呈现其轻薄短小的型态;另该半导体组件可藉导线架引脚端部外露,而能直接经由引脚外露端作功能性或开路/短路的检测。The semiconductor component can be assembled on a circuit board in combination with other electronic components, and its straight pins can be directly soldered on the circuit board to form an electrical connection, so as to provide its specific working performance, and It can present its light, thin and small shape; in addition, the semiconductor component can be exposed through the exposed end of the lead frame, so that the function or open circuit/short circuit can be detected directly through the exposed end of the pin.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02292733.6U CN2591779Y (en) | 2002-12-20 | 2002-12-20 | Leadless Semiconductor Components |
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| CN02292733.6U CN2591779Y (en) | 2002-12-20 | 2002-12-20 | Leadless Semiconductor Components |
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| CN2591779Y true CN2591779Y (en) | 2003-12-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316611C (en) * | 2004-03-19 | 2007-05-16 | 矽品精密工业股份有限公司 | Wafer-level semiconductor package with build-up structure and manufacturing method thereof |
| TWI475658B (en) * | 2013-01-18 | 2015-03-01 | I Chiun Precision Ind Co Ltd | LED leadframe and manufacturing method thereof |
-
2002
- 2002-12-20 CN CN02292733.6U patent/CN2591779Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316611C (en) * | 2004-03-19 | 2007-05-16 | 矽品精密工业股份有限公司 | Wafer-level semiconductor package with build-up structure and manufacturing method thereof |
| TWI475658B (en) * | 2013-01-18 | 2015-03-01 | I Chiun Precision Ind Co Ltd | LED leadframe and manufacturing method thereof |
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| C14 | Grant of patent or utility model | ||
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| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Guangzhou Hailin Electronic Technology Co., Ltd. Assignor: UPI Semiconductor Corp Contract fulfillment period: 2009.8.10 to 2012.8.9 Contract record no.: 2009990001055 Denomination of utility model: Non-pin semiconductor assembly Granted publication date: 20031210 License type: Exclusive license Record date: 20090924 |
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| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.8.10 TO 2012.8.9; CHANGE OF CONTRACT Name of requester: GUANGZHOU CITY HAILIN ELECTRONIC TECHNOLOGY DEVELO Effective date: 20090924 |
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| C17 | Cessation of patent right | ||
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Expiration termination date: 20121220 Granted publication date: 20031210 |