CN223829815U - Semiconductor test structure - Google Patents

Abstract

This utility model provides a semiconductor testing structure. The semiconductor testing structure includes: a substrate; an epitaxial layer disposed on the substrate; a field oxide layer located on the epitaxial layer, the field oxide layer having open regions, and multiple trenches spaced apart on the open regions, with polysilicon disposed within the trenches; a gate oxide layer located between the trenches and the epitaxial layer; a dielectric layer covering the outer surface of the epitaxial layer away from the substrate; a metal layer located on the dielectric layer, the metal layer including a first pad and a second pad electrically connected to the two ends of the trenches respectively; and multiple contact vias penetrating the dielectric layer, the metal layer being connected to the multiple trenches through the multiple contact vias; the semiconductor testing structure tests the offset of the contact vias of the semiconductor by applying voltage at the first pad and the second pad.

Description

Semiconductor test structure

Technical Field

This utility model relates to the field of semiconductor technology, and in particular to a semiconductor testing structure.

Background Technology

In the manufacturing process of semiconductor devices, such as power semiconductor MOSFETs, the creation of contact holes connecting the metal and silicon requires photolithographic alignment. Alignment error is a key factor affecting device performance and yield. Traditional monitoring methods typically rely on complex photolithographic data analysis, which is not only cumbersome but also difficult to manage and struggles to detect abnormal process fluctuations in a timely manner. Although photolithography processes have automatic alignment error compensation systems, these systems often only reduce errors to a certain extent and cannot fully meet monitoring requirements. Therefore, developing a test structure capable of efficiently monitoring alignment errors is particularly important.

Utility Model Content

Therefore, in order to overcome at least some of the defects and deficiencies in the prior art, this utility model provides a semiconductor testing structure.

Specifically, in one aspect, the semiconductor testing structure provided by this utility model embodiment includes: a substrate; an epitaxial layer disposed on the substrate; a field oxide layer located on the epitaxial layer, wherein an open region is provided on the field oxide layer, and a plurality of trenches are spaced apart on the open region, wherein polysilicon is disposed in the trenches; a gate oxide layer located between the trenches and the epitaxial layer; a dielectric layer covering the outer surface of the epitaxial layer away from the substrate; a metal layer located on the dielectric layer, wherein the metal layer includes a first pad and a second pad electrically connected to the two ends of the trenches respectively; and a plurality of contact vias penetrating the dielectric layer, wherein the metal layer is connected to the plurality of trenches through the plurality of contact vias; the semiconductor testing structure tests the offset of the contact vias of the semiconductor by applying voltage at the first pad and the second pad.

In one specific embodiment of this utility model, the plurality of contact vias include: a plurality of first contact vias, each corresponding to a first end of a plurality of trenches, wherein a second pad is electrically connected to the trench through the first contact vias; and a plurality of second contact vias, each corresponding to a second end of a plurality of trenches, wherein a first pad is electrically connected to the trench through the second contact vias. The plurality of second contact vias are divided into adjacent first, second, and third portions. The second contact vias in the first portion overlap with the trench, the second contact vias in the second portion contact the trench but do not overlap, and the second contact vias in the third portion are spaced apart from the trench and do not overlap.

In one specific embodiment of this utility model, the overlap length between the second contact through hole and the groove decreases in a stepwise manner along the arrangement direction of the groove.

In one specific embodiment of this utility model, the step distance is 20-50 nm.

In one specific embodiment of this utility model, the spacing between any two adjacent grooves is equal.

In one specific embodiment of this utility model, the number of grooves is seven, and the number of second contact through holes is also seven.

In one specific embodiment of this utility model, the overlap lengths of the second contact through hole and the trench along the arrangement direction of the trench are 200nm, 150nm, 100nm, 50nm, 0nm, -50nm, and -100nm, respectively.

In one specific embodiment of this utility model, the groove extends along a first direction.

In one specific embodiment of this utility model, the groove extends along a second direction.

As can be seen from the above, the semiconductor test structure provided by this utility model embodiment includes a substrate, an epitaxial layer, a field oxide layer, a gate oxide layer, a dielectric layer, a metal layer, and contact vias. By setting trenches in the open area of the field oxide layer, and the contact vias passing through the dielectric layer, the metal layer and the contact vias are connected. By applying a voltage between the first pad and the second pad of the metal layer, and by testing the offset of the semiconductor contact vias based on the resistance or current change between the first pad and the second pad, the semiconductor overlay error can be characterized, enabling comprehensive monitoring of process changes, which is beneficial for timely troubleshooting and improving production efficiency.

Attached Figure Description

To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

Figure 1 is a schematic diagram of a semiconductor testing structure provided in an embodiment of this utility model.

Figure 2 is a top view of a semiconductor testing structure provided in an embodiment of this utility model.

Figure 3 is a top view of another semiconductor testing structure provided in an embodiment of this utility model.

Figures 4, 5, and 6 are schematic diagrams of the equivalent circuit.

Figure 7 is a flowchart illustrating the testing method of the semiconductor test structure according to an embodiment of the present invention.

Key component designations:

10. Substrate; 20. Epitaxial layer; 30. Gate oxide layer; 40. Trench; 41. First end; 42. Second end; 50. Contact via; 51. First contact via; 52. Second contact via; 60. Dielectric layer; 70. Metal layer; 71. First pad; 72. Second pad.

Detailed Implementation

To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments described in this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

It should be noted that all directional indicators (such as up, down, left, right, front, back, top, and bottom) in this utility model embodiment are only used to explain the relative positional relationship and movement of the components in a specific posture (as shown in the attached figure). If the specific posture changes, the directional indicator will also change accordingly. Furthermore, the term "vertical" in the utility model embodiments and claims refers to an angle of 90° between two components or a deviation of -5° to +5°, and the term "parallel" refers to an angle of 0° between two components or a deviation of -5° to +5°.

In this embodiment of the invention, the use of terms such as "first" and "second" is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

Referring to Figure 1, an embodiment of this utility model provides a semiconductor test structure, which can be used, for example, for testing and monitoring overlay errors in the manufacturing process of semiconductor devices such as power semiconductor MOSFET devices. The semiconductor test structure may include: a substrate 10, an epitaxial layer 20, a field oxide layer, a gate oxide layer 30, a dielectric layer 60, a metal layer 70, and a plurality of contact vias 50.

The substrate 10 can be a single-layer structure or a multilayer structure composed of the same or different materials. The substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III/V or II/VI compound semiconductors, or a layered substrate such as Si/SiGe, Si/SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator, or other materials other than semiconductor materials. The substrate 10 can be a wafer or a chip, and this invention does not limit this.

An epitaxial layer 20 is disposed on a substrate 10, specifically, for example, on the upper surface of the epitaxial layer 20. A field oxide layer is disposed on the epitaxial layer 20, and an open region is provided on the field oxide layer. A plurality of trenches 40 are spaced apart on the open region, and polysilicon is disposed in the trenches 40. A gate oxide layer 30 is located between the trenches 40 and the epitaxial layer 20. During the manufacturing process, for example, a plurality of spaced trenches 40 can be etched in the open region of the field oxide layer, and a gate oxide layer 30 is first grown in the trenches 40 and then deposited to form polysilicon. A dielectric layer 60 covers the outer surface of the epitaxial layer 20 away from the substrate 10. A metal layer 70 is disposed on the dielectric layer 60. The metal layer 70 includes a first pad 71 and a second pad 72 respectively connecting the two ends of the trenches 40. A plurality of contact vias 50 penetrate the dielectric layer 60, and the metal layer 70 is connected to the plurality of trenches 40 through the plurality of contact vias 50, that is, the first pad 71 and the second pad 72 are connected to the plurality of trenches 40 through the plurality of contact vias 50. The semiconductor test structure tests the offset of the semiconductor contact hole by applying voltage at the first pad 71 and the second pad 72. By applying voltage across the two ends of the semiconductor test structure, resistance or current is generated. Since the resistance or current characteristics are related to the overlay error of the semiconductor, the offset of the semiconductor contact hole can be reflected by measuring the change in resistance or current, thereby characterizing the overlay accuracy.

In the semiconductor manufacturing process, the fabrication processes and procedures for semiconductors and semiconductor test structures are fully compatible, requiring no additional photomasks and thus not increasing manufacturing costs. The semiconductor test structure can be located in the dicing area of the substrate under test (STDT). The STDT may include, for example, both the semiconductor and the semiconductor test structure. The dicing area is located around the semiconductor; cutting along the dicing area yields the semiconductor device. The semiconductor test structure does not occupy the area of the device region, avoiding interference with the wiring design of the device region, thereby preventing impact on device performance and increased production costs. In some embodiments, the semiconductor test structure may not be located in the dicing area; for example, it may be located within the device. However, this embodiment is not limited to this.

The semiconductor test structure provided in this embodiment includes a substrate 10, an epitaxial layer 20, a field oxide layer, a gate oxide layer 30, a dielectric layer 60, a metal layer 70, and a contact via 50. By setting a trench 40 in the open area of the field oxide layer, the contact via 50 passes through the dielectric layer 60, thereby connecting the metal layer 70 and the contact via 50. By applying a voltage between the first pad 71 and the second pad 72 of the metal layer 70, and by testing the offset of the semiconductor contact via based on the resistance or current change between the first pad 71 and the second pad 72, the semiconductor overlay error can be characterized, enabling comprehensive monitoring of process changes, which is beneficial for timely troubleshooting and improving production efficiency.

Referring to Figures 2 and 3, the plurality of contact vias 50 may include, for example, a plurality of first contact vias 51 and a plurality of second contact vias 52. The trench 40 includes opposing first ends 41 and second ends 42. The plurality of first contact vias 51 are correspondingly disposed at the first ends 41 of the trench 40, and the second pads 72 are electrically connected to the trench 40 through the first contact vias 51. The plurality of second contact vias 52 are correspondingly disposed at the second ends 42 of the plurality of trenches 40, and the first pads 71 are electrically connected to the trench 40 through the second contact vias 52. The plurality of trenches 40 may be, for example, equally spaced. The shape and size of the plurality of first contact vias 51 may be, for example, identical, and the first contact vias 51 may completely overlap with the trenches 40. The shape and size of the plurality of second contact vias 52 may also be, for example, identical, but the size of the first contact vias 51 may be, for example, smaller, and the size of the second contact vias 52 may be relatively larger than the size of the first contact vias 51.

In this embodiment, the plurality of second contact through holes 52 can be, for example, divided into adjacent first, second, and third portions. The second contact through holes 52 in the first portion overlap with the groove 40, the second contact through holes 52 in the second portion contact the groove 40 but do not overlap, and the second contact through holes 52 in the third portion are spaced apart from the groove 40 and do not overlap. The number of second contact through holes 52 is at least three, one of which overlaps with the groove 40, for example, partially; another second contact through hole 52 contacts the groove 40 but does not overlap; and a third second contact through hole 52 is spaced apart from the groove 40 and does not overlap. By setting three overlapping situations, more offset situations can be covered, thereby increasing the measurement range.

As shown in Figure 2, in one specific embodiment of this example, the trench 40 may extend along a first direction, which may be, for example, a horizontal direction. The first contact via 51 is located in the middle of the polysilicon in the trench 40. Due to the small size of the first contact via 51, it can always contact the polysilicon in the trench 40 with the same contact area regardless of its offset in the first direction, i.e., the horizontal direction. The offset of the second contact via 52 in the horizontal direction will cause an increase or decrease in the contact area between the second contact via 52 and the polysilicon in the trench 40. This will cause a change in resistance or current between the first pad 71 and the second pad 72 when a voltage is applied, thus characterizing the offset of the semiconductor contact hole in the horizontal direction.

As shown in Figure 3, in one specific embodiment of this example, the trench 40 may extend along a second direction, which may be, for example, a vertical direction. The first contact via 51 is located in the middle of the polysilicon in the trench 40. Due to the small size of the first contact via 51, it can always contact the polysilicon in the trench 40 with the same contact area regardless of its offset in the second direction, i.e., the vertical direction. The offset of the second contact via 52 in the vertical direction will cause an increase or decrease in the contact area between the second contact via 52 and the polysilicon in the trench 40. This will cause a change in resistance or current between the first pad 71 and the second pad 72 when a voltage is applied, thus characterizing the offset of the semiconductor contact hole in the vertical direction.

The offset of the semiconductor contact hole in the arrangement direction of the trench 40 will cause an increase or decrease in the contact area between the second contact via 52 and the polysilicon of the trench 40. The semiconductor test structure tests the offset of the semiconductor contact hole by applying voltage to the first pad 71 and the second pad 72 and measuring the resistance change between the first pad 71 and the second pad 72. The offset of the semiconductor contact hole is determined by comparing the test resistance between the first pad 71 and the second pad 72 with a resistance threshold. The first pad 71 and the second pad 72 are connected through the test instrument probes, and an appropriate voltage is applied from the first pad 71 to the second pad 72. The test instrument then records the resistance value between the first pad 71 and the second pad 72. When the test resistance is less than the resistance threshold, the semiconductor contact hole is offset to the left; when the test resistance is equal to the resistance threshold, the semiconductor contact hole is not offset; when the test resistance is greater than the resistance threshold, the semiconductor contact hole is offset to the right. Referring to Figures 4, 5, and 6, for example, in the initial state, the resistance is 1Ω, and there are four second contact vias 52 overlapping with the polysilicon of the trench 40, each with a resistance of 0.25Ω. When the test structure is offset 50nm to the right, there are five second contact vias 52 overlapping with the polysilicon of the trench 40, the parallel resistance increases, and the total resistance decreases, with a total resistance of 0.8Ω. The semiconductor contact holes are offset to the left. When the test structure is offset 50nm to the left, there are three second contact vias 52 overlapping with the polysilicon of the trench 40, the parallel resistance decreases, and the total resistance increases, with a total resistance of 1.3Ω. The semiconductor contact holes are offset to the right.

Furthermore, the overlap length between the second contact via 52 and the trench 40 decreases in a stepwise manner along the arrangement direction of the trench 40, which increases the effective measurement range. Preferably, the step distance can be, for example, 20-50 nm. In one specific embodiment of this example, the number of trenches 40 is seven, and the number of second contact vias 52 is also seven. The overlap lengths between the second contact vias 52 and the trenches 40 along the arrangement direction of the trenches 40 are successively 200 nm, 150 nm, 100 nm, 50 nm, 0 nm, -50 nm, and -100 nm. Of course, this embodiment is not limited to this. In this embodiment, the number of trenches 40 and the step distance of the overlap between the second contact vias 52 and the trenches 40 can be set according to actual needs.

Referring to Figure 7, the testing method for the semiconductor test structure of this utility model embodiment may include, for example, the following steps:

S10, providing a substrate under test, the substrate under test including the semiconductor test structure and semiconductor described above;

S20, the first pad and the second pad are connected through the probes of the test machine, and voltage is applied from the first pad to the second pad;

S30, the offset of the contact hole of the semiconductor is tested based on the resistance change between the first pad and the second pad.

The semiconductor testing method provided in this embodiment is implemented through the aforementioned semiconductor testing structure. Specifically, in the semiconductor manufacturing process, the fabrication processes and flows of the semiconductor and the semiconductor testing structure are fully compatible, requiring no additional mask and not increasing manufacturing costs. The semiconductor testing structure can be located in the dicing area of the substrate under test. The substrate under test may include, for example, a semiconductor and a semiconductor testing structure. The dicing area is located on the periphery of the semiconductor, and a semiconductor device can be obtained after cutting along the dicing area. The semiconductor testing structure does not occupy the area of the device area, avoiding affecting the wiring design of the device area, thereby avoiding affecting the performance of the device and increasing production costs. In some embodiments, the semiconductor testing structure may not be located in the dicing area, for example, it may be located inside the device. Of course, this embodiment is not limited to this. The first pad 71 and the second pad 72 of the semiconductor testing structure are connected to the probes of the testing machine and a voltage is applied. The first pad 71 is connected to the second pad 72, and an appropriate voltage is applied from the first pad 71 to the second pad 72. Then, the testing machine records the resistance value between the first pad 71 and the second pad 72, and tests the offset of the contact holes of the semiconductor based on the resistance change between the first pad 71 and the second pad 72. In some other embodiments, a test instrument may be used to record the current value between the first pad 71 and the second pad 72, and the offset of the contact hole of the semiconductor may be tested based on the current change between the first pad 71 and the second pad 72.

Specifically, for example, the test resistance between the first pad 71 and the second pad 72 can be compared with a resistance threshold, and the offset of the semiconductor contact hole can be determined based on the comparison result. When the test resistance is less than the resistance threshold, the semiconductor contact hole is offset to the left; when the test resistance is equal to the resistance threshold, the semiconductor contact hole is not offset; when the test resistance is greater than the resistance threshold, the semiconductor contact hole is offset to the right. Referring to Figures 4, 5, and 6, for example, when the initial resistance is 1Ω, there are four second contact vias 52 overlapping with the polysilicon of the trench 40, each with a resistance of 0.25Ω. When the test structure is offset 50nm to the right, five second contact vias 52 overlap with the polysilicon of the trench 40, increasing the parallel resistance and decreasing the total resistance. The total resistance is 0.8Ω, and the semiconductor contact holes are offset to the left. When the test structure is offset 50nm to the left, three second contact vias 52 overlap with the polysilicon of the trench 40, decreasing the parallel resistance and increasing the total resistance. The total resistance is 1.3Ω, and the semiconductor contact holes are offset to the right.

The semiconductor testing structure provided in this embodiment includes a substrate 10, an epitaxial layer 20, a field oxide layer, a gate oxide layer 30, a dielectric layer 60, a metal layer 70, and contact vias 50. A trench 40 is formed in the open area of the field oxide layer, and the contact vias 50 pass through the dielectric layer 60, connecting the metal layer 70 and the contact vias 50. The semiconductor testing method provided in this embodiment generates resistance by applying a voltage between the first pad 71 and the second pad 72 of the metal layer 70, thereby testing the offset of the semiconductor contact vias. This characterizes semiconductor overlay errors, enabling comprehensive monitoring of process changes, facilitating timely troubleshooting and improving production efficiency. Furthermore, by configuring multiple second contact vias 52 with the following configurations—a first portion overlapping the trench 40, a second portion contacting the trench 40 but not overlapping, and a third portion spaced apart from the trench 40 and not overlapping—a wider range of offset cases can be covered, increasing the measurement range. Furthermore, the overlap length of the second contact through hole 52 and the groove 40 is gradually reduced along the arrangement direction of the groove 40. This setting can further increase the effective measurement range, improve the monitoring effect, and help to troubleshoot in a timely manner and improve production efficiency.

Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of this utility model. Provided that the technical features do not conflict, the structure is not contradictory, and the inventive purpose of this utility model is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims (9)

1. A semiconductor test structure, comprising:

A substrate;

an epitaxial layer disposed on the substrate;

The field oxide layer is positioned on the epitaxial layer, an opening area is arranged on the field oxide layer, a plurality of grooves are formed in the opening area at intervals, and polysilicon is arranged in the grooves;

a gate oxide layer located between the trench and the epitaxial layer;

the dielectric layer is covered on the outer surface of the epitaxial layer, which is far away from the substrate;

A metal layer on the dielectric layer, the metal layer including a first bonding pad and a second bonding pad electrically connected to two ends of the trench, respectively, and

A plurality of contact through holes penetrating through the dielectric layer, the metal layer is connected with the grooves through the contact through holes;

the semiconductor test structure tests a deflection condition of a contact hole of a semiconductor by applying voltages at the first pad and the second pad.

2. The semiconductor test structure of claim 1, wherein the plurality of contact vias comprises:

the first contact through holes are arranged at the first ends of the grooves in a one-to-one correspondence manner, and the second bonding pads are electrically connected with the grooves through the first contact through holes;

The first bonding pads are electrically connected with the grooves through the second contact through holes, the second contact through holes of the first portions are arranged in an overlapping mode with the grooves, the second contact through holes of the second portions are in contact with the grooves but not in an overlapping mode, and the second contact through holes of the third portions are arranged in an interval mode with the grooves and not in an overlapping mode.

3. The semiconductor test structure of claim 2, wherein an overlapping length of the second contact via and the trench decreases stepwise along an arrangement direction of the trench.

4. The semiconductor test structure of claim 3, wherein the step distance is 20-50 nm.

5. The semiconductor test structure of claim 4, wherein a pitch between any adjacent two of the trenches is equal.

6. The semiconductor test structure of claim 3, wherein the number of trenches is seven and the number of second contact vias is also seven.

7. The semiconductor test structure of claim 6, wherein an overlapping length of the second contact via and the trench along an arrangement direction of the trench is 200nm, 150nm, 100nm, 50nm, 0nm, -50nm, -100nm in order.

8. The semiconductor test structure of any of claims 1-7, wherein the trench extends along a first direction.

9. The semiconductor test structure of any of claims 1-7, wherein the trench extends along a second direction.