CN222916006U

CN222916006U - A timing circuit, chip and electronic device

Info

Publication number: CN222916006U
Application number: CN202421594184.4U
Authority: CN
Inventors: 王泽源
Original assignee: Xi'an Xinhai Microelectronics Technology Co ltd
Current assignee: Xi'an Xinhai Microelectronics Technology Co ltd
Priority date: 2024-07-05
Filing date: 2024-07-05
Publication date: 2025-05-27
Anticipated expiration: 2034-07-05

Abstract

The application provides a time sequence circuit, a chip and electronic equipment, and belongs to the technical field of electronics. The time sequence circuit comprises a delay branch, an input branch and a clock generation module, wherein the input end of the delay branch is used for receiving an initial clock signal, the output end of the delay branch is connected with the first input end of the clock generation module, the input end of the input branch is used for receiving the initial clock signal, the output end of the input branch is connected with the second input end of the clock generation module, and the output end of the clock generation module is used for outputting a target clock signal, wherein the duty ratio of the target clock signal is larger than that of the initial clock signal. By adopting the application, the requirement of transmission delay can be reduced, and the design pressure of the related modules on the delay path can be reduced.

Description

Sequential circuit, chip and electronic equipment

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a timing circuit, a chip, and an electronic device.

Background

In the field of electronics, clock signals are commonly used in synchronous circuits to ensure synchronous operation of associated electronic components.

A common clock signal typically has a duty cycle of 50%, i.e. the high level and the low level have the same duration in the same period. In some circuits, the rising edge of the clock signal may be used as a starting point for processing and transmitting the input signal by the correlation module therein, and the processed signal is collected at the falling edge of the clock signal. For example, in a conversion path of an analog-to-digital conversion circuit, an input signal may be converted at a rising edge of a clock signal, and an output signal of a comparator may be collected at a falling edge of the clock signal. Therefore, it is necessary to ensure that the delay of the correlation module is less than half the clock period (e.g., 12.5 ns), so as to ensure that the correlation module completes before the falling edge of the clock signal arrives.

To reduce the propagation delay of the associated module, this is generally achieved by increasing the area of the electronic components and increasing the current. The larger the area of the electronic component, the faster the response speed, the larger the current, and the faster the transmission speed, and thus the delay time can be reduced. But the circuit area and power consumption are correspondingly increased.

Therefore, a new timing circuit is needed to form a new clock signal to reduce the transmission delay requirement.

Disclosure of utility model

In order to solve the problems in the prior art, the embodiment of the application provides a time sequence circuit, a chip and electronic equipment, which can reduce the requirement of transmission delay and reduce the design pressure of related modules on a delay path. The technical proposal is as follows:

According to an aspect of the present application, there is provided a timing circuit including a delay branch, an input branch, and a clock generation module;

The input end of the delay branch is used for receiving an initial clock signal, and the output end of the delay branch is connected with the first input end of the clock generation module;

The input end of the input branch is used for receiving the initial clock signal, and the output end of the input branch is connected with the second input end of the clock generation module;

the output end of the clock generation module is used for outputting a target clock signal;

Wherein the duty cycle of the target clock signal is greater than the duty cycle of the initial clock signal.

According to another aspect of the present application, there is provided a chip including the timing circuit described above.

According to another aspect of the present application, there is provided an electronic device including the timing circuit described above.

In the application, the time sequence circuit can comprise a delay branch, an input branch and a clock generation module, wherein the falling edge of the initial clock signal is delayed by the delay branch, so that the duty ratio of the target clock signal output by the clock generation module is improved, the allowable delay time is prolonged, the requirement of transmission delay is reduced, and the design pressure of the related module on the delay path is reduced.

Drawings

Further details, features and advantages of the application are disclosed in the following description of exemplary embodiments with reference to the following drawings, in which:

FIG. 1 shows a schematic diagram of a sequential circuit provided in accordance with an exemplary embodiment of the present application;

FIG. 2 illustrates a schematic diagram of a clock signal provided in accordance with an exemplary embodiment of the present application;

FIG. 3 illustrates another clock signal schematic provided in accordance with an exemplary embodiment of the present application;

FIG. 4 illustrates a first delay module schematic provided in accordance with an exemplary embodiment of the present application;

Fig. 5 shows a schematic diagram of a delay path of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

Fig. 6 shows a schematic diagram of a timing circuit of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application;

fig. 7 shows a schematic diagram of a level shift module provided according to an exemplary embodiment of the present application;

fig. 8 shows a second delay module schematic provided according to an exemplary embodiment of the application.

In the drawing the view of the figure,

1. The device comprises a delay branch, a first delay module, a first delay sub-module, a level conversion module, a second delay module, a delay branch, a delay sub-module, a first delay sub-module, a level conversion module, a delay sub-module, a delay branch, a delay input branch and a delay clock generation module.

Detailed Description

Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.

The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment," another embodiment "means" at least one additional embodiment, "and" some embodiments "means" at least some embodiments. Related definitions of other terms will be given in the description below. It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between different devices, modules, or units and not for limiting the order or interdependence of the functions performed by such devices, modules, or units.

It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise.

The names of messages or information interacted between the devices in the embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of such messages or information.

The embodiment of the application provides a time sequence circuit, and the detection circuit provided by the embodiment can be integrated in a chip or arranged in electronic equipment.

As shown in the timing circuit schematic of fig. 1, the timing circuit may include a delay arm 1, an input arm 2, and a clock generation module 3.

The input end of the delay branch 1 can be used for receiving an initial clock signal, and the output end of the delay branch 1 is connected with the first input end of the clock generation module 3;

The input end of the input branch 2 can be used for receiving the initial clock signal, and the output end 2 of the input branch is connected with the second input end of the clock generation module 3;

The output end of the clock generation module 3 is used for outputting a target clock signal;

Wherein the duty cycle of the target clock signal is greater than the duty cycle of the initial clock signal. The initial clock signal may refer to a clock signal commonly used in chips or electronic devices, with a duty cycle of typically 50%.

The implementation principle is as follows:

In one possible implementation, the initial clock signal may be input to the delay branch 1, and the falling edge in the initial clock signal is delayed for a certain period of time (referred to as a first period in this embodiment) by the delay branch 1, and the first clock signal is output. As shown in the clock signal diagram of fig. 2, a falling edge is triggered at a new time in the first clock signal.

Meanwhile, the initial clock signal is connected to the input branch 2, and the second clock signal is output through the input branch 2. The rising edge of the second clock signal may be the same as the trigger time of the rising edge in the initial clock signal, or the rising edge in the initial clock signal may be delayed for a certain period of time (this embodiment will be referred to as the second period of time), and the rising edge may be triggered at a new time. Wherein the second time period is less than the first time period.

Further, the clock generation module 3 may receive the first clock signal and the second clock signal, combine the falling edge of the first clock signal and the rising edge of the second clock signal, form a new clock signal, and output the new clock signal, that is, the target clock signal. Wherein, the duty cycle of the target clock signal is larger than that of the initial clock signal due to longer falling edge delay in the first clock signal.

By increasing the duty cycle of the target clock signal, the allowable delay time is prolonged, and the requirement of transmission delay is reduced, thereby reducing the design pressure of the related modules on the delay path.

Alternatively, the output end of the delay branch 1 may be used to output the delayed clock signal after delaying the initial clock signal, and the output end of the input branch 2 may be used to output the initial clock signal.

In a possible embodiment, the delay branch 1 may delay the whole of the initial clock signal by a certain length (i.e. the first time length), and output a delayed clock signal (i.e. a specific first clock signal), and the duty cycle of the delayed clock signal and the initial clock signal may be the same. It should be noted that the first duration at this time may be less than half of the clock period to ensure that the delayed falling edge triggers before the rising edge of the next clock period (i.e., the rising edge of the next clock period in the initial clock signal), as shown in fig. 3.

The input branch 2 may output the initial clock signal (i.e. a specific second clock signal) directly without any processing of the initial clock signal.

Alternatively, the clock generation module 3 may include an or gate unit.

In a possible implementation, as shown in the clock signal schematic diagram of fig. 3, in the clock generation module 3, the first clock signal and the second clock signal may be subjected to phase or processing, and a target clock signal may be output. The clock generation module 3 may output a high level voltage when either one of the two is at a high level, and the clock generation module 3 may output a low level voltage when both are at a low level. On this basis, taking one clock cycle of the initial clock signal as an example, the rising edge triggered first (i.e. the rising edge of the second clock signal of the input branch 2) and the falling edge triggered last (i.e. the falling edge of the first clock signal of the delay branch 1) can be reserved, so that the duty cycle of the target clock signal is improved.

Optionally, the target clock signal is used for a target circuit, and the target circuit may include at least one target delay module;

Referring to the first delay module schematic diagram shown in fig. 4, the delay branch 1 may include a first delay module 11, where the first delay module 11 includes at least one first delay sub-module 111, and the first delay sub-module 111 has the same structure as any target delay module.

In one possible implementation manner, the target delay module is a relevant module on a delay path in the target circuit, and the delay branch 1 may be provided with a first delay sub-module 111 with the same structure as that of the target delay module, which is used as the first delay module 11, that is, the first delay sub-module 111 has the same structure as any target delay module. When there are a plurality of target delay modules in the target circuit, at least one target delay module may be copied into the delay branch 1, i.e. the first delay module 11 may comprise at least one first delay sub-module 111.

When the first delay module 11 includes a plurality of first delay sub-modules 111, the plurality of first delay sub-modules 111 may be connected in series.

Under the same PVT (Process, voltage, temperature) conditions, the delays of the first delay sub-module 111 and the target delay module having the same structure can be generally regarded as equal. Therefore, the first duration of the delay branch 1 can be matched with the target delay module, and the delay of the target delay module is usually not more than half of the clock period, so that the first duration can be ensured to be less than half of the clock period. When the delay of the target circuit changes along with the change of PVT conditions, the first time length also generates the change with the same or similar trend along with the change of PVT conditions, and the time sequence circuit with the self-adaptive duty ratio is obtained.

Optionally, the target circuit may include an analog-to-digital conversion circuit, and the first delay sub-module 111 may include a first level conversion delay sub-module, a second level conversion delay sub-module, and a digital domain logic delay sub-module;

The first level conversion delay module refers to a delay sub-module for converting from low level to high level, and the second level conversion delay module refers to a delay sub-module for converting from high level to low level.

As a specific example, referring to the schematic diagram of the delay path of the analog-to-digital conversion circuit shown in fig. 5, according to the execution timing sequence among the modules, the delay path of the analog-to-digital conversion circuit may include a digital domain logic delay module of a 1.1V voltage domain, a first level conversion delay module of converting from 1.1V to 5V, a cdac switch array delay module of 5V domain, and a cdac setup delay module, a comparator transmission delay module of 3.3V domain, and a second level conversion delay module of converting from 3.3V to 1V.

The cdac V-domain switch array delay module and the cdac setup delay module are usually delay modules of an analog domain, and delay uncertainty exists in circuit modules of the analog domain, if the delay modules are copied to the delay branch 1, a falling edge after delay may trigger after a rising edge before delay of a next clock cycle (i.e., a rising edge of a next clock cycle in the initial clock signal), so that the clock generation module 3 cannot form a correct target clock signal.

Accordingly, the remaining digital domain delay modules may be copied to delay branch 1 as first delay sub-modules 111, i.e. comprising a first level shifting delay sub-module (corresponding to the first level shifting delay module described above for shifting from 1.1V to 5V), a second level shifting delay sub-module (corresponding to the second level shifting delay module described above for shifting from 3.3V to 1V) and a digital domain logic delay sub-module (corresponding to the digital domain logic delay module described above).

As a specific example, referring to the schematic timing circuit diagram of an analog-to-digital conversion circuit shown in fig. 6, a digital domain logic delay sub-module and a first level conversion delay sub-module may be connected in series in the delay branch 1, so that a falling edge of a first clock signal output by the delay branch 1 (that is, a falling edge of a target clock signal) may be adapted to digital logic delays and level conversion delays under different PVT conditions, that is, the falling edge may be adaptively adjusted according to actual situations of the analog-to-digital conversion circuit delays.

Optionally, referring to the schematic level shift module shown in fig. 7, the delay branch 1 may further include a level shift module 12;

An input of the first delay block 11 may be used to receive an initial clock signal;

The input end of the level conversion module 12 is connected with the output end of the first delay module 11, and the output end of the level conversion module 12 is connected with the first input end of the clock generation module 3.

In one possible implementation, if the output voltage of the first delay module 11 does not match the operating voltage domain of the clock generation module 3, a level conversion module 12 may be disposed after the first delay module 11 to convert the output voltage of the first delay module 11 to the operating voltage domain of the clock generation module 3. For example, in fig. 6, the output voltage of the first level shift delay sub-module is 5V domain, and assuming that the clock generation module 3 operates in 1.1V domain, the level shift module 12 for shifting from 5V to 1.1V may be set after the first level shift delay sub-module, so that the first clock signal output by the delay branch 1 is in 1.1V domain.

In particular, the level shift module 12 may include an even number of inverters connected in series, and the specific circuit of the level shift module 12 is not limited in this embodiment.

Optionally, referring to the second delay module schematic shown in fig. 8, the delay branch 1 may further include a second delay module 13, where the second delay module 13 includes at least one second delay sub-module 131, and the second delay module 13 is different from the first delay module 11.

In a possible embodiment, a second delay module 13 may be further arranged in the delay branch 1 according to the actual requirement of the circuit, and the second delay module 13 may be independent of the delay path of the target circuit, so as to further prolong the delay. When the second delay module 13 includes a plurality of second delay sub-modules 131, the plurality of second delay sub-modules 131 may be connected in series.

Optionally, the second delay sub-module 131 may include a logic gate unit, where the logic gate unit may include an and gate, an or gate, a not gate, and the like, and the embodiment is not limited to a specifically adopted logic gate unit.

Of course, the delay branch 1 may include a first delay module 11, a level shift module 12, and a second delay module 13, where the first delay module 11, the level shift module 12, and the second delay module 13 are connected in series. The level shift module 12 may be arranged after the first delay module 11 and before the clock generation module 3. The second delay module 13 may be disposed at any position, for example, before the first delay module 11, after the level conversion module 12, or alternatively, the logic gate units may be disposed in a scattered manner, which is not limited to the specific arrangement manner of the second delay module 13 in this embodiment.

The embodiment of the application has the following beneficial effects:

The exemplary embodiment of the application also provides a chip which comprises the time sequence circuit provided by the embodiment of the application. The time sequence circuit can comprise a delay branch, an input branch and a clock generation module, wherein the falling edge of the initial clock signal is delayed through the delay branch, so that the duty ratio of the target clock signal output by the clock generation module is improved, the allowable delay time is prolonged, the requirement of transmission delay is reduced, and the design pressure of the related module on the delay path of the chip is reduced.

The embodiment of the application also provides electronic equipment, which comprises the time sequence circuit provided by the embodiment of the application. The time sequence circuit can comprise a delay branch, an input branch and a clock generation module, wherein the falling edge of the initial clock signal is delayed through the delay branch, so that the duty ratio of the target clock signal output by the clock generation module is improved, the allowable delay time is prolonged, the requirement of transmission delay is reduced, and the design pressure of a related module on a delay path of the electronic equipment is reduced.

Claims

1. A sequential circuit, characterized in that the sequential circuit comprises a delay branch, an input branch and a clock generation module;

The input end of the delay branch is used to receive the initial clock signal, and the output end of the delay branch is connected to the first input end of the clock generation module;

The input end of the input branch is used to receive the initial clock signal, and the output end of the input branch is connected to the second input end of the clock generation module;

The output end of the clock generation module is used to output the target clock signal;

Wherein, the duty cycle of the target clock signal is greater than the duty cycle of the initial clock signal.

2. The timing circuit according to claim 1 is characterized in that the output end of the delay branch is used to output the delayed clock signal after the initial clock signal is delayed, and the output end of the input branch is used to output the initial clock signal.

3. The sequential circuit according to claim 1, wherein the target clock signal is used for a target circuit, and the target circuit comprises at least one target delay module;

The delay branch includes a first delay module, the first delay module includes at least one first delay submodule, and the structure of the first delay submodule is the same as that of any of the target delay modules.

4. The sequential circuit according to claim 3, characterized in that the target circuit comprises an analog-to-digital conversion circuit, and the first delay submodule comprises: a first level conversion delay submodule, a second level conversion delay submodule, and a digital domain logic delay submodule;

The first level conversion delay submodule refers to a delay submodule for converting from a low level to a high level, and the second level conversion delay submodule refers to a delay submodule for converting from a high level to a low level.

5. The timing circuit according to claim 3, characterized in that the delay branch further comprises a level conversion module;

The input end of the first delay module is used to receive the initial clock signal;

The input end of the level conversion module is connected to the output end of the first delay module, and the output end of the level conversion module is connected to the first input end of the clock generation module.

6 . The sequential circuit according to claim 3 , wherein the delay branch further comprises a second delay module, the second delay module comprises at least one second delay submodule, and the second delay module is different from the first delay module.

7 . The sequential circuit according to claim 6 , wherein the second delay submodule comprises a logic gate unit.

8 . The sequential circuit according to claim 1 , wherein the clock generation module comprises an OR gate unit.

9. A chip, characterized by comprising the sequential circuit according to any one of claims 1 to 8.

10. An electronic device, comprising the sequential circuit according to any one of claims 1 to 8.