CN222803341U - Photoelectric device based on multi-surface reflection - Google Patents
Photoelectric device based on multi-surface reflection Download PDFInfo
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Abstract
The utility model relates to a photoelectric device based on multi-surface reflection, which comprises a driving wafer and pixel units, wherein the driving wafer comprises an anode contact, the pixel units comprise pixel main bodies and outer edge wall bodies, the outer edge wall bodies are arranged on the side walls of the pixel main bodies, the outer edge wall bodies comprise side insulating layers and side reflecting metal layers, one side of each pixel main body is provided with an N-type semiconductor layer, the other side of each pixel main body is provided with a P-type semiconductor layer, a transparent conductive film layer and a bottom reflecting metal layer are formed between each P-type semiconductor layer and the driving wafer, the N-type semiconductor layers and the P-type semiconductor layers in each pixel unit are insulated through the side insulating layers, and the N-type semiconductor layers in all pixel units are connected through common cathodes. The utility model can effectively avoid the short circuit and leakage phenomenon, simultaneously ensure that each pixel unit can achieve the effect of multi-surface reflection, and increase the optical intensity of the LED photoelectric device.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a photoelectric device based on multi-surface reflection.
Background
The existing LED photoelectric device is generally provided with a single-sided reflecting mirror, the reflecting mirror is generally positioned at the bottom of a pixel luminous unit, an emergent light source of an LED faces all directions, the single-sided reflecting mode only utilizes bottom reflection, the luminous angle of the single-sided reflecting mirror is generally more than 110 degrees, the luminous collection rate and the utilization rate of the pixel unit are low, the improvement of the overall optical efficiency is not facilitated, the use requirement cannot be met, for example, for some projection fields, the luminous collimation degree of the light source is required to be higher, the luminous angle is smaller, the utilization rate of the light source is improved, and therefore the brightness of the LED photoelectric device is ensured, but the existing LED photoelectric device cannot meet the requirement. In addition, the electrical isolation effect inside the pixel unit of the existing LED photoelectric device is poor, short circuit and electric leakage are easy to occur, so that the photoelectric device is invalid, and the use reliability of the LED photoelectric device cannot be guaranteed.
Therefore, the existing LED photoelectric device cannot effectively ensure better optical intensity, and the pixel unit is easy to generate leakage failure phenomenon due to poor electrical isolation effect, so that the use reliability of the LED photoelectric device is affected.
Disclosure of utility model
Therefore, the technical problem to be solved by the utility model is to overcome the defects that the LED photoelectric device in the prior art cannot effectively ensure better optical strength and the pixel unit is easy to generate leakage failure, so as to improve the use reliability of the LED photoelectric device.
In order to solve the technical problems, the utility model provides a photoelectric device based on multi-surface reflection, which comprises,
A drive wafer including an anode contact therein;
The pixel unit is arranged on the driving wafer and corresponds to the anode contact, the pixel unit comprises a pixel main body and an outer edge wall body, the outer edge wall body is arranged on the side wall of the pixel main body, the outer edge wall body comprises a side surface insulating layer and a side surface reflecting metal layer, the inner wall of the side surface insulating layer is attached to the side wall of the pixel main body, and the outer wall of the side surface insulating layer is attached to the side surface reflecting metal layer;
An N-type semiconductor layer is arranged on one side, far away from the driving wafer, of the pixel main body, a P-type semiconductor layer is arranged on one side, close to the driving wafer, of the pixel main body, a transparent conductive film layer is formed between the P-type semiconductor layer and the driving wafer, the P-type semiconductor layer is electrically connected with a corresponding anode contact on the driving wafer through the transparent conductive film layer, and a bottom surface reflection metal layer is formed between the transparent conductive film layer and the driving wafer;
The N-type semiconductor layers and the P-type semiconductor layers in each pixel unit are insulated by the side insulating layer, and the N-type semiconductor layers in all the pixel units are connected by a common cathode.
In one embodiment of the present utility model, a bonding layer is further disposed between the bottom surface reflective metal layer and the driving wafer, the bonding layer is a conductive layer, the bonding layer includes a first bonding metal layer and a second bonding metal layer, the first bonding metal layer is electrically connected to the bottom surface reflective metal layer, and the second bonding metal layer is electrically connected to the anode contact.
In one embodiment of the present utility model, the P-type semiconductor layer and the bottom surface reflective metal layer are both in direct contact with the transparent conductive film layer to make electrical connection.
In one embodiment of the present utility model, a bottom surface reflection medium layer is further disposed between the transparent conductive film layer and the bottom surface reflection metal layer, and the bottom surface reflection medium layer is a non-conductive layer.
In one embodiment of the present utility model, the pixel unit further includes a side metal rail located outside the side reflection metal layer, and the transparent conductive film layer and the bottom reflection metal layer are electrically connected through the side metal rail.
In one embodiment of the present utility model, the refractive index of the bottom reflective dielectric layer is less than the refractive index of the transparent conductive film layer.
In one embodiment of the present utility model, the transparent conductive film layer adopts one or more of an TO film layer, a ZnO film layer, and an IZO film layer.
In one embodiment of the present utility model, the side insulating layer is formed with a step portion at one end thereof adjacent to the transparent conductive film layer, and the side reflective metal is located on the step portion.
In one embodiment of the present utility model, a metal mesh is further disposed between two adjacent pixel units, and each of the metal mesh is electrically connected to the common cathode.
In one embodiment of the present utility model, a microlens is further connected to each of the pixel units.
Compared with the prior art, the technical scheme of the utility model has the following advantages:
According to the multi-surface reflection-based photoelectric device, the outer edge wall body is arranged at the side wall of the pixel main body, so that the phenomenon of short circuit leakage between the N-type semiconductor layer and the P-type semiconductor layer of the pixel unit can be effectively avoided, the leakage risk and the crosstalk between pixels are well avoided, the use reliability of the LED photoelectric device can be better ensured, and meanwhile, multi-surface reflection of the side surface and the bottom surface of each pixel unit can be realized, so that the multi-surface reflection effect is achieved, the light-emitting collection rate and the utilization rate are improved, and the optical intensity and the brightness performance of the LED photoelectric device are improved.
Drawings
In order that the utility model may be more readily understood, a more particular description of the utility model will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.
FIG. 1 is a schematic diagram of the structure of one embodiment of a multi-faceted reflection-based photovoltaic device of this utility model (common cathode omitted);
FIG. 2 is a schematic structural diagram of another embodiment of a multi-faceted reflection-based photovoltaic device of this utility model (omitting the common cathode);
FIG. 3 is a schematic diagram of a driving wafer according to the present utility model;
FIG. 4 is a schematic structural view of an embodiment of a compound semiconductor in the present utility model;
fig. 5 is a schematic structural view of another embodiment of a compound semiconductor in the present utility model;
FIG. 6 is a schematic diagram of the preparation of an optoelectronic device using the compound semiconductor shown in FIG. 4;
FIG. 7 is a schematic diagram of the preparation of an optoelectronic device using the compound semiconductor shown in FIG. 5;
FIG. 8 is a schematic diagram of one embodiment of the present utility model of a photovoltaic device undergoing common cathode and microlens fabrication;
FIG. 9 is a schematic diagram of another embodiment of the present utility model for co-cathode and microlens fabrication of an optoelectronic device;
FIG. 10 is a schematic diagram of a third embodiment of the utility model for co-cathode and microlens fabrication of an optoelectronic device;
description of the specification reference numerals:
10. the wafer is driven, 101, anode contact;
20. Pixel unit, 201, pixel main body, 2011, N type semiconductor layer, 2012, active layer, 2013, P type semiconductor layer, 202, outer edge wall, 2021, side insulating layer, 20211, step part, 2022, side reflecting metal layer, 2023, side metal fence, 203, transparent conductive film layer, 204, bottom reflecting metal layer, 205, bottom reflecting medium layer;
30. bonding layer 301, first bonding metal layer 302, second bonding metal layer;
40. A common cathode;
50. a compound semiconductor 501, a substrate;
60. a metal mesh grid;
70. a microlens;
Detailed Description
The present utility model will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the utility model and practice it. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
In the description of the present utility model, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the utility model and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, unless otherwise indicated, the meaning of "a plurality" is two or more.
The embodiment provides a photoelectric device based on multi-surface reflection, so that the LED photoelectric device has better optical intensity, and the phenomenon of leakage failure of a pixel unit is effectively avoided, thereby improving the use reliability of the LED photoelectric device.
The structure of this embodiment will be further described with reference to fig. 1 to 10.
Example 1
Referring to fig. 1, the present embodiment discloses a multi-surface reflection-based photoelectric device, which includes a driving wafer 10 and a pixel unit 20, wherein the driving wafer 10 is used for driving and controlling light emission of the pixel unit 20;
The driving wafer 10 includes an anode contact 101 for implementing anode connection with the pixel unit 20;
the pixel unit 20 is disposed on the driving wafer 10 and corresponds to the anode contact 101;
The pixel unit 20 includes a pixel main body 201 and an outer edge wall 202, the outer edge wall 202 is disposed on a sidewall of the pixel main body 201, the outer edge wall 202 includes a side insulating layer 2021 and a side reflective metal layer 2022, an inner wall of the side insulating layer 2021 is attached to the sidewall of the pixel main body 201, such that no gap exists between the two, and an outer wall of the side insulating layer 2021 is attached to the side reflective metal layer 2022, such that no gap exists between the two;
An N-type semiconductor layer 2011 is disposed on a side of the pixel main body 201 away from the driving wafer 10, and a P-type semiconductor layer 2013 is disposed on a side of the pixel main body close to the driving wafer 10;
A transparent conductive film layer 203 is formed between the P-type semiconductor layer 2013 and the driving wafer 10, and the P-type semiconductor layer 2013 is electrically connected with the corresponding anode contact 101 on the driving wafer 10 through the transparent conductive film layer 203;
A bottom surface reflection metal layer 204 is formed between the transparent conductive film layer 203 and the driving wafer 10 to realize bottom surface reflection;
The N-type semiconductor layers 2011 and the P-type semiconductor layers 2013 in each pixel unit 20 are insulated by the side insulating layer 2021, and the N-type semiconductor layers 2011 in all pixel units 20 are connected by the common cathode 40.
In the above structure, the side surface insulating layer 2021 and the side surface reflecting metal layer 2022 form the side surface reflecting mirror, and the transparent conductive film layer 203 and the bottom surface reflecting metal layer 204 form the bottom surface reflecting mirror, so that a multi-surface reflecting cavity is formed, and light emitted by the pixel unit 20 can be reflected not only from the bottom surface but also from the side surface, thereby achieving multi-surface reflecting effect, improving light-emitting collection rate and utilization rate, facilitating the improvement of overall optical efficiency, greatly improving the brightness of the pixel unit 20 and the collimation degree of light, further restricting divergence angle while improving performance, and integrally improving the optical intensity and brightness of the pixel unit 20.
Further, the side insulating layer 2021 and the side reflective metal layer 2022 may be used to form an omni-directional mirror—odr (Omn i-d i rect i ona l ref l ector) mirror, and the transparent conductive film layer 203 and the bottom reflective metal layer 204 may also form an ODR mirror, so as to better reduce reflection loss and improve reflectivity, thereby better improving the brightness and intensity of the light-emitting unit 20.
In addition, in the above pixel unit 20 structure, by providing the outer edge wall body 202 at the side wall of the pixel main body 201, the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 in each pixel unit 20 are insulated from each other by the side insulating layer 2021, so that the short circuit leakage phenomenon between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 can be effectively avoided, and thus the use reliability of the pixel unit 20 structure is better ensured.
An active layer 2012 is typically disposed between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 of each pixel body 201 for emitting light, and the driving wafer 10 may be a CMOS integrated circuit.
In addition, the pixel units and the anode contacts may be in one-to-one correspondence, or a plurality of anode contacts may be in one pixel unit.
Taking M icro-LED field as an example, some compound materials related to this embodiment are shown in table 1 below, and in some practical applications, the compound film layer may be more complex, or there may be material cross-usage, and mainly includes P-type semiconductor layer material, N-type semiconductor layer material, and active layer (MQW quantum well) sandwiched between the two:
Table 1 film material tables of each compound
| Layer name | Material | Material | Material | Material | Material | Material | Material |
| P-type semiconductor layer | GaP | GaAs | GaAs | GaAs | AlGaN | GaN | GaN |
| MQW active quantum well | AlGaInP | AlGaInP | InGaAs | AlGaAs | InGaN | InGaN | InGaN |
| N-type semiconductor layer | GaAs | AlGaAs | AlGaAs | GaAs | GaN | GaN | GaN |
In one embodiment, a bonding layer 30 is further disposed between the bottom reflective metal layer 204 and the driving wafer 10, the bonding layer 30 is a conductive layer, so as to implement electrical conduction between the P-type semiconductor layer 2013 and the driving wafer 10, the bonding layer 30 includes a first bonding metal layer 301 and a second bonding metal layer 302, the bottom reflective metal layer 204 is electrically connected to the first bonding metal layer 301, and the second bonding metal layer 302 is electrically connected to the anode contact 101.
The P-type semiconductor layer 2013 and the bottom reflective metal layer 204 are in direct contact with the transparent conductive film layer 203 to be electrically connected, and at this time, the P-type semiconductor layer 2013 directly and sequentially passes through the transparent conductive film layer 203, the bottom reflective metal layer 204 and the bonding layer 30 to be electrically connected, without providing an external conductive structure.
In one embodiment, the transparent conductive film 203 on the bottom surface is one or more of ito (tin doped indium oxide) film, znO (zinc oxide) film, or ZO (indium zinc oxide) film.
The transparent conductive film layer 203 on the bottom surface may be directly used as a P-type ohmic contact layer of the P-type semiconductor layer 2013.
For example, an ITO film is formed on the surface of a P-type semiconductor layer by vapor deposition, sputtering, or the like using a Si-based blue indium gallium nitride (I n gan) compound, and ohmic contact is formed by high-temperature annealing TO form a P-type ohmic contact layer. The specific film thickness and conditions for forming the contact may be varied as desired, and are not limited herein.
In one embodiment, the thickness of the side insulating layer 2021 is greater than that of the side reflective metal layer 2022, so as to better ensure the insulating effect of the side insulating layer.
For example, the side insulating layer 2021 is a silicon oxide layer having a thickness of 300nm, and the side reflective metal layer 2022 is an aluminum layer having a thickness of 100 nm.
In one embodiment, as shown in fig. 1, a step portion 20211 is formed at an end of the side insulating layer 2021 near the transparent conductive film layer 203, and a side reflective metal is located on the step portion 20211.
In another embodiment, as shown in fig. 2, the side insulating layer 2021 may not have the step portion 20211 at an end near the transparent conductive film layer 203.
In an actual working condition, the step 20211 or the structure of the step 20211 may be obtained according to an actual manufacturing process.
In one embodiment, as shown in fig. 8-10, a metal mesh grid 60 is further disposed between two adjacent pixel units 20, and each metal mesh grid 60 is electrically connected to the common cathode 40, so as to enhance current expansion of the common cathode 40, further enhance light intensity and convergent light emission angle, and better prevent pixel crosstalk.
The metal grid 60 may be formed by patterned vapor deposition or patterned etching after film plating, for example, aluminum metal may be used as the metal grid.
In one embodiment, as shown in fig. 8-10, a microlens 70 is further disposed on each pixel unit 20, where the lens may be hemispherical or semi-rugby, and the focal point of the lens may be the surface of the common cathode 40 or the surface of the metal grid.
As shown in fig. 6, this embodiment also discloses a method for manufacturing an optoelectronic device based on multi-surface reflection, which includes:
1) As shown in fig. 3, the driving wafer 10 is first prepared so that the anode contact 101 is included in the driving wafer 10;
2) Connecting the compound semiconductor with the driving wafer 10, and processing the compound semiconductor 50 to form a pixel unit 20 corresponding to the anode contact 101, wherein the structure of the compound semiconductor 50 is shown in fig. 4;
The pixel unit 20 includes a pixel main body 201 and an outer edge wall 202, the outer edge wall 202 is disposed on a sidewall of the pixel main body 201, the outer edge wall 202 includes a side insulating layer 2021 and a side reflective metal layer 2022, an inner wall of the side insulating layer 2021 is attached to the sidewall of the pixel main body 201, and an outer wall of the side insulating layer 2021 is attached to the side reflective metal layer 2022;
An N-type semiconductor layer 2011 is arranged on one side of the pixel main body 201 far away from the driving wafer 10, a P-type semiconductor layer 2013 is arranged on one side of the pixel main body close to the driving wafer 10, a transparent conductive film layer 203 is formed between the P-type semiconductor layer 2013 and the driving wafer 10, and a bottom surface reflection metal layer 204 is formed between the transparent conductive film layer 203 and the driving wafer 10;
the P-type semiconductor layer 2013 is electrically connected to the corresponding anode contact 101 on the driving wafer 10 through the transparent conductive film layer 203, and the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013 in each pixel unit 20 are insulated by a side insulating layer 2021;
3) Finally, the N-type semiconductor layers 2011 in all the pixel units 20 are connected through the common cathode 40.
In one embodiment, the compound semiconductor and the driving wafer 10 are bonded through the bonding layer 30, the bonding layer 30 is a conductive layer, and the bonding layer 30 includes a first bonding metal layer 301 and a second bonding metal layer 302;
Before bonding, it is necessary to deposit a bonding metal at the bottom surface reflection metal of the compound semiconductor 50 to form a first bonding metal layer 301, and also deposit a bonding metal on the driving wafer 10 to form a second bonding metal layer 302, so that the anode contact 101 and the second bonding metal layer 302 are electrically connected, and then invert the compound semiconductor 50 so that the first bonding metal layer 301 and the second bonding metal layer 302 are thermally pressed and bonded together, thereby forming the bonding layer 30.
The bonding bond metal material may be one or more of N I +Sn combination, au+Sn combination, cu+Sn combination, au+ I n combination, au+Au combination, A l +Al combination, cu+Cu combination, ITO+ITO combination, and the like.
The compound semiconductor generally refers to a compound formed of two or more elements. Including crystalline inorganic compounds (e.g., group II-V, I I-VI compound semiconductors) and oxide semiconductors, etc. The compound semiconductor related by the application is mainly an LED epitaxial material, such as an InGaN ternary material system or an A/Ga/InP quaternary material system.
In one embodiment, as shown in fig. 4, the compound semiconductor 50 includes a substrate 501, and an N-type semiconductor layer 2011, a P-type semiconductor layer 2013, a transparent conductive film layer 203, a bottom surface reflection metal layer 204, and a first bonding metal layer 301 sequentially formed in a direction away from the substrate 501, with an active layer 2012 provided between the N-type semiconductor layer 2011 and the P-type semiconductor layer 2013;
A method of connecting a compound semiconductor to a driving wafer 10 and processing the compound semiconductor 50 to form a pixel cell 20 corresponding to an anode contact 101, includes,
Step S1), as in stage a in fig. 6, performing thermocompression bonding on the first bonding metal layer 301 of the compound semiconductor 50 and the second bonding metal layer 302 of the driving wafer 10 to achieve bonding connection;
Step S2), removing the substrate 501 of the compound semiconductor 50;
The substrate removing mode adopts different process modes according to different substrate materials, such as removing a sapphire substrate by adopting a laser stripping mode, removing a silicon substrate by adopting an HNA wet etching mode, and the like. After the substrate is removed, the N-type semiconductor is exposed on the surface of the wafer, the pixelated preparation condition is provided, and if necessary, an N-ohm contact layer can be prepared on the N-type semiconductor, wherein the ohm contact layer can be a transparent conductive layer or a single layer or a laminated layer of a metal layer such as Au, ge, al and the like.
The substrate may be gallium nitride (GaN), silicon (S I), silicon carbide (S I C), sapphire (Sapph I re), gallium arsenide (GaAs), indium phosphide (inp), or the like.
Step S3), as in stage b of fig. 6, etching the compound semiconductor 50 by a first etching method, wherein the transparent conductive film layer 203 is used as an etching stop layer during etching, thereby obtaining a plurality of pixel bodies 201 corresponding to the anode contacts 101;
The first etching method may be photolithography, dry etching, wet etching, or the like.
Step S4), as shown in stages c-d in fig. 6, forming an outer edge wall 202 at the sidewall of each pixel body 201, the outer edge wall 202 including a side insulating layer 2021 and a side reflective metal layer 2022, the side insulating layer 2021 being deposited on the sidewall of the pixel body 201, the side reflective metal layer 2022 being deposited on the outer wall of the side insulating layer 2021;
Step S5), as shown in stage e of fig. 6, the bonding layer 30 between the outer edge walls 202 of two adjacent pixel bodies 201 and the material layer above the bonding layer 30 are etched away, so that electrical isolation is formed between the pixel bodies 201.
It should be understood that the term "removing the material layer above the bonding layer 30" refers to removing all the material layers above the bonding layer 30 between the outer edge walls 202, for example, if the bonding layer 30 between the outer edge walls 202 further has a bottom metal reflective layer, a transparent conductive film layer 203, and the like, then all the material layers are removed, and if a bottom reflective dielectric layer 205 is further provided between the bottom metal reflective layer and the transparent conductive film layer 203, then all the material layers are removed.
The etching method in step S5) may BE an ibe (ion beam etching ) etching method.
Finally, a common cathode 40 may be prepared as shown in stage f of fig. 6.
Further, in step S4), the outer edge wall 202 may be formed at the side wall of each pixel body 201 by integral etching or by layered etching:
Referring to stage c-d in fig. 6, the overall etching method comprises depositing a side insulating layer 2021 on the outside of the pixel main body 201, depositing a side reflective metal layer 2022 on the outside of the side insulating layer 2021, performing overall etching on the overall structure formed by the side insulating layer 2021 and the side reflective metal layer 2022 by dry etching after the deposition is completed, and only retaining the side insulating layer 2021 and the side reflective metal layer 2022 on the side wall of the pixel main body 201 after etching;
In the pixel unit 20 obtained by the integral etching method, a step portion 20211 is formed at one end of the side insulating layer 2021 close to the transparent conductive film layer 203, and a side reflective metal is located on the step portion 20211.
Referring to stage c-f of fig. 7, the layered etching method includes, after depositing the side insulating layer 2021 on the outside of the pixel body 201, etching the side insulating layer 2021 by dry etching, leaving only the side insulating layer 2021 on the side wall of the pixel body 201 after etching, then depositing the side reflective metal layer 2022 on the outside of the side insulating layer 2021, etching the side reflective metal layer 2022 by dry etching after depositing, and leaving only the side reflective metal layer 2022 on the side wall of the pixel body 201 after etching.
In the pixel unit 20 obtained by the preparation method of the layering etching, the side insulating layer 2021 does not form a step portion near one end of the transparent conductive film layer 203.
According to the preparation method of the outer edge wall of the pixel unit, a photoetching machine is not required during preparation, and the preparation method is realized in a dry etching mode, so that the requirement on a more advanced photoetching machine can be eliminated, an exposure process is not required, the defects of graphical failure, large alignment deviation, high generation cost and the like caused by graphical etching by using the photoetching machine in the prior art are avoided, meanwhile, the preparation precision can be effectively ensured, the precision of an in-situ or self-alignment type can be achieved, and the submicron precision is realized by using a micron-sized equipment process.
In one embodiment, the side insulating layer 2021 includes one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium pentoxide, and niobium pentoxide.
In one embodiment, the bottom reflective metal layer 204 and the side reflective metal layer 2022 each comprise one or more of silver, aluminum copper alloy, aluminum nickel alloy, gold, rhodium, platinum.
In one embodiment, as shown in fig. 8, 9 or 10, when the N-type semiconductor layers 2011 in all the pixel units 20 are connected through the common cathode 40, the common cathode 40 may be formed by depositing a transparent conductive film on the N-type semiconductor sides of all the pixel units 20 by sputtering, evaporation or the like, and the film may be one or more of an ITO (tin doped indium oxide) film, an AZO (aluminum doped zinc oxide) film, an ATO (antimony doped tin oxide) film, an FTO (fluorine doped tin oxide) film, or a combination of several kinds of such films, or a metal doped ITO formed by annealing after plating thin Al, au, ag on the ITO surface TO enhance the current transmission capability of the common cathode 40 layer.
Specifically, as shown in the stage a of fig. 8, the surface planarization may be performed by CMP to expose the N-type semiconductor layer, and then co-cathode deposition may be performed by sputtering, vapor deposition, or as shown in the stage a of fig. 10, the N-type semiconductor layer may be exposed by patterning etching, and then co-cathode deposition may be performed by sputtering, vapor deposition, or in the stage of patterning etching to expose the N-type semiconductor layer, and likewise patterning etching the dielectric layer between pixels, where the etching depth of the dielectric layer may be the same as the etching depth of the exposed N-type semiconductor layer, or may be etched separately to a deeper depth, and then filling metal into the etched trench to prepare the co-cathode 40.
In one embodiment, the N-type semiconductor layers 2011 in all the pixel units 20 are electrically connected to the common cathode 40 after being connected to the common cathode 40, and then the metal mesh grid 60 is electrically connected to the common cathode 40.
Example two
As shown in fig. 2, the main difference between the present embodiment and the first embodiment is that a bottom surface reflection medium layer 205 is further disposed between the transparent conductive film layer 203 and the bottom surface reflection metal layer 204, and the bottom surface reflection medium layer 205 is a non-conductive layer, so as to enhance the bottom surface reflection effect through the bottom surface reflection medium layer 205.
Further, the bottom reflective dielectric layer 205 comprises one or more of silicon dioxide, silicon nitride, aluminum oxide, titanium pentoxide, and niobium pentoxide.
The above structure may jointly form an ODR mirror through the transparent conductive film layer 203, the bottom surface reflection dielectric layer 205, and the bottom surface reflection metal layer 204, or jointly form an ODR mirror through the bottom surface reflection dielectric layer 205 and the bottom surface reflection metal layer 204.
In one embodiment, the refractive index of the bottom reflective dielectric layer 205 is smaller than the refractive index of the transparent conductive film layer 203 to enhance ODR reflection.
In one embodiment, the pixel unit 20 further includes a side metal rail 2023, the side metal rail 2023 is located outside the side reflective metal layer 2022, and the transparent conductive film layer 203 and the bottom reflective metal layer 204 are electrically connected through the side metal rail 2023, so that anode communication between the P-type semiconductor layer 2013 and the bonding layer 30 is achieved.
As shown in fig. 7, this embodiment also discloses a manufacturing method of a multi-surface reflection-based photoelectric device, which is mainly different from the manufacturing method of the first embodiment in that the structure of the compound semiconductor 50 is shown in fig. 5, when the compound semiconductor 50 is connected to the driving wafer 10 and the compound semiconductor 50 is processed to form the pixel unit 20 corresponding to the anode contact 101, in step S5), the bonding layer 30 between the outer edge walls 202 of two adjacent pixel main bodies 201 and the material layer above the bonding layer are etched and removed, and then a side metal rail 2023 is further formed, and the side metal rail 2023 is located outside the side reflection metal layer 2022, so that the transparent conductive film 203 and the bottom reflection metal layer 204 are electrically connected through the side metal rail 2023.
The metal rail 2023 may BE a rail formed by etching the ibe, so that the rail may BE utilized without being eliminated, which is advantageous in simplifying a process and improving process stability, and also in improving a product yield and reducing a cost, and the metal rail may BE a rail formed in other manners.
According to the photoelectric device based on multi-surface reflection and the preparation method thereof, the side surface insulating layer and the side surface reflecting metal layer are introduced to form the side surface reflecting mirror, and the transparent conductive film layer and the bottom surface reflecting metal layer form the bottom surface reflecting mirror, so that a multi-surface reflecting cavity is formed, a multi-surface reflecting effect is achieved, the light emitting collection rate and the light utilization rate are improved, the brightness performance of the device is improved, in addition, the leakage risk and the crosstalk between pixels can be well avoided, and the pixel density of the LED device is improved.
All the above optional technical solutions can be combined to form an optional embodiment of the present utility model, and any multiple embodiments can be combined, so as to obtain the requirements of coping with different application scenarios, which are all within the protection scope of the present utility model, and are not described in detail herein.
It should be noted that the above-mentioned embodiments are merely examples for clarity of illustration, and not limited to the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (10)
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