CN221201168U - Package structure - Google Patents

Abstract

The utility model provides a packaging structure, comprising: the hybrid substrate comprises a main body substrate and a rewiring structure, wherein the main body substrate comprises a core layer, a first stacking layer and a second stacking layer, the first stacking layer and the second stacking layer are arranged on two opposite sides of the core layer, and the rewiring structure is arranged on one side, far away from the core layer, of the first stacking layer, is in contact with the main body substrate and is electrically connected with the main body substrate; the main chip module and the passive device matrixes are electrically connected through the hybrid substrate and are arranged on one side of the rewiring structure far away from the main substrate side by side, wherein each passive device matrix is provided with a plurality of chip areas and a cutting reserved area and comprises a plurality of passive device chips which are respectively arranged on the plurality of chip areas, the plurality of passive device chips are arranged side by side and are spaced from each other through the cutting reserved area, and the passive device matrixes are provided with substrates which extend continuously in the plurality of chip areas and the cutting reserved area. The package structure has improved device performance and warpage of the package structure can be reduced or avoided.

Description

Package structure

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor packaging, and in particular to a packaging structure.

Background technique

Chip on Wafer on Substrate (CoWoS) packaging is an advanced semiconductor packaging technology that can achieve high-density line connections between multiple chips and high-speed data transmission. How to optimize the signal transmission between the conductive elements of the packaging structure is an important research topic in this field; moreover, in CoWoS packaging, there may be a warpage problem. How to reduce the warpage of the packaging structure is also an important research topic in the field of packaging technology.

Utility Model Content

According to at least one embodiment of the present disclosure, a packaging structure is provided, comprising: a hybrid substrate, comprising a main substrate and a rewiring structure, the main substrate comprising a core layer, a first stacking layer and a second stacking layer, wherein in a direction perpendicular to the main surface of the hybrid substrate, the first stacking layer and the second stacking layer are arranged on opposite sides of the core layer, and the rewiring structure is arranged on a side of the first stacking layer away from the core layer, and is in contact with and electrically connected to the main substrate; a main chip module and at least one passive device matrix, which are electrically connected to each other through the hybrid substrate, and are arranged side by side on a side of the rewiring structure away from the main substrate in a direction parallel to the main surface of the hybrid substrate, wherein each of the passive device matrices has a plurality of chip areas and a cutting reservation area, and comprises a plurality of passive device chips respectively arranged in the plurality of chip areas, the plurality of passive device chips are arranged side by side in a direction parallel to the main surface of the hybrid substrate, and are spaced from each other by the cutting reservation area, wherein the passive device matrix has a substrate that continuously extends over the plurality of chip areas and the cutting reservation area.

In the packaging structure provided according to at least one embodiment of the present disclosure, the core layer includes a core dielectric layer and a conductive component, the first stacking layer includes a first dielectric layer and a first conductive structure, the second stacking layer includes a second dielectric layer and a second conductive structure, the first conductive structure, the conductive component and the second conductive structure are electrically connected to each other, the redistribution structure includes a third dielectric layer and a redistribution layer, and the third dielectric layer contacts the first dielectric layer, and the redistribution layer contacts and is electrically connected to the first conductive structure.

In the packaging structure provided according to at least one embodiment of the present disclosure, the stiffness of the core dielectric layer is greater than one or more of the stiffness of the first dielectric layer, the stiffness of the second dielectric layer, and the stiffness of the third dielectric layer.

In the packaging structure provided according to at least one embodiment of the present disclosure, the chip in the main chip module includes a chip substrate, and a first stiffness difference between the stiffness of the core dielectric layer and the stiffness of the chip substrate is smaller than a second stiffness difference between the stiffness of the first dielectric layer, the second dielectric layer or the third dielectric layer and the stiffness of the chip substrate.

In the packaging structure provided according to at least one embodiment of the present disclosure, the chip in the main chip module includes a chip substrate, and a first thermal expansion coefficient difference between the thermal expansion coefficient of the core dielectric layer and the thermal expansion coefficient of the chip substrate is smaller than a second thermal expansion coefficient difference between the thermal expansion coefficient of the first dielectric layer, the second dielectric layer or the third dielectric layer and the thermal expansion coefficient of the chip substrate.

In the packaging structure provided according to at least one embodiment of the present disclosure, the core dielectric layer includes an inorganic material.

In the packaging structure provided according to at least one embodiment of the present disclosure, the core dielectric layer includes glass.

In the packaging structure provided according to at least one embodiment of the present disclosure, the line width of the conductive line of the redistribution layer is smaller than the line width of the conductive line in the first conductive structure and/or the second conductive structure.

According to the packaging structure provided by at least one embodiment of the present disclosure, in the hybrid substrate, the sidewall of the redistribution structure is aligned with the sidewall of the main substrate in a direction perpendicular to the main surface of the hybrid substrate.

In the packaging structure provided according to at least one embodiment of the present disclosure, the passive device matrix includes: the substrate, including a first substrate portion located in the multiple chip areas and a second substrate portion located in the cutting reservation area; and a dielectric structure, arranged on one side of the substrate, continuously extending in the multiple chip areas and the cutting reservation area, and including a first dielectric portion located in the multiple chip areas and a second dielectric portion located in the cutting reservation area; wherein each passive device chip includes one or more passive devices arranged in or on at least one of the first substrate portion and the first dielectric portion.

In the packaging structure provided according to at least one embodiment of the present disclosure, the cutting reservation area includes at least the second substrate portion and the second dielectric portion, and the orthographic projection of the one or more passive devices on the hybrid substrate does not overlap with the orthographic projection of the cutting reservation area on the hybrid substrate.

In the packaging structure provided according to at least one embodiment of the present disclosure, the cutting reservation area further includes an alignment mark disposed in or on at least one of the second substrate portion and the second dielectric portion.

In the packaging structure provided by at least one embodiment of the present disclosure, the passive device matrix is a capacitor matrix, and each passive device chip includes one or more capacitors.

In the packaging structure provided according to at least one embodiment of the present disclosure, each passive device chip includes a silicon capacitor.

In the packaging structure provided according to at least one embodiment of the present disclosure, the plurality of capacitors of the plurality of passive device chips are connected in parallel to each other through the hybrid substrate.

The packaging structure provided according to at least one embodiment of the present disclosure also includes: an encapsulation layer, which is arranged on the side of the redistribution structure of the hybrid substrate away from the main substrate, and surrounds and covers the main chip module and the passive device matrix, wherein the encapsulation layer covers the side walls of the main chip module and the passive device matrix, and fills the gap between the main chip module and the passive device matrix.

In the packaging structure provided according to at least one embodiment of the present disclosure, the multiple passive device chips include an edge passive device chip located at the edge of the passive device matrix, and the edge passive device chip has a first chip side and a second chip side opposite to or adjacent to each other; the first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is covered by the encapsulation layer, and the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix, is adjacent to the cutting reservation area, and is separated from the encapsulation layer.

In the packaging structure provided according to at least one embodiment of the present disclosure, the main chip module includes a first chip and a second chip, and the first chip, the second chip and a plurality of passive device chips in the passive device matrix are electrically connected to each other through the rewiring structure.

In the packaging structure provided according to at least one embodiment of the present disclosure, the first chip includes a logic chip, and the second chip includes a memory chip.

In the packaging structure provided according to at least one embodiment of the present disclosure, the logic chip includes a system chip, and the memory chip includes a high-bandwidth memory chip.

In the packaging structure provided according to at least one embodiment of the present disclosure, from a plan view, the passive device matrix and the main chip module have side edges aligned in a direction parallel to the main surface of the hybrid substrate.

In the packaging structure provided according to at least one embodiment of the present disclosure, the at least one passive device matrix includes multiple passive device matrices, and the multiple passive device matrices are arranged on the same side or different sides of the main chip module in a direction parallel to the main surface of the hybrid substrate.

A package structure provided according to at least one embodiment of the present disclosure has improved device performance and can reduce or avoid warping.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

FIG. 1 shows a schematic cross-sectional view of a package.

FIG. 2 shows a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

FIG. 3 is a schematic cross-sectional view showing a more detailed structure of a package structure according to some embodiments of the present disclosure.

FIG. 4 shows a schematic plan view of a package structure according to some embodiments of the present disclosure.

FIG. 5 shows a schematic enlarged plan view of a passive device matrix according to some embodiments of the present disclosure.

FIG. 6 shows a schematic cross-sectional view of a passive device matrix according to some embodiments of the present disclosure.

FIG. 7 illustrates a schematic plan view of a passive device wafer according to some embodiments of the present disclosure.

Detailed ways

In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Generally speaking, a CoWoS package includes a chip, an interposer, and a substrate (or package substrate). The interposer is located between the chip and the substrate, providing interconnections between multiple chips and electrically connecting the chip to the substrate. Based on the type of interposer, the CoWoS package can be divided into the following three types: CoWoS-S package using a silicon substrate as an interposer, CoWoS-R package using an organic interposer including a rewiring structure, and CoWoS-L package using a combination of a bridge chip and a rewiring structure as an interposer.

In CoWoS-R and CoWoS-L packages, the interposer includes an organic dielectric layer and a redistribution structure, which is embedded in the organic dielectric layer and used to achieve electrical connections between multiple chips and between multiple chips and substrates. Since the interposer has an organic dielectric layer, this interposer (i.e., including an organic dielectric layer and a redistribution structure) is also called an organic interposer.

FIG. 1 shows a schematic cross-sectional view of a package.

Referring to FIG1 , the package 50 is a CoWoS package and includes one or more main chips 10, an interposer 25 and a substrate 30. The package 50 may also be referred to as a package structure. For example, a plurality of main chips 10 are disposed on one side of the interposer 25 and are electrically connected to the interposer 25. The interposer 25 includes an organic dielectric layer 20 and a rewiring structure 21 embedded in the organic dielectric layer 20. The substrate 30 is located on a side of the interposer 25 away from the main chip 10 and is electrically connected to the main chip 10 through the interposer 25. Here, the package 50 is illustrated by taking the CoWoS-R package as an example, and it should be understood that the interposer 25 may also be replaced by other types of interposers.

For example, a conductive connector 26 is further provided between the interposer 25 and the substrate 30 to provide an electrical connection between the interposer 25 and the substrate 30; for example, there is a gap between the interposer 25 and the substrate 30 in a direction perpendicular to the main surface of the substrate, and the interposer 25 is electrically connected to the substrate 30 through the conductive connector 26; in some examples, the package 50 further includes a bottom filling material layer 27 to fill the gap between the interposer 25 and the substrate 30 and surround and protect the conductive connector 26. In the package 50, the interposer 25 and the substrate 30 are separately formed by different manufacturing processes and are connected to each other through the conductive connector 26. For example, the conductive connector 26 may be or include a conductive bump such as a solder ball, such as a controlled collapsed chip connection (C4) bump.

In the CoWoS package, the sizes of the multiple main chips 10 on the interposer 25 may not be completely matched. For example, there may be some empty areas in the chip bonding area of the interposer 25. These empty areas are not conducive to stress balance, and thus may cause the package structure to warp. Dummy chips 3 may be arranged in these empty areas. Although the dummy chips 3 can play a role in reducing the warpage of the package, the dummy chips have no other electrical functions except filling the empty areas.

In the CoWoS package, passive devices are usually also included, and the passive devices are electrically connected to the main chip located on the interposer to provide corresponding electrical performance. For example, the passive device may be or include a capacitor, and can be used to reduce the power noise of the package structure. In the package structure, the power delivery network (PDN) provides a constant voltage track for the power/ground pins of the chip, etc., to ensure the normal operation of the device. The impedance of the power distribution network is a frequency-dependent impedance function: Z(ƒ); when the fluctuating current I(ƒ) passes through the power distribution network, voltage noise is generated: V(ƒ)=I(ƒ)×Z(ƒ), therefore, the principle of designing the power distribution network is to reduce the impedance of the power distribution network, thereby reducing the voltage noise. Reducing the impedance of the power distribution network can be achieved by adding capacitors to the package structure, and the higher the capacitance of the capacitor, the smaller the corresponding capacitive reactance, which is more conducive to reducing the impedance.

In CoWoS-S packaging, passive devices may be embedded in the interposer using a silicon substrate, but the space for embedding passive devices in the interposer is limited. For example, when the passive device is a capacitor, the capacitance of the capacitor embedded in the interposer of the silicon substrate may be limited, so that its ability to reduce power supply noise is also limited. In CoWoS-R packaging or CoWoS-L packaging, generally speaking, passive devices such as capacitors may not be embedded in the interposer, or the process difficulty and cost of embedding passive devices such as capacitors in the interposer of such packaging is very high, and the implementation is difficult.

Passive devices can be mounted on the package substrate, for example, on a side of the package substrate close to the interposer, or on a side of the package substrate away from the interposer and provided with a conductive terminal. For example, as shown in FIG1 , the package 50 may also include an electronic device 31, which is arranged on a side of the substrate 30 close to the interposer 25, and is electrically connected to the interposer 25 through the substrate 30 and the conductive connector 26, and then electrically connected to the main chip 10 through the interposer 25. The electronic device 31 is, for example, a passive device such as a ceramic capacitor. In some examples, a passive device (for example, a capacitor) may also be arranged on a side of the substrate 30 away from the interposer 25, and a connector 35 (or conductive terminal) is also arranged on the side of the substrate 30 away from the interposer 25 for external connection of the package 50; for example, the package 50 may be connected to the power supply terminal through a plurality of connectors 35. That is, the passive device and the connector may be arranged on the same side of the package substrate.

The passive device installed on the package substrate needs to be electrically connected to the main chip located on the interposer through the package substrate and the interposer. The connection path between the passive device and the main chip is relatively long, which may make the passive device unable to provide the corresponding electrical performance well. For example, when the passive device is a filter capacitor, the relatively long connection path may make the filtering effect of the capacitor limited and fail to reduce the power supply noise well. In addition, the passive device installed on the package substrate (for example, installed on the side close to the interposer) will occupy additional area of the package substrate, resulting in a larger overall size of the package structure. If the passive device is installed on the side of the package substrate away from the interposer, it is necessary to sacrifice part of the conductive terminal area to set the passive device, which may have an adverse effect on chips with high power consumption.

In response to the above problems, an embodiment of the present disclosure provides a packaging structure, including: a hybrid substrate, including a main substrate and a rewiring structure, the main substrate including a core layer, a first stacking layer and a second stacking layer, wherein in a direction perpendicular to the main surface of the hybrid substrate, the first stacking layer and the second stacking layer are arranged on opposite sides of the core layer, and the rewiring structure is arranged on a side of the first stacking layer away from the core layer, and is in contact with and electrically connected to the main substrate; a main chip module and at least one passive device matrix, which are electrically connected through the hybrid substrate, and are arranged side by side on a side of the rewiring structure away from the main substrate in a direction parallel to the main surface of the hybrid substrate, wherein each passive device matrix has a plurality of chip areas and a cutting reservation area, and includes a plurality of passive device chips respectively arranged in the plurality of chip areas, the plurality of passive device chips are arranged side by side in a direction parallel to the main surface of the hybrid substrate, and are spaced from each other by the cutting reservation area, wherein the passive device matrix has a substrate that continuously extends in the plurality of chip areas and the cutting reservation area.

In the embodiment of the present disclosure, the hybrid substrate is configured to include a main substrate and a rewiring structure, and the rewiring structure and the main substrate are directly in contact and electrically connected, and the main chip module and the passive device matrix are electrically connected through the hybrid substrate, and are arranged side by side on one side of the rewiring structure; in this way, the hybrid substrate can replace both the interposer and the substrate in the package shown in FIG1, that is, a package substrate that integrates the interposer and the substrate together, or it can also be called a hybrid package substrate. Moreover, the main substrate and the rewiring structure in the hybrid substrate are directly in contact and electrically connected, without being connected to each other through intermediate components such as solder balls, thereby shortening the connection path between the rewiring structure and the main substrate, that is, shortening the signal transmission path, thus improving the signal transmission efficiency and reducing the signal loss. Moreover, compared with the package shown in FIG1 in which the main chip is mounted on the interposer and the passive device is mounted on the substrate, the main chip module and the passive device matrix of the present disclosure are arranged side by side on the rewiring structure of the package structure, so the distance between the main chip module and the passive device matrix is closer, shortening the connection path between the two, so that the passive device matrix can better provide corresponding electrical performance for the main chip module. Therefore, the device performance of the package structure is improved.

On the other hand, arranging the main chip module and the passive device matrix side by side on one side of the hybrid substrate can also help balance the stress of the package structure, thereby reducing or avoiding the warping of the package structure. Moreover, compared with arranging multiple independent passive device chips individually on the hybrid substrate, the multiple passive device chips of the passive device matrix of the embodiment of the present disclosure are arranged on the hybrid substrate in a matrix form, which can reduce the space occupied by the passive device chips, improve the integration of the passive device chips, and can be more conducive to reducing the warping of the package structure. It can also simplify the manufacturing process and help reduce the overall size of the package structure without sacrificing the area on the side of the hybrid substrate away from the main chip module for setting the conductive terminals. Therefore, the side of the hybrid substrate away from the main chip module can be used to set a sufficient number of conductive terminals to provide electrical connection between the package structure and external components (for example, the power supply terminal).

In addition, compared with the method of setting a dummy chip in the package of Figure 1 to reduce warping, the embodiment of the present disclosure can not only reduce or avoid warping by setting a passive device matrix, but the passive device matrix can also provide corresponding electrical performance; that is, the function of reducing warping of the dummy chip and the function of the passive device are integrated together, which can also help reduce the package size and reduce the packaging cost.

FIG. 2 shows a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure.

2, in some embodiments, the package structure 500 includes a hybrid substrate 400, a main chip module 110, and at least one passive device matrix 120. For example, the hybrid substrate 400 includes a main substrate 350 and a rewiring structure 210; the rewiring structure 210 is disposed on the main substrate 350, in contact with and electrically connected to the main substrate 350. For example, the main substrate 350 includes a core layer 300, a first build-up layer 310, and a second build-up layer 320 that are electrically connected to each other; in a direction perpendicular to the main surface of the hybrid substrate 400, the first build-up layer 310 and the second build-up layer 320 are disposed on opposite sides of the core layer 300, and the rewiring structure 210 is disposed on a side of the first build-up layer 310 away from the core layer 300, in contact with and electrically connected to the first build-up layer 310. For example, the redistribution structure 210 and the first stacking layer 310 are located on a side of the core layer 300 close to the main chip module 110 and the passive device matrix 120, while the second stacking layer 320 is located on a side of the core layer 300 far from the main chip module 110 and the passive device matrix 120. In this document, the main surface of the hybrid substrate refers to a surface close to or far from the main chip module, and is, for example, a surface extending in the horizontal direction shown in the figure.

The main chip module 110 and the passive device matrix 120 are electrically connected to the hybrid substrate 400 and are electrically connected to each other through the hybrid substrate 400, and can be arranged side by side on a side of the redistribution structure 210 of the hybrid substrate 400 away from the main substrate 350 in a direction parallel to the main surface of the hybrid substrate 400. That is, the redistribution structure 210 is located between the main chip module 110 and the main substrate 350 and between the passive device matrix 120 and the main substrate 350. In some embodiments, each passive device matrix 120 has a plurality of chip areas 121 and a cutting reserved area 122, and includes a plurality of passive device chips 120a respectively arranged in the plurality of chip areas 121, the plurality of passive device chips 120a are arranged side by side in a direction parallel to the main surface of the hybrid substrate, and are spaced from each other by the cutting reserved area 122, wherein the passive device matrix 120 has a substrate that continuously extends in the plurality of chip areas 121 and the cutting reserved area 122.

In some embodiments, at least a portion of the main chip module 110 and the passive device matrix 120 are electrically connected to each other through a rewiring structure 210. For example, the rewiring structure 210 is mainly used to provide electrical connections between one or more chips in the main chip module 110 and a plurality of passive device chips in the passive device matrix 120, and to electrically connect the main chip module 110 and the passive device matrix 120 to the main substrate 350, for example, to achieve signal and power interconnection. The main substrate 350 can provide electrical connections between the main chip module 110 and the passive device matrix 120 and the conductive terminals 370. Part of the main substrate 350 can also be used to provide electrical connections between the main chip module 110 and the passive device matrix 120.

For example, a plurality of conductive terminals 370 may be provided on one side of the hybrid substrate 400 away from the main chip module 110 (i.e., the side of the second stacking layer 320 away from the core layer 300). The conductive terminals 370 may be or include solder balls, such as a ball grid array (BGA). However, the present disclosure is not limited thereto. For example, the package structure 500 may be further connected to other external components, such as a printed circuit board (PCB) through the conductive terminals 370.

FIG. 3 is a schematic cross-sectional view showing a more detailed structure of a package structure 500 according to some embodiments of the present disclosure.

3 , in some embodiments, the core layer 300 includes a core dielectric layer 301 and a conductive member 302 ; the first stacking layer 310 includes a first dielectric layer 305 and a first conductive structure 306 ; the second stacking layer 320 includes a second dielectric layer 307 and a second conductive structure 308 ; and the redistribution structure 210 may include a third dielectric layer 200 and a redistribution layer 205 .

For example, the conductive member 302 in the core layer 300 may include a conductive via penetrating the core dielectric layer 301 and/or conductive wires located on opposite sides of the core dielectric layer, the conductive wires and the conductive vias are connected to each other and electrically connected to the conductive layer in the buildup layer. The core dielectric layer 301 may be a single-layer or multi-layer structure, which is not limited in the present disclosure.

For example, the first conductive structure 306 of the first stacking layer 310 may be at least partially embedded in the first dielectric layer 305 and may include one or more layers of conductive wires and/or conductive vias, which may be used to provide electrical connections between conductive wires located in different layers, electrical connections between the conductive wires and the conductive components 302 of the core layer 300, and/or electrical connections between the conductive wires and the redistribution layer 205.

For example, the second conductive structure 308 of the second buildup layer 320 may be at least partially embedded in the second dielectric layer 307, and may include one or more layers of conductive wires, conductive vias and/or conductive pads, wherein the conductive vias may be used to provide electrical connections between conductive wires located in different layers, between the conductive wires and the conductive members 302 of the core layer 300, and/or between the conductive wires and the conductive pads; the conductive pads may be used to connect the conductive terminals 370, and may be embedded in the second dielectric layer 307 or may protrude from the surface of the second dielectric layer 307 on the side away from the core layer 300. It should be understood that for the sake of simplicity of the drawings, the conductive vias in the first buildup layer and the second buildup layer are not specifically shown in the drawings. The first dielectric layer 305 and the second dielectric layer 307 may each be a single layer or a multi-layer structure, and the present disclosure is not limited thereto.

For example, the redistribution structure 210 may have one or more redistribution layers (RDL) 205, and the one or more redistribution layers 205 may be at least partially embedded in the third dielectric layer 200. The third dielectric layer 200 may be a single-layer or multi-layer structure, and the present disclosure is not limited to this; each redistribution layer 205 may include a conductive line 201 and/or a conductive via 202. For example, the conductive via may be used to provide electrical connection between conductive lines located at different layers, electrical connection between the conductive line and the first conductive structure 306 of the first stacking layer 310, and/or electrical connection between the conductive line and the main chip module and the passive device matrix.

Continuing to refer to FIG3 , the first conductive structure 306, the conductive member 302, and the second conductive structure 308 of the main substrate 350 are electrically connected to each other. The redistribution layer 205 is electrically connected to the first conductive structure 306, and is further connected to other conductive elements of the main substrate through the first conductive structure 306. In the embodiment of the present disclosure, the redistribution structure 210 is included in the hybrid substrate 400, and its third dielectric layer 200 is in contact with the first dielectric layer 305 of the main substrate, and the redistribution layer 205 is in contact with the first conductive structure 306 of the main substrate and is electrically connected. Compared with the package shown in FIG1 , the redistribution structure 210 of the package structure 500 and the main substrate 350 are directly in contact and electrically connected, without the need for connection through an intermediate member such as a conductive connector located between the two. In this way, the signal transmission path in the package structure is shortened, the signal transmission efficiency is improved, and the signal loss or attenuation can be reduced. In some embodiments, the hybrid substrate 400 can facilitate the transmission of high-frequency signals.

In the hybrid substrate 400, the conductive member 302, the first conductive structure 306, the second conductive structure 308 and the redistribution layer 205 may each include a suitable conductive material, such as a metal material such as titanium, copper, etc. The first dielectric layer 305, the second dielectric layer 307 and the third dielectric layer 200 may each include an organic dielectric material, and the materials of these dielectric layers may be the same or different from each other. For example, the materials of the first dielectric layer 305, the second dielectric layer 307 and the third dielectric layer 200 may each be selected from at least one of dielectric materials such as polyimide (PI), Ajinomoto deposited film (ABF), resin (e.g., BT), etc.

In some embodiments, the material of the core dielectric layer 301 may be different from the materials of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200. For example, the stiffness of the core dielectric layer 301 is greater than one or more of the stiffness of the first dielectric layer 305, the stiffness of the second dielectric layer 307, and the stiffness of the third dielectric layer 200; for example, the stiffness of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may all be less than the stiffness of the core dielectric layer 301. In other words, the Young's modulus of the core dielectric layer 301 is greater than the Young's modulus of one or more of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200; for example, the Young's modulus of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may all be less than the Young's modulus of the core dielectric layer 301.

In some embodiments, the thermal expansion coefficient of the core dielectric layer 301 is smaller than the thermal expansion coefficient of one or more of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200; for example, the thermal expansion coefficients of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may all be greater than the thermal expansion coefficient of the core dielectric layer 301.

In some embodiments, the stiffness of the core dielectric layer may be more closely matched to the stiffness of the chip substrate of the chip in the main chip module than the first to third dielectric layers; for example, a first stiffness difference between the stiffness of the core dielectric layer and the stiffness of the chip substrate is smaller than a second stiffness difference between the stiffness of the first dielectric layer, the second dielectric layer, or the third dielectric layer and the stiffness of the chip substrate.

In some embodiments, the thermal expansion coefficient of the core dielectric layer may be more closely matched to the thermal expansion coefficient of the chip substrate of the chip in the main chip module than the first to third dielectric layers; for example, a first thermal expansion coefficient difference between the thermal expansion coefficient of the core dielectric layer and the thermal expansion coefficient of the chip substrate is smaller than a second thermal expansion coefficient difference between the thermal expansion coefficient of the first dielectric layer, the second dielectric layer, or the third dielectric layer and the thermal expansion coefficient of the chip substrate.

For example, the main chip module 110 includes one or more chips, and each chip may include a chip substrate S and a device layer D located on the chip substrate S. The chip substrate S may be or include a semiconductor substrate, such as a silicon substrate, and the chip substrate may also alternatively or additionally include other suitable semiconductor materials, such as germanium. The device layer D is disposed on one side of the chip substrate S, and may include active devices (e.g., transistors), passive devices (e.g., capacitors, inductors, etc.) or a combination thereof and an interconnection structure, and each device may be connected through the interconnection structure. It should be understood that the chip substrates of different chips may include the same or different semiconductor materials, and the device layers of different chips may include the same or different devices. The chip substrates of multiple chips have little difference in stiffness or thermal expansion coefficient, for example, they may be substantially the same.

In some embodiments, the stiffness and/or thermal expansion coefficient of the core dielectric layer 301 may match the stiffness and/or thermal expansion coefficient of the chip substrate S, i.e., have a small difference. For example, the stiffness difference between the core dielectric layer 301 and the chip substrate S is less than at least one of the stiffness difference between the first dielectric layer 305 and the chip substrate S, the stiffness difference between the second dielectric layer 307 and the chip substrate S, and the stiffness difference between the third dielectric layer 200 and the chip substrate S. For example, the stiffness differences between the first to third dielectric layers and the chip substrate are all greater than the stiffness difference between the core dielectric layer and the chip substrate.

For example, the difference in thermal expansion coefficient between the core dielectric layer 301 and the chip substrate S is smaller than at least one of the difference in thermal expansion coefficient between the first dielectric layer 305 and the chip substrate S, the difference in thermal expansion coefficient between the second dielectric layer 307 and the chip substrate S, and the difference in thermal expansion coefficient between the third dielectric layer 200 and the chip substrate S. For example, the differences in thermal expansion coefficient between the first to third dielectric layers and the chip substrate are all greater than the difference in thermal expansion coefficient between the core dielectric layer and the chip substrate.

For example, the core dielectric layer includes an inorganic material. For example, the core dielectric layer includes glass. By using the above materials, the core dielectric layer can have better thermal stability and mechanical strength. For example, the thermal stability and mechanical strength of the core dielectric layer of the embodiment of the present disclosure are better than the core layer using organic materials in some substrates.

In the embodiments of the present disclosure, by setting the above-mentioned materials of the core dielectric layer, that is, setting the core dielectric layer to have greater stiffness, smaller thermal expansion coefficient and/or setting the stiffness and/or thermal expansion coefficient of the core dielectric layer to match the chip substrate, the risk of warping of the packaging structure can be reduced.

Continuing to refer to FIG3 , in some embodiments, the conductive lines of the redistribution layer 205 are finer than the conductive lines in the main substrate 350. For example, the line width of the conductive lines of the redistribution layer 205 is smaller than the line width of the conductive lines of the first conductive structure 306 and/or the line width of the conductive lines of the second conductive structure 308; for example, the line width of the conductive lines of the redistribution layer 205 is smaller than the line width of the conductive lines of the first conductive structure 306, and smaller than the line width of the conductive lines of the second conductive structure 308; the line width of the conductive lines in the first conductive structure 306 and the line width of the conductive lines in the second conductive structure 308 may be substantially the same. For example, the line spacing between the conductive lines of the redistribution layer 205 is smaller than the line spacing between the conductive lines in the first conductive structure 306 and/or the line spacing between the conductive lines in the second conductive structure 308; for example, the line spacing between the conductive lines in the redistribution layer 205 is smaller than the line spacing between the conductive lines in the first conductive structure 306, and smaller than the line spacing between the conductive lines in the second conductive structure 308; the line spacing between the conductive lines in the first conductive structure 306 and the line spacing between the conductive lines in the second conductive structure 308 may be approximately the same.

It should be understood that the line width of the conductive line refers to the width of the conductive line in its width direction, and the width direction of the conductive line is perpendicular to the extension direction of the conductive line; the line spacing between the conductive lines refers to the center distance (pitch) between two adjacent conductive lines, which is roughly equal to the sum of the spacing (spacing) between two adjacent conductive lines and the width of the conductive line.

In some embodiments, the number of layers of conductive wires in the first conductive structure 306, the second conductive structure 308, and the redistribution layer 205 may be the same as or different from each other; for example, the number of layers of conductive wires in the first conductive structure 306 and the second conductive structure 308 may be the same as each other, and may be different from the number of layers of conductive wires in the redistribution layer 205; for example, the number of layers of conductive wires in the redistribution layer 205 may be less than the number of layers of conductive wires in the first conductive structure 306 and/or the number of layers of conductive wires in the second conductive structure 308.

For example, the thicknesses of the first dielectric layer 305, the second dielectric layer 307, and the third dielectric layer 200 may be the same or different from each other; for example, the thicknesses of the first dielectric layer 305 and the second dielectric layer 307 may be substantially the same; for example, the thickness of the third dielectric layer 200 may be less than the thickness of the first dielectric layer 305 and/or the thickness of the second dielectric layer 307. That is, compared with the first buildup layer 310 and the second buildup layer 320, the redistribution structure 210 may have a smaller overall thickness.

In some embodiments, at least part of the main chip module 110 and the passive device matrix 120 are electrically connected to each other through the rewiring structure 210 of the hybrid substrate 400. For example, at least part of the multiple chips in the main chip module 110 can be electrically connected to each other through the rewiring structure 210; for example, the multiple chips in the main chip module 110 and at least part of the multiple passive device chips in the passive device matrix can be electrically connected to each other through the rewiring structure 210. For example, the multiple chips in the main chip module 110 and some of the multiple passive device chips in the passive device matrix can also be electrically connected to each other through the rewiring structure 210 and the conductive elements in the main substrate 350.

In some embodiments, different routing requirements can be met by setting the conductive lines of the main substrate and the conductive lines of the redistribution structure in the hybrid substrate 400 to have different line widths and line spacings.

In some embodiments, the hybrid substrate 400 further includes a solder mask 360. For example, the solder mask 360 is disposed on a side of the main substrate 350 away from the redistribution structure 210, covers the surface of the main substrate 350 on this side, and has an opening to expose a portion of the surface of the second conductive structure in the second buildup layer 320 (for example, the surface of the conductive pad), so that the conductive terminal 370 can be electrically connected to the second conductive structure through the opening of the solder mask 360.

In some embodiments, since the main substrate 350 and the redistribution structure 210 are in direct contact, a solder resist layer may not be disposed on a side of the main substrate 350 close to the redistribution structure 210 .

Continuing to refer to FIG. 3, in some embodiments, each chip in the main chip module 110 is electrically connected to the hybrid substrate 400 through the first conductive bump 107, and each passive device chip 120a in the passive device matrix 120 is electrically connected to the hybrid substrate 400 through the second conductive bump 108. The first conductive bump 107 is arranged between each chip of the main chip module and the redistribution layer to electrically connect the chip to the redistribution structure; the second conductive bump 108 is arranged between the passive device matrix and the redistribution layer to electrically connect the passive device chip to the redistribution structure. For example, the first conductive bump 107 and the second conductive bump 108 can each be or include conductive bumps such as micro-bumps.

In some embodiments, the packaging structure 500 also includes a bottom filling layer 160, which fills the space between the main chip module 110 and the rewiring structure 210 and the space between the passive device matrix 120 and the rewiring structure 210, and surrounds the first conductive bump 107 and the second conductive bump 108 in a direction parallel to the main surface of the hybrid substrate.

In some embodiments, the package structure 500 further includes an encapsulation layer 180, which is disposed on the hybrid substrate 400, for example, on the side of the redistribution structure 210 away from the main substrate 350, and surrounds and covers the main chip module 110 and the passive device matrix 120. For example, the encapsulation layer 180 covers and contacts the sidewalls of the main chip module 110 and the sidewalls of the passive device matrix 120, and fills the gap between the main chip module 110 and the passive device matrix 120. In some embodiments, the encapsulation layer 180 may further cover the surface of the main chip module 110 and the passive device matrix 120 away from the hybrid substrate 400, wherein the surface of the main chip module 110 and the passive device matrix 120 away from the redistribution structure 210 (i.e., the upper surface shown in FIG. 3 ) may be substantially flush in a direction parallel to the main surface of the hybrid substrate. In an alternative embodiment, the surface of the encapsulation layer 180 away from the hybrid substrate 400, the surface of the main chip module 110 away from the hybrid substrate 400, and the surface of the passive device matrix 120 away from the redistribution structure 210 may be roughly flush in a direction parallel to the main surface of the hybrid substrate; that is, the surfaces of the main chip module 110 and the passive device matrix 120 away from the hybrid substrate 400 may be exposed without being covered by the encapsulation layer 180.

Fig. 4 is a schematic plan view of a package structure 500 according to some embodiments of the present disclosure. Fig. 3 is, for example, a cross-sectional view taken along line I-I' of Fig. 4 .

3 and 4, in some embodiments, in a direction parallel to the main surface of the hybrid substrate, the redistribution structure 210 of the hybrid substrate 400 and the main substrate 350 may have substantially the same size (e.g., width, area, etc.). The orthographic projections of the redistribution structure 210 and the main substrate 350 on the main surface of the hybrid substrate (or a reference plane parallel to the main surface) may coincide with each other. For example, as shown in FIG3, the sidewalls of the redistribution structure 210 and the sidewalls of the main substrate 350 may be substantially aligned with each other in a direction perpendicular to the main surface of the hybrid substrate.

For example, the redistribution structure 210 is directly formed on the main substrate 350, and the formed redistribution structure 210 has substantially the same dimensions as the main substrate 350. In the disclosed embodiment, the hybrid substrate 400 integrates the redistribution structure 210 and the main substrate 350, which can simplify the process flow and reduce the process cost.

In some embodiments, the main chip module 110 includes one or more chips, each of which may be a system on chip (SoC), a digital signal processor (DSP), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a memory chip, etc. For example, the main chip module 110 includes a plurality of chips, and the plurality of chips may include chips of the same type or different types. The plurality of chips are arranged side by side on the hybrid substrate and may be electrically connected to each other through the hybrid substrate.

For example, the main chip module 110 includes one or more first chips 101 and one or more second chips 102a, 102b, 102c, 102d; the one or more first chips and the one or more second chips are electrically connected to each other through a hybrid substrate. For example, the first chip, the second chip, and a plurality of passive device chips are electrically connected to each other through a rewiring structure in the hybrid substrate. For example, the one or more first chips may include a logic chip, which may include, for example, a system on chip (SoC); the one or more second chips may include a memory chip, which may include, for example, a high bandwidth memory (HBM) chip.

For example, each chip in the main chip module may include a chip substrate and a device layer as shown in FIG3, and the conductive bump is arranged on the side of the device layer away from the chip substrate. The side of the chip having the conductive bump or close to the device layer may be referred to as the front side or active side of the chip, and the side where the substrate of the chip is located (i.e., the side opposite to the front side) may be referred to as the back side. For example, each chip in the main chip module may be flip-chip mounted on a hybrid substrate so that its front side faces the rewiring structure of the hybrid substrate, and may be electrically connected to the rewiring structure through conductive connectors such as conductive bumps.

In some embodiments, a plurality of passive device matrices 120 and a plurality of chips in the main chip module 110 are arranged side by side on the hybrid substrate, and the passive device matrices are arranged at intervals from adjacent chips.

Figure 5 shows a schematic enlarged plan view of the passive device matrix 120 according to some embodiments of the present disclosure and a schematic enlarged view of the passive device chips in the passive device matrix; Figure 6 shows a schematic cross-sectional view of the passive device matrix along line A-A of Figure 5 according to some embodiments of the present disclosure.

3 to 6 , the passive device matrix 120 has a plurality of chip regions 121 and a cutting reserved region 122, and includes a plurality of passive device chips 120a respectively located in the plurality of chip regions 121. In each passive device matrix 120, the plurality of chip regions 121 may be arranged side by side in a direction parallel to the main surface of the hybrid substrate, for example, they may be arranged in an array including one or more rows and/or one or more columns along a first direction D1 and a second direction D2; the cutting reserved region 122 is located around each chip region 121 and separates adjacent chip regions 121. Each chip region 121 corresponds to a passive device chip 120a, that is, the passive device matrix 120 includes a plurality of passive device chips 120a, the plurality of passive device chips 120a are arranged side by side (for example, arranged in an array), and are separated from each other by the cutting reserved region 122. The first direction D1 and the second direction D2 intersect with each other, for example, are perpendicular to each other.

For example, multiple passive device chips 120a may have approximately the same size; multiple passive device chips 120a located in the same row may be approximately aligned with each other in the first direction D1, for example, have side walls (or called side edges) aligned with each other in the first direction D1; multiple passive device chips 120a located in the same column may be approximately aligned with each other in the second direction D2, for example, have side walls aligned with each other in the second direction D2.

For example, the cutting reserved area 122 may be in a grid shape; for example, the cutting reserved area 122 may have a first sub-area 122a extending along the first direction D1 and a second sub-area 122b extending along the second direction D2. For example, a plurality of first sub-areas 122a extend in parallel with each other along the first direction D1 and are arranged along the second direction D2; a plurality of second sub-areas 122b extend in parallel with each other along the second direction D2 and are arranged along the first direction D1; a plurality of first sub-areas 122a and a plurality of second sub-areas 122b intersect with each other and define a plurality of chip areas 121. Each chip area 121 may be surrounded by the cutting reserved area 122.

Referring to FIG. 5 and FIG. 6 , in some embodiments, the passive device matrix 120 includes a substrate 100, a dielectric structure 105 disposed on one side of the substrate 100, and a plurality of passive devices 106. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, and the substrate may alternatively or additionally include other suitable semiconductor materials, such as germanium. For example, the material of the dielectric structure 105 may include a silicon-containing material, such as silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof, and may be a single-layer structure or a multi-layer structure, such as a multi-layer structure including a plurality of dielectric layers. A plurality of passive devices 106 are disposed in the chip region 121, and at least a portion of the passive devices 106 may be embedded in at least one of the substrate 100 and the dielectric structure 105.

For example, the substrate 100 extends continuously in a plurality of chip regions 121 and a cutting reserved region 122, and includes a first substrate portion 100a located in the plurality of chip regions 121 and a second substrate portion 100b located in the cutting reserved region 122. The plurality of first substrate portions 100a and the second substrate portion 100b are in contact with each other and continuous, and have the same material. That is, the substrate 100 including the plurality of first substrate portions 100a and the second substrate portion 100b is an integrally formed continuous substrate, and no other material layer may be interposed between the first substrate portion and the second substrate portion, and there is no interface between the two. It should be understood that the boundary between the chip region and the cutting reserved region is shown in dashed lines in the figure only for the convenience of illustration, and does not mean that there is an interface between the chip region and the cutting reserved region.

For example, the dielectric structure 105 extends continuously in the plurality of chip regions 121 and the cutting reserve region 122, and includes a first dielectric portion 105a located in the plurality of chip regions 121 and a second dielectric portion 105b located in the cutting reserve region 122. The plurality of first dielectric portions 105a and the second dielectric portions 105b are in contact with each other and continuous, and have the same material. It should be understood that the dielectric structure 105 extends continuously in the chip region and the cutting reserve region means that one or more dielectric layers in the dielectric structure 105 each extend continuously in these regions, and the portions of the plurality of first dielectric portions and the second dielectric portions located in the corresponding dielectric layers are in contact with each other and continuous, without having an interface therebetween.

That is, the plurality of passive device chips 120a and the cutting reserve area 122 located in the plurality of chip regions 121 share the same substrate 100 and the same dielectric structure 105. In some embodiments, each passive device chip 120a includes one or more passive devices 106 disposed in or on at least one of the first substrate portion 100a and the first dielectric portion 105a of the corresponding chip region 121. It should be understood that the number, position, and structure of the passive devices in each chip region 121 shown in the figure are for illustration only, and the present disclosure is not limited thereto.

In some embodiments, the cutting reserved area 122 includes at least a second substrate portion 100b and a second dielectric portion 105b. One or more passive devices 106 of the plurality of passive device chips 120a may not extend into the cutting reserved area 122. The orthographic projections of the one or more passive devices 106 of the passive device chip 120a on a reference plane extending in a direction parallel to the main surface of the substrate are staggered from the orthographic projections of the cutting reserved area 122 on the reference plane, and the reference plane is, for example, the main surface of the hybrid substrate 400 shown in FIG. 3. In this article, the staggered orthographic projections of multiple components on the same reference plane means that the orthographic projections of the multiple components do not overlap, and include the orthographic projections of the multiple components being spaced apart from each other and not overlapping, and also include the situation where the orthographic projections of the multiple components are adjacent to each other but not overlapping.

In some embodiments, the cutting reserved area 122 is also provided with an alignment mark, which can be provided in or on at least one of the second substrate portion 100b and the second dielectric portion 105b. For example, the cutting reserved area 122 has an alignment mark 103 provided on the second dielectric portion 105b. It should be understood that the structural features such as the number, shape and position of the alignment mark 103 described in the figure are only for illustration, and the present disclosure is not limited thereto, and can be designed accordingly according to actual product requirements.

In some embodiments, the passive device matrix 120 is an integrated passive device matrix, and the passive device chips therein include capacitors, or may also include other types of passive devices. For example, the passive device matrix 120 is a capacitor matrix, and each passive device chip includes one or more capacitors, and the one or more capacitors may be or include silicon capacitors, for example. For example, the passive device 106 is a capacitor, such as a metal-insulator-metal (MIM) capacitor, a deep trench capacitor (DTC), or any other suitable type of capacitor. FIG6 schematically illustrates an electrode plate of a capacitor embedded in a dielectric structure using a MIM capacitor as an example, but the capacitor structure of the disclosed embodiment is not limited thereto.

Referring to FIGS. 3 to 6 , the passive device matrix 120 further includes a plurality of second conductive bumps 108 disposed in a plurality of chip regions 121 ; the second conductive bumps 108 are electrically connected to the passive devices 106 of the passive device chip 120 a and are used as external connection points of the passive device chip 120 a , for example, for electrical connection between the passive device chip 120 a and the rewiring structure. For example, a plurality of second conductive bumps 108 electrically connected to corresponding electrode plates of one or more capacitors may be provided in each passive device chip 120 a . The second conductive bumps 108 may be a single-layer or multi-layer structure, and may include metal materials such as titanium, copper, nickel, tin, silver, alloys thereof, or combinations thereof. For example, in some examples, the second conductive bumps 108 may be a multi-layer structure, and include a first metal layer, a second metal layer, and a solder layer stacked sequentially above the substrate; for example, the first metal layer may be or include a titanium copper (TiCu) layer, the second metal layer may be or include a nickel layer, and the solder layer may include tin silver (SnAg), but the present disclosure is not limited thereto. The type, size (eg, width, area, spacing), etc. of the plurality of second conductive bumps 108 may be set and adjusted according to product requirements.

In some embodiments, when the passive device matrix 120 is a capacitor matrix, multiple capacitors of multiple passive device chips 120a in the passive device matrix 120 can be connected in parallel with each other, for example, they can be connected in parallel with each other through the rewiring structure of the hybrid substrate and/or the main substrate; when the same passive device chip 120a includes multiple capacitors, the multiple capacitors can also be connected in parallel with each other. When multiple passive device matrices 120 are provided in the packaging structure, multiple capacitors of multiple passive device matrices 120 can also be connected in parallel with each other. Connecting multiple capacitors in parallel can increase the overall capacitance of the passive device matrix, which is beneficial to reduce the capacitive reactance and impedance in the packaging structure circuit, and further beneficial to reduce the power supply noise of the packaging structure.

Referring to FIG. 3 to FIG. 5 , in some embodiments, the plurality of passive device chips 120 of the passive device matrix 120 may include edge passive device chips, which are located at the edge of the passive device matrix 120, for example, adjacent to the main chip module 110 or close to the edge of the encapsulation layer 180. For example, the passive device matrix 120 is arranged in an array of n×m (i.e., n rows and m columns, where n≥1, m≥1, and m+n＞2), and the passive device chips 120 located in the 1st row, the nth row, the 1st column, and the mth column are edge passive device chips. In other words, the edge passive device chip is the outermost passive device chip among the plurality of passive device chips of the passive device matrix; the edge of the passive device matrix includes the sidewall of the passive device matrix and a portion of the area close to the sidewall.

For example, one side of the edge passive device chip may be adjacent to the main chip module (e.g., facing the main chip module) or close to the edge of the encapsulation layer 180 and covered (i.e., encapsulated) by the encapsulation layer 180, and the other side of the edge passive device chip is close to other passive device chips, adjacent to the cutting reservation area 122, and separated from the encapsulation layer 180.

For example, the edge passive device chip has a first chip side and a second chip side that are opposite to or adjacent to each other; the first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer, and is covered by the encapsulation layer; the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix, is adjacent to the cutting reservation area, and is separated from the encapsulation layer.

For example, in conjunction with FIG. 3 to FIG. 5 , in the example of the passive device matrix 120 arranged in a 5×8 array (i.e., 5 rows and 8 columns) as shown in FIG. 5 , the passive device chips 120a located in the 1st row, the 5th row, the 1st column, and the 8th column are edge passive device chips. For example, at least one side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer, and at least the other side of the edge passive device chip faces other passive device chips and is adjacent to the cutting reservation area 122.

For example, the edge passive device chip may have a first chip side a1 and a second chip side a2 that are adjacent to each other or opposite to each other in a direction parallel to the main surface of the hybrid substrate (e.g., the first direction D1 or the second direction D2), the first chip side a1 of the edge passive device chip faces the edge of the main chip module or close to the encapsulation layer, and is covered (i.e., encapsulated) by the encapsulation layer; while the second chip side a2 of the edge passive device chip faces other passive device chips, is adjacent to the cutting reservation area 122, and is separated from the encapsulation layer. The cutting reservation area 122 located on the second chip side a2 of the edge passive device chip is located between the edge passive device chip and the adjacent passive device chip, and is separated from the encapsulation layer.

In some embodiments, the first chip side a1 of the edge passive device chip may also be provided with a cutting reserved area 122, or the first chip side a1 of the edge passive device chip may be directly exposed on the side wall of the passive device matrix, and the cutting reserved area may not be provided on this side. The first chip side a1 of the edge passive device chip being encapsulated by the encapsulation layer may include the surface of a portion of the edge cutting reserved area located on the first chip side a1 of the edge passive device chip being covered by the encapsulation layer and in contact with the encapsulation layer, or the side surface of the first chip side a1 of the edge passive device chip being covered by the encapsulation layer and in contact with the encapsulation layer.

4 , in some embodiments, the rewiring structure 210 of the hybrid substrate 400 has a chip bonding region BR for bonding the main chip module 110 and the passive device matrix 120. For example, the chip bonding region BR may be centrally disposed on the hybrid substrate 400, that is, from a plan view, the center of the chip bonding region BR may coincide with the center of the hybrid substrate 400 (e.g., the center of the rewiring structure 210, the center of the main substrate 350), the chip bonding region BR may be a structure symmetrical about a center line extending through the center, and the hybrid substrate 400 may be a structure symmetrical about the center line.

The chip bonding area BR has a first bonding area R1 and a second bonding area R2. The first bonding area R1 is used to bond one or more chips in the main chip module 110 and can also be called the main chip bonding area; the second bonding area R2 is used to bond the passive device matrix 120 and can also be called the passive device bonding area. In the chip bonding area BR, there can be one or more second bonding areas R2; in the case of having multiple second bonding areas R2, the multiple second bonding areas R2 can be located on the same side or different sides of the first bonding area R1 in the direction parallel to the main surface of the hybrid substrate. For example, all chips in the main chip module 110 are arranged in the first bonding area R1, and each second bonding area R2 can be correspondingly arranged with a passive device matrix 120; that is, the passive device matrix 120 can be arranged one by one with the second bonding area R2. In the case of having multiple passive device matrices 120, the multiple passive device matrices 120 can be arranged on the same side or different sides of the main chip module 110 in the direction parallel to the main surface of the hybrid substrate.

In some embodiments, the plurality of chips in the main chip module 110 may be roughly evenly distributed in the first bonding area R1. In some examples, the plurality of chips in the main chip module 110 may have different shapes or sizes, etc., so that the first bonding area R1 may have an irregular shape. The second bonding area R2 is the vacant area in the chip bonding area BR except the first bonding area R1, and the passive device matrix 120 is arranged in the second bonding area R2 to fill the vacant area of the chip bonding area BR; for example, the chip bonding area BR formed by the second bonding area R2 and the first bonding area R1 may have a roughly regular shape, and may be roughly symmetrical, for example.

For example, in the example shown in FIG4 , the plurality of second bonding regions R2 are respectively located at the corners of the first bonding region R1, close to the edge of the hybrid substrate, the first chip and the plurality of second chips of the main chip module 110 are bonded to the first bonding region R1 of the rewiring structure 210, and the plurality of passive device matrices 120 are respectively bonded to the plurality of second bonding regions R2 of the rewiring structure 210. The plurality of passive device matrices 120 are disposed at the corners of the main chip module 110, close to the edge of the hybrid substrate.

In some embodiments, as shown in FIG. 4 , from a plan view, the first chip 101 may be centrally disposed relative to the rewiring structure 210, and the first chip 101 may be an axisymmetric structure; for example, the symmetry axis of the first chip 101 may coincide with the orthographic projection of the center line of the rewiring structure 210 on the main surface of the hybrid substrate, and the center line of the rewiring structure 210 may extend along the first direction D1 or along the second direction D2, and may also be the symmetry axis of the rewiring structure 210. In some embodiments, the plurality of second chips have substantially the same shape and size, and may be symmetrically disposed relative to the center line of the rewiring structure 210 extending along the first direction or the second direction. For example, the first chip 101 has a first side and a second side opposite to each other in the first direction D1, the second chip 102a and the second chip 102b are arranged on the first side of the first chip 101, and the second chip 102c and the second chip 102d are arranged on the second side of the first chip 101; the second chip 102a and the second chip 102c may be symmetrically arranged about the symmetry axis of the first chip 101 extending along the second direction D2 or the center line of the rewiring structure 210; similarly, the second chip 102b and the second chip 102d may be symmetrically arranged about the symmetry axis of the first chip 101 extending along the second direction D2 or the center line of the rewiring structure 210. The second chip 102a and the second chip 102b may be symmetrically arranged about the symmetry axis of the first chip extending along the first direction D1 or the center line of the rewiring structure; the second chips 102c and 102d may be symmetrically arranged about the symmetry axis of the first chip extending along the first direction D1 or the center line of the rewiring structure.

The passive device matrix 120 may overlap with one or more chips in the main chip module in at least one of the first direction D1 and the second direction D2. In this article, the overlapping of multiple components in a certain direction means that the orthographic projections of the multiple components on the reference plane perpendicular to the direction overlap; that is, the orthographic projection of the passive device matrix 120 on the reference plane perpendicular to the first direction D1 or the second direction D2 (for example, the extension plane of the side wall of the hybrid substrate) overlaps with the orthographic projection of one or more chips in the main chip module on the reference plane.

For example, the passive device matrix 120 may be arranged on one side of the first chip 101 in the first direction D1, and on one side of the second chip in the second direction D2. In the case where a plurality of passive device matrices 120 are arranged in the package structure, the shapes, sizes, etc. of the plurality of passive device matrices 120 may be the same or different from each other. In some examples, the passive device matrices 120 may have substantially the same shape and size, and may be arranged substantially symmetrically with each other. For example, in the example shown in FIG. 4 , two passive device matrices located at the upper left corner and the upper right corner of the chip bonding area or two passive device matrices located at the lower left corner and the lower right corner of the chip bonding area may be arranged symmetrically about the symmetry axis of the first chip extending along the second direction D2 or the center line of the redistribution structure; two passive device matrices located at the upper left corner and the lower left corner of the chip bonding area or two passive device matrices located at the upper right corner and the lower right corner of the chip bonding area may be arranged symmetrically about the symmetry axis of the first chip extending along the first direction D1 or the center line of the redistribution structure.

In some embodiments, from a plan view, the passive device matrix 120 and the main chip module 110 may have side walls (or referred to as side edges) that are substantially aligned in a direction parallel to the main surface of the hybrid substrate. For example, a side edge of the passive device matrix 120 may be aligned with a side edge of the first chip 101 extending along the first direction D1 in the first direction D1; for example, a side edge of the passive device matrix 120 may be aligned with a side edge of the second chip extending along the second direction D2 in the second direction D2.

In the embodiment of the present disclosure, by arranging a passive device matrix in the vacant area of the chip bonding region of the hybrid substrate, it is beneficial to balance the stress of the packaging structure, thereby reducing or avoiding the warping of the packaging structure.

It should be understood that the shapes, sizes, quantities, and arrangements of the chips of the main chip module 110 and the passive device matrix 120 shown in FIG. 4 are only for illustration, and the present disclosure is not limited thereto. The sizes, quantities, and arrangements of the chips of the main chip module 110 and the passive device matrix 120 can be set and adjusted according to actual product design and requirements, so that the main chip module 110 and the passive device matrix 120 can balance stress and reduce warping of the package structure.

Continuing to refer to FIG. 3 to FIG. 6, in some embodiments, the passive device matrix 120 is arranged on the hybrid substrate. In addition to reducing or avoiding the warping of the package structure, the passive device matrix can also provide corresponding electrical performance for the main chip module. For example, the passive device matrix 120 can be or include a capacitor matrix, and the passive device chips 120a therein can all be or include silicon capacitors. In addition to reducing the warping of the package structure, the passive device matrix 120 can also be helpful to improve the power supply performance and reliability of the package structure. For example, compared with the ceramic capacitor mounted on the substrate shown in FIG. 1, the silicon capacitor has a higher resonant frequency, which can effectively reduce high-frequency noise. The silicon capacitor has a lower parasitic resistance and/or a lower parasitic inductance, which is more conducive to reducing the impedance of the power supply network, thereby significantly reducing the power supply noise, and the silicon capacitor has a higher stability even at high temperatures, so the power supply performance and reliability of the package structure can be improved. On the other hand, compared with ceramic capacitors, silicon capacitors have smaller sizes (e.g., width, thickness, etc.), and more silicon capacitors can be arranged per unit volume, which is conducive to increasing the overall capacitance of the capacitor matrix, thereby more conducive to reducing power supply noise.

Specifically, under ideal conditions, capacitors can be considered as pure capacitors with only capacitance characteristics, but in fact, capacitors also have resistance characteristics and inductance characteristics coupled with them, that is, they also have parasitic resistance and/or parasitic inductance, where parasitic resistance is called equivalent series resistance (ESR) and parasitic inductance is called equivalent series inductance (ESL). In other words, there is not only capacitance C in the capacitor, but also resistance component (ie ESR) and inductance component (ie ESL). Therefore, the impedance characteristic curve of the capacitor presents a "V" shape, which is capacitive before the resonant frequency. As the frequency increases, the impedance decreases. The impedance at the resonant frequency depends on the ESR; after the resonant frequency, the impedance characteristic becomes inductive, and the impedance increases as the frequency increases. The inductive impedance characteristic depends on the ESL. The smaller the ESR, the lower the impedance at the resonant frequency. The smaller the ESL, the lower the impedance in the inductive area. Therefore, the smaller the ESR and ESL, the more conducive to the removal of high-frequency noise. Silicon capacitors have smaller ESR and/or ESL, which can better improve the impedance of the power supply network and thus reduce power supply noise.

For example, taking silicon capacitors and ceramic capacitors of the same capacitance value (e.g., 180nf) as examples, the resonant frequency of the ceramic capacitor can be located near 20MHz, the resonant frequency of the silicon capacitor can be located near 100MHz, and the ESL of the silicon capacitor can be about 1/10 of that of the ceramic capacitor. In other words, the silicon capacitor has a good suppression effect on the high-frequency noise on the packaging structure, and its ESL is only 1/10 of that of the ceramic capacitor, so it has a better decoupling effect (i.e., removing the noise on the chip power pin).

When there are multiple passive device matrices, the sizes of the multiple passive device matrices and the number of passive device chips contained therein may be the same or different; when the multiple passive device matrices are multiple capacitor matrices, the capacitance values of the multiple capacitor matrices may be the same or different. For example, multiple capacitor matrices with different capacitance values may be used, thereby reducing noise at different frequency points.

For example, in the example shown in FIG. 4 , the same capacitor type can be used in four capacitor matrices; for example, the capacitance value of a single capacitor in each capacitor matrix is 1 μf, and the capacitance value of each 5×8 capacitor matrix is 5×8×1μf=40μf; then the total capacitance of the four capacitor matrices is 40μf×4=160μf. In other examples, a combination of capacitor matrices with different capacitance values can also be used for power supply filtering. For example, multiple capacitor matrices with capacitance values of 1uf, 500nf, 180nf, 140nf, etc. can be used, and the multiple capacitor matrices are respectively set in different free areas. It should be understood that the above description of the capacitance is only for illustration, and the present disclosure is not limited thereto. The capacitance of the corresponding capacitor matrix can be set according to product requirements.

In some embodiments, when the passive device matrix 120 is a capacitor matrix, the passive device matrix 120 is provided to improve the warpage of the package structure and improve the power supply performance of the package structure, and it can also help reduce the overall size of the package device and improve the reliability of the package structure. For example, in some package structures without the capacitor matrix, embedding passive devices inside the hybrid substrate 400 may not be implemented or the process is too difficult, so it is necessary to set capacitors such as ceramic capacitors on the hybrid substrate 400 to reduce power supply noise, but the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the ceramic capacitor are high, and high-frequency noise cannot be improved. In addition, the size of the ceramic capacitor is relatively large and occupies a large area. If the ceramic capacitor is set on the side of the hybrid substrate close to the main chip module, the ceramic capacitor needs to occupy a large space, which may cause the overall size of the package structure to be large. If the ceramic capacitor is set on the side of the hybrid substrate away from the main chip module, the distance from the main chip is far, and the filtering effect it can play is limited; and if the capacitor and the conductive terminal are set on the same side of the hybrid substrate, it is necessary to sacrifice part of the conductive terminal area to set the capacitor, which may have an adverse effect on the chip with high power consumption.

In the embodiment of the present disclosure, a capacitor matrix having multiple capacitor chips is provided on the hybrid substrate 400, and more capacitor chips can be provided per unit area by using the capacitor matrix, that is, the capacitor matrix has an increased capacitance, which is more conducive to reducing the impedance in the package structure circuit, and further more conducive to reducing power supply noise. The size, capacitance, etc. of the passive device matrix of the embodiment of the present disclosure can be set and adjusted according to product needs.

Moreover, since the capacitor matrix is provided, it is not necessary to provide capacitors such as ceramic capacitors on the hybrid substrate or the number of ceramic capacitors provided on the hybrid substrate can be reduced, so that the additional area on the hybrid substrate can be avoided or the area on the hybrid substrate occupied by these capacitors can be reduced, thereby facilitating the reduction of the overall size of the package structure. For example, in some embodiments, a ceramic capacitor 220 can be selectively provided on the side of the hybrid substrate 400 away from the conductive terminal 370. In some embodiments, the ceramic capacitor 220 can be omitted, which can be more conducive to reducing the overall size of the package structure. The ceramic capacitor 220 is shown in dotted lines in the figure, indicating that the ceramic capacitor can be selectively provided on the hybrid substrate and can be omitted in some examples. Moreover, in the embodiment of the present disclosure, since the capacitor matrix is provided to effectively reduce the power supply noise, it is not necessary to provide a capacitor on the side of the hybrid substrate 400 away from the main chip module, thereby eliminating the need to occupy the area of the conductive terminal 370, and therefore a sufficient number of conductive connectors can be provided to provide electrical connection between the package structure and an external component (e.g., a power supply terminal).

7 shows a plan view of a passive device wafer 10 according to some embodiments of the present disclosure. For example, a passive device matrix 120 in a package structure is cut from the passive device wafer.

Referring to FIG. 7 , in some embodiments, the passive device wafer 10 is provided with a plurality of chip regions 121 and a cutting region 12, and a passive device chip 120a is provided in each chip region 121; the plurality of passive device chips 120a are spaced apart from each other by the cutting region 12. The plurality of passive device chips 120a may be arranged in an array, for example, may be arranged in an array including a plurality of rows and columns along a first direction D1 and a second direction D2. The cutting region 12 is located between adjacent passive device chips 120a to space the adjacent passive device chips 120a apart. One or more alignment marks may be provided in the cutting region 12, and the alignment marks are used, for example, for alignment during the manufacturing process of the passive device chip, the wafer cutting process, and the like.

For example, the matrix region MR is located in the passive device wafer, and the matrix region MR includes a plurality of passive device chips 120a and a first cutting region 12a located between the plurality of passive device chips 120a; the matrix region MR is the region in the wafer where the subsequently formed passive device matrix 120 is located before the wafer cutting process. The first cutting region 12a is the portion of the cutting region 12 located in the matrix region MR, and the cutting region 12 also includes a second cutting region 12b located around the matrix region MR.

The passive device wafer 10 is subjected to a wafer cutting process to cut the portion of the wafer located in the matrix region MR from the wafer and form a passive device matrix 120, that is, the passive device matrix located in the matrix region MR is separated from other passive device chips in the wafer by the wafer cutting process. For example, the passive device wafer 10 is subjected to a wafer cutting process along a cutting path, and the cutting path at least partially extends along the second cutting region 12b to separate the passive device matrix from other passive device chips located outside the matrix region MR, and form a passive device matrix 120 as shown in FIG5 . In some embodiments, the passive device matrix located in the matrix region of the wafer before the wafer cutting process may be referred to as an initial passive device matrix; that is, the wafer cutting process cuts the initial passive device matrix from the wafer to form a passive device matrix.

For example, FIG. 7 schematically shows the first cutting path CL1, the second cutting path CL2, the third cutting path CL3 and the fourth cutting path CL4 of the wafer cutting process, each of which at least partially extends along the second cutting area 12b around the matrix area. For example, the first cutting path CL1 and the second cutting path CL2 may extend along the first direction D1, the third cutting path CL3 and the fourth cutting path CL4 may extend along the second direction D2, and these cutting paths intersect each other and define the boundary of the passive device matrix. The cutting path of the wafer cutting process does not pass through the first cutting area 12a between the multiple passive device chips located in the matrix area. The wafer cutting process may be or include a mechanical saw process, a laser drilling process, a laser cutting process or a combination thereof.

After the wafer cutting process, the passive device matrix 120 located in the matrix region MR is separated from other passive device chips of the wafer located outside the matrix region MR; and the multiple passive device chips 120a located in the matrix region MR are retained in the formed passive device matrix 120 because the cutting area between these passive device chips 120a has not undergone the cutting process, that is, forming at least part of the cutting reserved area 122 shown in Figures 5 and 6, and the multiple passive device chips 120a in the passive device matrix are still continuous with each other and share the same substrate, but are not independent of each other. In some embodiments, the second cutting area 12b outside the outer side walls of the edge passive device chips of the passive device matrix 120 may be partially removed during the cutting process, and partially retained in the passive device matrix 120 and serve as part of the cutting reserved area 122; in other embodiments, the second cutting area 12b outside the outer side walls of the edge passive device chips of the passive device matrix 120 may be completely removed during the wafer cutting process, and the side walls of the edge passive devices may be exposed at the side walls of the passive device matrix.

In some embodiments, the manufacturing method of the package structure 500 includes the following steps: one or more chips in the main chip module 110 are bonded to the first bonding area R1 of the rewiring structure 210, and the first bonding area R1 can also be called the main chip bonding area. Then, the free area of the free area (i.e., the second bonding area R2) of the chip bonding area BR of the rewiring structure 210 except the first bonding area R1 is calculated. It should be understood that there may be one or more free areas. When there are multiple free areas, the free areas of the multiple free areas are calculated respectively. Each free area corresponds to a passive device matrix.

The matrix area of the required passive device matrix is set based on the spare area; for example, the matrix area may be less than or approximately equal to the spare area. The position of the matrix area is determined in the passive device wafer based on the set matrix area; for example, the number and arrangement of the passive device chips in the passive device matrix are calculated based on the matrix area; for example, the passive device matrix includes a plurality of passive device chips arranged in an n×m array, and the values of n and m can be calculated in this step. For example, the matrix form that satisfies the matrix area can be calculated based on the size of a single passive device chip in the passive device wafer and the size of the cutting area, that is, the values of n and m are obtained; then the position of the matrix area that meets the requirements is determined in the wafer. Afterwards, the above-mentioned wafer cutting process is performed to cut the passive device matrix located in the matrix area from the passive device wafer, that is, the required passive device matrix arranged in an n×m array is cut from the passive device wafer, and the size of the formed passive device matrix matches the size of the above-mentioned spare area.

It should be understood that when there are multiple free areas, after the free areas of the multiple free areas are calculated respectively, one or more subsequent steps can be performed to obtain a passive device matrix matching each free area. Multiple passive device matrices of different free areas can be cut from the same passive device wafer or different passive device wafers, and the sizes of the multiple passive device matrices can be the same or different. The capacitance values of the multiple passive device matrices can be the same or different.

After the passive device matrix 120 is cut from the wafer, the passive device matrix 120 is bonded to the empty area of the redistribution structure 210 , ie, the second bonding region R2 .

Therefore, the packaging structure of the embodiment of the present disclosure adopts a passive device matrix and can also simplify the process. For example, it can simplify the above-mentioned wafer cutting process and the bonding process between multiple passive device chips of the passive device matrix and the hybrid substrate. This can improve process efficiency, reduce the risk of chip failure, improve yield, and reduce process costs.

There are a few points to note:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

(2) Unless there is a conflict, the features of the same embodiment or different embodiments of the present disclosure may be combined with each other.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (22)

1. A package structure, comprising:

A hybrid substrate including a main body substrate including a core layer, a first buildup layer and a second buildup layer, wherein the first buildup layer and the second buildup layer are disposed on opposite sides of the core layer in a direction perpendicular to a main surface of the hybrid substrate, and a rerouting structure disposed on a side of the first buildup layer remote from the core layer and in contact with and electrically connected to the main body substrate;

A main chip module and at least one passive device matrix electrically connected to each other through the hybrid substrate and arranged side by side on a side of the rewiring structure remote from the main body substrate in a direction parallel to a main surface of the hybrid substrate,

Wherein each of the passive device matrices has a plurality of chip regions and dicing reserved regions, and includes a plurality of passive device chips respectively disposed in the plurality of chip regions, the plurality of passive device chips being disposed side by side in a direction parallel to a main surface of the hybrid substrate and being spaced apart from each other by the dicing reserved regions, wherein the passive device matrix has a substrate continuously extending between the plurality of chip regions and the dicing reserved regions.

2. The package structure of claim 1, wherein the core layer comprises a core dielectric layer and a conductive member, the first buildup layer comprises a first dielectric layer and a first conductive structure, the second buildup layer comprises a second dielectric layer and a second conductive structure, the first conductive structure, the conductive member, and the second conductive structure are electrically connected to each other, the redistribution structure comprises a third dielectric layer and a redistribution layer, and the third dielectric layer is in contact with the first dielectric layer, and the redistribution layer is in contact with and electrically connected to the first conductive structure.

3. The package structure of claim 2, wherein the core dielectric layer has a stiffness that is greater than one or more of the stiffness of the first dielectric layer, the stiffness of the second dielectric layer, and the stiffness of the third dielectric layer.

4. The package structure of claim 2, wherein the chip in the main chip module comprises a chip substrate, and a first stiffness difference between a stiffness of the core dielectric layer and a stiffness of the chip substrate is less than a second stiffness difference between a stiffness of the first dielectric layer, the second dielectric layer, or the third dielectric layer and a stiffness of the chip substrate.

5. The package structure of claim 2, wherein the chip in the main chip module comprises a chip substrate, and a first difference in thermal expansion coefficient between the thermal expansion coefficient of the core dielectric layer and the thermal expansion coefficient of the chip substrate is smaller than a second difference in thermal expansion coefficient between the thermal expansion coefficient of the first dielectric layer, the second dielectric layer, or the third dielectric layer and the thermal expansion coefficient of the chip substrate.

6. The package structure of claim 2, wherein the core dielectric layer comprises an inorganic material.

7. The package structure of claim 2, wherein the core dielectric layer comprises glass.

8. The package structure of claim 2, wherein a line width of the conductive lines of the redistribution layer is smaller than a line width of the conductive lines in the first conductive structure and/or the second conductive structure.

9. The package structure according to claim 1, wherein in the hybrid substrate, a sidewall of the rewiring structure is aligned with a sidewall of the main body substrate in a direction perpendicular to a main surface of the hybrid substrate.

10. The package structure of any one of claims 1-9, wherein the passive device matrix comprises:

the substrate comprises a first substrate part positioned in the plurality of chip areas and a second substrate part positioned in the cutting reserved area; and

A dielectric structure disposed on one side of the substrate, extending continuously between the plurality of chip regions and the dicing reserved region, and including a first dielectric portion in the plurality of chip regions and a second dielectric portion in the dicing reserved region;

Wherein each passive device chip includes one or more passive devices disposed in or on at least one of the first substrate portion and the first dielectric portion.

11. The package structure of claim 10, wherein the cut-and-hold region includes at least the second substrate portion and the second dielectric portion, and wherein an orthographic projection of the one or more passive devices on the hybrid substrate does not overlap with an orthographic projection of the cut-and-hold region on the hybrid substrate.

12. The package structure of claim 10, wherein the dicing reserved area further comprises an alignment mark disposed in or on at least one of the second substrate portion and the second dielectric portion.

13. The package structure of any one of claims 1-9, wherein the passive device matrix is a capacitive matrix and each passive device chip includes one or more capacitors.

14. The package structure of claim 13, wherein each passive device chip comprises a silicon capacitor.

15. The package structure of claim 13, wherein a plurality of capacitances of the plurality of passive device chips are connected in parallel with each other through the hybrid substrate.

16. The package structure according to any one of claims 1-9, further comprising:

And the encapsulation layer is arranged on one side of the rewiring structure of the hybrid substrate, which is far away from the main substrate, and surrounds and encapsulates the main chip module and the passive device matrix, wherein the encapsulation layer covers the side walls of the main chip module and the passive device matrix and fills a gap between the main chip module and the passive device matrix.

17. The package structure of claim 16, wherein the plurality of passive device chips includes an edge passive device chip located at an edge of the passive device matrix, the edge passive device chip having a first chip side and a second chip side opposite or adjacent to each other;

The first chip side of the edge passive device chip faces the main chip module or is close to the edge of the encapsulation layer and is encapsulated by the encapsulation layer, and the second chip side of the edge passive device chip faces other passive device chips in the passive device matrix and is adjacent to the cutting reserved area and separated from the encapsulation layer.

18. The package structure of claim 1, wherein the main chip module includes first and second chips, the first and second chips and a plurality of passive device chips in the passive device matrix being electrically connected to each other through the rerouting structure.

19. The package structure of claim 18, wherein the first chip comprises a logic chip and the second chip comprises a memory chip.

20. The package structure of claim 19, wherein the logic chip comprises a system chip and the memory chip comprises a high bandwidth memory chip.

21. The package structure of claim 1, wherein the passive device matrix and the main chip module have sides aligned in a direction parallel to a main surface of the hybrid substrate in plan view.

22. The package structure of claim 1, wherein the at least one passive device matrix comprises a plurality of passive device matrices, and the plurality of passive device matrices are disposed on the same side or different sides of the main chip module in a direction parallel to a major surface of the hybrid substrate.