CN212810303U

CN212810303U - Composite power element

Info

Publication number: CN212810303U
Application number: CN202020867365.5U
Authority: CN
Inventors: 徐信佑; 王振煌; 洪世杰
Original assignee: Quanyuxin Technology Co ltd
Current assignee: Quanyuxin Technology Co ltd
Priority date: 2020-05-21
Filing date: 2020-05-21
Publication date: 2021-03-26
Anticipated expiration: 2030-05-21

Abstract

The utility model discloses a composite power element, which includes a substrate structure, an insulating layer, a dielectric layer, a metal oxide semi-conductor field effect transistor, and a Zener diode. The metal oxide semi-conductor field effect transistor is formed in the transistor forming region of the substrate structure. The Zener diode is formed in the circuit element forming region of the substrate structure and includes a Zener diode doping structure formed on the insulating layer and covered by the dielectric layer. The Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other. The Zener diode also includes a Zener diode metal structure, which is formed on the dielectric layer and partially penetrates the dielectric layer to electrically connect the P-type doping region and the N-type doping region of the Zener diode doping structure. The Zener diode is configured to receive a reverse bias when the composite power element is powered on. Thereby, the process complexity of the composite power element can be simplified, and the volume of the terminal product can also be reduced.

Description

Composite power element

Technical Field

The present invention relates to a power device, and more particularly to a composite power device.

Background

In existing power components, such as: for example, a metal-oxide-semiconductor field effect transistor (MOSFET), a Bipolar Junction Transistor (BJT), or other circuit elements (such as a resistor or a zener diode) may be added to a circuit design to form an electronic circuit with a specific function, and the circuit elements may be electrically connected to a power device by soldering. However, the connection between the circuit device and the power device increases the complexity of the product and cannot effectively reduce the volume of the product.

Therefore, the present inventors have found that the above-mentioned drawbacks can be improved, and have made intensive studies and application of the theory, and finally, have proposed a novel and effective method for improving the above-mentioned drawbacks with a rational design.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved in the present invention is to provide a composite power device for the deficiency of the prior art.

The embodiment of the utility model discloses compound power component, include: a substrate structure including a base layer and an epitaxial layer formed on the base layer; the epitaxial layer is concavely provided with at least one groove, the substrate structure is defined with a transistor forming area and a circuit element forming area adjacent to the transistor forming area along the length direction of the substrate structure, and the groove is positioned in the transistor forming area; an insulating layer formed on the epitaxial layer and the inner wall of the trench in an extending manner; the part of the insulating layer, which is positioned on the inner wall of the groove, is defined as a groove insulating layer which surrounds and forms a groove, and the rest part of the insulating layer is defined as a covering insulating layer; a dielectric layer formed on the insulating layer; a metal oxide semiconductor field effect transistor located in the transistor forming region and comprising: a gate filling structure formed in the groove of the trench insulation layer; a substrate doping structure formed in the epitaxial layer and located in the peripheral region of the trench; a source metal structure formed on the dielectric layer and partially penetrating the dielectric layer to electrically connect the substrate doped structure; and a drain metal structure formed on a bottom surface of the substrate layer; and a zener diode located in the circuit element formation region and including: a Zener diode doping structure formed on the coating insulating layer and covered by the dielectric layer; the Zener diode doping structure comprises a P-type doping area and an N-type doping area which are mutually connected; and a Zener diode metal structure formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region of the Zener diode doped structure; wherein the Zener diode is configured to receive a reverse bias voltage when the composite power device is energized.

Preferably, in the zener diode, the zener diode metal structure includes two metal pins, the two metal pins are disposed at an interval and partially penetrate the dielectric layer to be electrically connected to the N-type doped region and the P-type doped region of the zener diode doped structure, respectively; when the composite power element is electrified, the potential of the metal pin connected with the P-type doped region is lower than that of the metal pin connected with the N-type doped region, so that the reverse bias voltage is generated.

Preferably, the composite power element further includes: a resistor located in the circuit element forming region and disposed at a distance from the zener diode, and the resistor comprising: a resistor doped structure formed on the insulating cover layer and covered by the dielectric layer; the resistor doping structure is a P-type doping semiconductor or an N-type doping semiconductor; and a resistor metal structure formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the resistor doped structure, wherein the resistor is configured to generate a resistance when the composite power device is powered on.

Preferably, the composite power element further includes: a conventional diode located in the circuit element formation region and disposed at a distance from the zener diode, and the conventional diode includes: a conventional diode doping structure formed on the cover insulating layer and covered by the dielectric layer; the conventional diode doping structure comprises a P-type doping area and an N-type doping area which are mutually connected; and a conventional diode metal structure formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region of the conventional diode doping structure; wherein the conventional diode is configured to receive a forward bias voltage; wherein the conventional diode is disposed adjacent to the MOSFET.

Preferably, in the conventional diode, the conventional diode metal structure includes two metal pins, the two metal pins are spaced apart from each other, and both of the two metal pins partially penetrate through the dielectric layer to be electrically connected to the N-type doped region and the P-type doped region of the conventional diode doped structure, respectively; when the composite power element is electrified, the potential of the metal pin connected to the P-type doped region is higher than that of the metal pin connected to the N-type doped region, so that the forward bias voltage is generated.

Preferably, in the conventional diode, the metal pin connected to the P-type doped region is configured to be electrically connected to the gate fill structure of the mosfet through a wire, and the metal pin connected to the N-type doped region is configured to be electrically connected to the source metal structure of the mosfet through a wire.

Preferably, the number of the conventional diodes is plural, and the plural conventional diodes are disposed on the coating insulating layer in series with each other.

Preferably, in any two adjacent conventional diodes connected in series with each other, the metal pin of one of the conventional diodes connected to the P-type doped region is directly contacted and electrically connected to the metal pin of the other of the conventional diodes connected to the N-type doped region; and wherein the conventional diode doping structure of one of the conventional diodes is not in direct contact with the conventional diode doping structure of the other of the conventional diodes.

Preferably, among a plurality of the conventional diodes connected in series with each other, the metal pin of the first conventional diode connected to the P-type doped region may be electrically connected to the gate fill structure of the mosfet by a wire, and the metal pin of the last conventional diode connected to the N-type doped region may be electrically connected to the source metal structure of the mosfet by a wire.

The utility model has the advantages that the composite power device provided by the utility model can integrate the formation of different electronic devices (such as Zener diode, resistor, conventional diode) in the process of the metal-oxide-semiconductor field effect transistor (especially the process after depositing polysilicon) to form the required power device, which does not need to add additional process, thereby simplifying the process complexity and reducing the volume of the terminal product.

For a further understanding of the features and technical content of the present invention, reference should be made to the following detailed description and accompanying drawings, which are only intended to illustrate the present invention, and not to limit the scope of the present invention.

Drawings

Fig. 1A to fig. 1H are schematic flow diagrams illustrating a manufacturing method of a composite power device according to a first embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of a composite power device according to a first embodiment of the present invention (an equivalent circuit corresponding to the structure of the device is shown).

Fig. 3 is an equivalent circuit diagram of a composite power device according to a first embodiment of the present invention.

Fig. 4 is a partial schematic view of a composite power element according to a second embodiment of the present invention.

Fig. 5 is an equivalent circuit diagram of a composite power device according to a second embodiment of the present invention.

Detailed Description

The embodiments disclosed in the present invention are described below with reference to specific embodiments, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure in the present specification. The present invention may be practiced or carried out in other different embodiments, and various modifications and changes may be made in the details of this description based on the different points of view and applications without departing from the spirit of the present invention. The drawings of the present invention are for illustrative purposes only and are not drawn to scale. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or from one signal to another signal. In addition, the term "or" as used herein should be taken to include any one or combination of more of the associated listed items as the case may be.

[ first embodiment ]

Referring to fig. 1A to fig. 1H, fig. 2 and fig. 3, a first embodiment of the present invention provides a method for manufacturing a composite power device 100. The method for manufacturing the composite power device includes steps S110 to S180. Wherein, fig. 1A to fig. 1H are schematic diagrams illustrating a manufacturing method of a composite power device according to the first embodiment of the present invention, fig. 2 is a schematic diagram illustrating a cross-sectional view (indicating an equivalent circuit corresponding to the device structure) of a composite power device according to the first embodiment of the present invention, and fig. 3 is an equivalent circuit diagram of a composite power device according to the first embodiment of the present invention.

It should be noted that the order of the steps and the actual operation manner described in the present embodiment can be adjusted according to the requirement, and are not limited to the description in the present embodiment.

The composite power device 100 of the present embodiment is a metal-oxide-semiconductor field-effect transistor (MOSFET) based power device. That is, the composite power device 100 of the present embodiment is an improved power device based on a mosfet. Furthermore, the composite power device 100 of the present embodiment may be applied to a high voltage regulator (high voltage regulator), for example, but the invention is not limited thereto.

In the present embodiment, a method for manufacturing a composite power device is described below, but for convenience of understanding, a unit region of the method for manufacturing a composite power device is taken as an example, and a cross-sectional view is taken for description, so that reference is mainly made to the drawings corresponding to each step, and to the drawings corresponding to other steps as needed. The specific steps of the method for manufacturing the composite power element are described below.

As shown in fig. 1A, the step S110 includes: a substrate structure 1 is provided. Wherein, the substrate structure 1 comprises: a base layer 11 (underlayer) and an epitaxial layer 12(epitaxial layer) formed on the base layer 11, and two surfaces of the substrate structure 1 on opposite sides are respectively defined as a top surface 101 and a bottom surface 102. More specifically, a surface of the epitaxial layer 12 opposite to the base layer 11 is the top surface 101, and a surface of the base layer 11 opposite to the epitaxial layer 12 is the bottom surface 102.

The material of the base layer 11 may be, for example, an N + -type doped semiconductor or a P + -type doped semiconductor. The epitaxial layer 12 may be formed on the base layer 11, for example, by an epitaxial process, and the conductive form of the epitaxial layer 12 may be the same as that of the base layer 11 (e.g., N + type doping or P + type doping).

In the present embodiment, the base layer 11 is an N + type doped semiconductor (i.e., N + Substrate) and the epitaxial layer 12 is an N-type doped semiconductor (i.e., N-EPI). The doping concentration of the substrate layer 11 is higher than that of the epitaxial layer 12, that is, the substrate layer 11 is a heavily doped region, and the epitaxial layer 12 is a lightly doped region, but the present invention is not limited thereto.

Further, the substrate structure 1 defines a transistor forming region a (transistor forming region) and a circuit element forming region b (circuit element forming region) adjacent to the transistor forming region a along a length direction D thereof. The circuit element forming region B may be further divided into a zener diode forming region B1(zener diode forming region), a resistor forming region B2(resistor forming region), and a conventional diode forming region B3(normal diode forming region).

In the present embodiment, the resistor formation region B2 is located between the zener diode formation region B1 and the conventional diode formation region B3, the zener diode formation region B1 is farther from the transistor formation region a than the resistor formation region B2, and the conventional diode formation region B3 is closer to the transistor formation region a than the resistor formation region B2, but the invention is not limited thereto.

As shown in fig. 1B, the step S120 includes: a plurality of trenches 13 are concavely formed on the epitaxial layer 12, and the plurality of trenches 13 are all located in the transistor forming region a. The plurality of trenches 13 may be formed by etching, for example. More specifically, the trenches 13 are recessed along the length direction D on a side surface of the epitaxial layer 12 opposite to the substrate layer 11, and bottoms of the trenches 13 are not in contact with the substrate layer 11 and are spaced from the substrate layer 11 by a distance. In another aspect, the plurality of trenches 13 are recessed from the top surface 101 of the substrate structure 1 and do not contact the base layer 11 of the substrate structure 1.

In the present embodiment, a trench depth of each trench 13 is usually between 0.5 microns and 3 microns, and preferably between 1 micron and 2 microns, but the present invention is not limited thereto.

It should be noted that the trenches 13 are described with reference to the trenches 13 at different positions in the epitaxial layer 12 in a cross-sectional view. If viewed as a whole, the grooves 13 may be connected or separated, and the present invention is not limited thereto.

As shown in fig. 1C, the step S130 includes: an insulating layer 2 (or oxide layer) is extendedly formed on a surface of the epitaxial layer 12 opposite to the base layer 11 (i.e. the top surface 101 of the substrate structure 1) and on inner walls of the trenches 13. The insulating layer 2 may be formed by a Low Temperature Oxidation (LTO) process or a thermal oxidation (thermal oxidation) process, for example, but the invention is not limited thereto.

In the present embodiment, the thickness of the insulating layer 2 is approximately between 5 nm and 100 nm, and the material of the insulating layer 2 may be, for example, a silicon compound. For example, the material of the insulating layer 2 may be silicon dioxide, but the invention is not limited thereto.

Furthermore, the portion of the insulating layer 2 located on the inner wall of each trench 13 is defined as a trench insulating layer 21 (or trench oxide layer), and each trench insulating layer 21 surrounds and forms a groove 22. That is, the trench insulating layers 21 are formed on the inner walls of the trenches 13, respectively, and the trench insulating layers 21 surround and form the grooves 22, respectively. In addition, the remaining portion of the insulating layer 2 (i.e., the portion of the insulating layer 2 on the top surface 101 of the epitaxial layer 12) is defined as a passivation insulating layer 23 (or referred to as a passivation oxide layer).

The trench insulating layers 21 are all located in the transistor forming region a, and the cover insulating layer 23 is extendedly located in the transistor forming region a and the circuit element forming region B.

As shown in fig. 1D, the step S140 includes: a polysilicon material M is formed on a surface of the insulating layer 2 opposite to the epitaxial layer 12, so that the polysilicon material M covers the insulating cover layer 23 and fills the plurality of grooves 22 surrounded by the plurality of trench insulating layers 21. It is composed ofThe polysilicon material M may be, for example, made of Silane (SiH)₄) Formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process, but the present invention is not limited thereto.

In the present embodiment, the polysilicon material M is deposited on the insulating layer 2 to a certain thickness, so that the outer surface of the polysilicon material M (i.e., the surface of the polysilicon material M opposite to the substrate layer 11) is a flat surface. More specifically, the portions of the outer surface of the polysilicon material M above the plurality of grooves 22 and above the insulating cover layer 23 are substantially flush with each other, but the present invention is not limited thereto.

As shown in fig. 1E, the step S150 includes: a photolithography operation (lithography operation) and an etching operation (etching operation) are performed on the polysilicon material M to remove a portion of the polysilicon material M, so that a plurality of polysilicon filling structures M1(poly-silicon filled structures) are respectively formed in the plurality of grooves 22 surrounded by the plurality of trench insulating layers 21, and a plurality of polysilicon block structures M2(poly-silicon block structures) are formed on the insulating cover layer 23.

In the present embodiment, a plurality of polysilicon filling structures M1 are respectively formed in the plurality of recesses 22 surrounded by the plurality of trench insulating layers 21. Accordingly, the polysilicon fill structures M1 are located in the transistor forming region a, as are the trench insulating layers 21.

Further, after the etching operation, the exposed surface of the polysilicon filling structures M1 (i.e., the top surface of the polysilicon filling structure M1 in fig. 1E) is lower than the outer surface of the insulating cover layer 23 (i.e., the side surface of the insulating cover layer 23 opposite to the epitaxial layer 12 in fig. 1E), but the invention is not limited thereto.

Furthermore, a plurality of polysilicon blocks M2 are formed on a surface of the insulating layer 23 opposite to the epitaxial layer 12, and a plurality of polysilicon blocks M2 are located in the circuit device formation region B to be fabricated into different circuit devices (such as zener diode, resistor, and conventional diode) in the subsequent process flow.

Further, a plurality of the polysilicon block structures M2 are spaced apart from each other on the insulating cover layer 23. In the present embodiment, the number of the plurality of polysilicon block structures M2 is three, and three polysilicon block structures M2 are respectively located in the zener diode forming region B1, the resistor forming region B2, and the conventional diode forming region B3 of the circuit element forming region B.

It should be noted that, in the present embodiment, the raw materials M of the polysilicon filling structure M1 and the polysilicon block structure M2 are formed in the same polysilicon deposition process, but the present invention is not limited thereto. The source material M of the polysilicon fill structure M1 and the polysilicon block structure M2 may be formed by a plurality of polysilicon deposition processes (e.g., 2, 3, or more) according to the process requirements.

As shown in fig. 1F, the step S160 includes: an ion implantation process is performed to form a plurality of polysilicon filling structures M1 located in the transistor forming region a into a plurality of gate filling structures 31 (or doped polysilicon filling structures), respectively, a portion of the epitaxial layer 12 located between any two adjacent trenches 13 is formed into a body doping structure 32(matrix doped structure), the polysilicon bulk structure M2 located in the zener diode forming region B1 is formed into a zener diode doping structure 41, the polysilicon bulk structure M2 located in the resistor forming region B2 is formed into a resistor doping structure 51, and the polysilicon bulk structure M2 located in the conventional diode forming region B3 is formed into a conventional diode doping structure 61. It should be noted that, in the present embodiment, the ion implantation process may, for example, include a plurality of ion implantation processes (e.g., a P-type ion implantation process and an N-type ion implantation process) for performing different doping (e.g., P-type doping or N-type doping) on the polysilicon material and the epitaxial layer.

Further, each of the gate filling structures 31 may be, for example, one of a P-type doped semiconductor and an N-type doped semiconductor, which is not limited by the present invention.

Each of the doped base structures 32 includes a P-type doped region 32P and an N-type doped region 32N formed on the P-type doped region 32P. That is, in each of the body doping structures 32, the N-type doping region 32N and the P-type doping region 32P are stacked on top of each other. The P-type doped region 32P is located at the lower side and abuts against the epitaxial layer 12, and the N-type doped region 32N is located at the upper side and abuts against the insulating cover layer 23. It should be noted that the conductive type of the P-type doped region 32P is different from the conductive type of the substrate layer 11 (N + -type doped semiconductor) and the conductive type of the epitaxial layer 12 (N-type doped semiconductor). That is, the P-type doped regions 32P in the present embodiment are P-type doped semiconductors, and the implanted ion species may be, for example, boron (B +), but the invention is not limited thereto.

The zener diode doped structure 41 includes a P-type doped region 41P and an N-type doped region 41N located at one side of the P-type doped region 41P (e.g., the left side of the P-type doped region 41P in fig. 1F). That is, in the zener diode doped structure 41, the N-type doped region 41N and the P-type doped region 41P are arranged right and left and connected to each other. Furthermore, the N-type doped region 41N and the P-type doped region 41P are formed on the insulating cover layer 23 and contact the insulating cover layer 23.

The resistor doped structure 51 may be, for example, one of a P-type doped semiconductor and an N-type doped semiconductor, and the present embodiment is preferably a P-type doped semiconductor, but the present invention is not limited thereto. Furthermore, the doping concentration of the resistor doping structure 51 is low relative to the doping concentration of the zener diode doping structure 41 or the doping concentration of the conventional diode doping structure 61, so as to generate the effect of resistance.

The conventional diode doping structure 61 is similar to the zener diode doping structure 41, and includes a P-type doping region 61P and an N-type doping region 61N located at one side of the P-type doping region 61P (e.g., the left side of the P-type doping region 61P in fig. 1F). That is, in the conventional diode doping structure 61, the N-type doping region 61N and the P-type doping region 61P are arranged left and right and connected to each other. Furthermore, the N-type doped region 61N and the P-type doped region 61P are formed on the insulating cover layer 23 and contact the insulating cover layer 23.

It should be noted that the ion species used in the ion implantation process described herein may be, for example: boron ion (B)⁺) Zinc ion (Zn)²⁺) Fluorine ion (F)^-) Nitrogen ion (N)^-) Oxygen ion (O)^2-) Carbon ion (C)⁴⁺) Argon ion (Ar)⁺) Phosphorus ion (P)⁺) Arsenic ion (As)⁺) Or antimony ion (Sb)²⁺)。

As shown in fig. 1G, the step S170 includes: an Inter Layer Dielectric (ILD) layer 7 is formed on the substrate structure 1 such that the insulating layer 2, the gate fill structures 31, the body doping structure 32, the zener diode doping structure 41, the resistor doping structure 51, and the regular diode doping structure 61 are covered by the dielectric layer 7.

The dielectric layer 7 may be formed by a chemical vapor deposition process, for example, but the invention is not limited thereto. For example, the dielectric layer 7 may also be formed by a physical vapor deposition process or other suitable deposition process. Furthermore, the material of the dielectric layer 7 may be, for example, a silicon compound or other dielectric materials.

Further, the outer surface of the dielectric layer 7 may be planarized by, for example, a Chemical Mechanical Polishing (CMP) process, but the present invention is not limited thereto.

As shown in fig. 1H, the step S180 includes: a metallization process is performed to form a source metal structure 33(source metal), a zener diode metal structure 42, a resistor metal structure 52, and a regular diode metal structure 62 on the dielectric layer 7, and a drain metal structure 34(drain metal) on the bottom surface 102 of the substrate structure 1, respectively. It should be noted that the "metal structure" mentioned herein may be formed by deposition, for example, and the "metal structure" may be a unitary structure formed by aluminum/silicon/copper alloy, but it is not limited thereto in practical application.

The source metal structure 33 is located in the transistor forming region a. The source metal structure 33 is formed on a surface of the dielectric layer 7 opposite to the substrate layer 11 and partially penetrates through the dielectric layer 7 to be electrically connected to at least one of the plurality of bulk doped structures 32.

In the present embodiment, the source metal structure 33 includes: one source metal conductive portion 331 and two source metal contact plugs 332 connected to the source metal conductive portion 331. Wherein, the source metal conductive part 331 is formed on a side surface of the dielectric layer 7 opposite to the base layer 11. The two source metal contact plugs 332 are disposed at intervals and respectively penetrate through the dielectric layer 7, so that the source metal conductive portion 331 can be electrically connected to two adjacent body doped structures 32 of the plurality of body doped structures 32 through the two source metal contact plugs 332.

In addition, the width of each of the source metal contact plugs 332 is smaller than the width of the body doped structure 32 connected thereto, and each of the source metal contact plugs 332 passes through the N-type doped region 32N in the body doped structure 32 corresponding thereto and partially extends into the P-type doped region 32P. Thereby, the two source metal contact plugs 332 are disposed at an equipotential compared to the two body doped structures 32 electrically connected thereto.

The drain metal structure 34 is formed on the bottom surface 102 of the substrate structure 1. That is, the drain metal structure 34 is formed on a surface of the substrate layer 11 opposite to the epitaxial layer 12. In the present embodiment, the drain metal structure 34 covers the entire bottom surface 102 of the substrate structure 1, but the present invention is not limited thereto.

According to the above configuration, as shown in fig. 2, the source metal structure 33 can be electrically connected to a source wire 33L to define a source s (source) of the mosfet. The drain metal structure 34 can be electrically connected to a drain wire 34L to define a drain d (drain) of the mosfet. Furthermore, one of the gate fill structures 31 (e.g., the gate fill structure on the far right in fig. 2) of the plurality of gate fill structures 31 can be used to electrically connect to a gate wire 31L to define a gate g (gate) of the mosfet. The above-mentioned components (e.g., the source metal structure 33, the drain metal structure 34, the gate filling structure 31, etc.) in the transistor forming region a can form a mosfet 3, and the equivalent circuit thereof is shown in fig. 3.

As shown in fig. 1H, the zener diode metal structure 42, the resistor metal structure 52, and the conventional diode metal structure 62 are all located in the circuit device formation region B.

The zener diode metal structure 42 is located in the zener diode forming region B1, and the zener diode metal structure 42 is formed on a side surface of the dielectric layer 7 opposite to the base layer 11 and partially penetrates through the dielectric layer 7 to be electrically connected to the zener diode doped structure 41. The zener diode metal structure 42 and the zener diode doped structure 41 can be matched with each other to form a zener diode 4 (Vz). The zener diode 4 is configured to receive a reverse bias voltage, and the zener diode 4 can withstand a voltage between 5 volts and 6 volts.

In the present embodiment, the zener diode metal structure 42 includes two metal pins 421. The two metal pins 421 of the zener diode metal structure 42 are disposed at an interval and partially penetrate the dielectric layer 7 to be electrically connected to the N-type doped region 41N and the P-type doped region 41P of the zener diode doped structure 41, respectively, so as to form the zener diode 4. In the zener diode 4, the metal pin 421 connected to the P-type doped region 41P is "lower" than the metal pin 421 connected to the N-type doped region 41N, so as to generate a "reverse bias" when the power device is powered on.

The resistor metal structure 52 is located in the resistor forming region B2, and the resistor metal structure 52 is formed on a surface of the dielectric layer 7 opposite to the substrate layer 11 and partially penetrates through the dielectric layer 7 to be electrically connected to the resistor doped structure 51. The resistor metal structure 52 and the resistor doped structure 51 can be matched to form a resistor 5(resistor, R).

In the present embodiment, the resistor metal structure 52 includes two metal pins 521. The two metal legs 521 of the resistor metal structure 52 are spaced apart from each other and partially penetrate the dielectric layer 7 to electrically connect to the resistor doped structure 51 (e.g., P-type doped semiconductor). The doping concentration of the resistor doping structure 51 is lower than that of the zener diode doping structure 41 and lower than that of the conventional diode doping structure 61, so as to generate a resistance effect when the power element is powered on.

The conventional diode metal structure 62 is located in the conventional diode forming region B3, and the conventional diode metal structure 62 is formed on a side surface of the dielectric layer 7 opposite to the base layer 11 and partially penetrates through the dielectric layer 7 to be electrically connected to the conventional diode doping structure 61. The conventional diode metal structure 62 and the conventional diode doping structure 61 can be matched with each other to form a conventional diode 6 (V)_D). The conventional diode 6 is configured to receive a forward bias voltage, and the conventional diode 6 can withstand a voltage between 0 volts and 0.7 volts.

In the present embodiment, the conventional diode metal structure 62 includes two metal pins 621. The two metal pins 621 of the conventional diode metal structure 62 are disposed at an interval and partially penetrate the dielectric layer 7 to be electrically connected to the N-type doped region 61N and the P-type doped region 61P of the conventional diode doped structure 61, respectively, so as to form the conventional diode 6. In the conventional diode 6, the metal pin 621 connected to the P-type doped region 61P is at a higher potential than the metal pin 621 connected to the N-type doped region 61N, so as to generate a forward bias voltage when the power device is powered on.

It should be noted that, in the conventional diode 6, the metal pin 621 connected to the P-type doped region 61P may be electrically connected to one of the gate fill structures 31 (e.g., the rightmost gate fill structure in fig. 2) in the plurality of gate fill structures 31 through a conductive wire (not shown). Furthermore, the metal pin 621 connected to the N-type doped region 61N may be electrically connected to the source metal structure 33 of the mosfet 3 through a conductive wire (not shown), but the invention is not limited thereto.

It should be noted that, in the present embodiment, the N-type doped region 32N of the body doped structure 32, the N-type doped region 41N of the zener diode 4, and the N-type doped region 61N of the conventional diode are completed in the same ion implantation process, but the invention is not limited thereto.

After the above steps S110 to S180 are performed, the composite power device 100 (or trench power device) shown in fig. 1H and fig. 2 can be completed. An equivalent circuit diagram of the composite power element 100 of the present embodiment is shown in fig. 3. It should be emphasized that, in practice, the various steps are not to be excluded to be replaced by reasonable variants.

It should be emphasized that the above steps are described in terms of cross-sectional views, and that the implementation of the present invention in various designs and layouts is not excluded on the premise of meeting the above steps. In other words, the composite power device 100 of the present embodiment may have different layout types when viewed from the top.

With the above arrangement, the method for manufacturing a composite power device according to the embodiments of the present invention can integrate the formation of different electronic devices (e.g., zener diode, resistor, conventional diode) into the process of the mosfet (especially the process after depositing polysilicon) to form the required power device, without adding additional processes, thereby simplifying the process complexity.

The above is a description of the method of manufacturing the composite power element according to the embodiment of the present invention, and the following is a description of a specific structure of the composite power element according to the embodiment. It should be noted that, although the composite power element of the present embodiment is manufactured by the above manufacturing method, the present invention is not limited thereto. That is, the composite power element of the present invention may be manufactured by other manufacturing methods.

As shown in fig. 1H and with reference to fig. 2 and fig. 3, the present embodiment further discloses a composite power device 100, which includes: a substrate structure 1, an insulating layer 2, a dielectric layer 7, a metal oxide semiconductor field effect transistor 3(MOSFET), a Zener diode 4 (V)_Z) A resistor 5(R), and a conventional diode 6 (V)_D)。

The substrate structure 1 includes a base layer 11 and an epitaxial layer 12 formed on the base layer 11. The epitaxial layer 12 is recessed with at least one trench 13, the substrate structure 1 is defined with a transistor forming region a and a circuit element forming region B adjacent to the transistor forming region a along a length direction D thereof, and the trench 13 is located in the transistor forming region a.

The insulating layer 2 is formed on the epitaxial layer 12 and on the inner wall of the trench 13 in an extending manner. The portion of the insulating layer 2 located on the inner wall of the trench 13 is defined as a trench insulating layer 21, which surrounds and forms a groove 22, and the rest of the insulating layer 2 is defined as a covering insulating layer 23. Further, the dielectric layer 7 is formed on the insulating layer 2.

The metal oxide semiconductor field effect transistor 3 is located in the transistor forming region a and includes: a gate filling structure 31, a body doping structure 32, a source metal structure 33, and a drain metal structure 34. Wherein, the gate filling structure 31 is formed in the recess 22 of the trench insulation layer 21. The substrate doping structure 32 is formed in the epitaxial layer 12 and located in a peripheral region of the trench 13. The source metal structure 33 is formed on the dielectric layer 7 and partially penetrates through the dielectric layer 7 to electrically connect the body-doped structure 32. The drain metal structure 34 is formed on a bottom surface of the substrate layer 11.

The zener diode 4 is located in the circuit element formation region B, and includes: a zener diode doped structure 41 and a zener diode metal structure 42. Wherein, the zener diode doped structure 41 is formed on the covering insulating layer 23 and covered by the dielectric layer 7. The zener diode doped structure 41 includes a P-type doped region 41P and an N-type doped region 41N connected to each other. The zener diode metal structure 42 is formed on the dielectric layer 7 and partially penetrates through the dielectric layer 7 to be electrically connected to the P-type doped region 41P and the N-type doped region 41N of the zener diode doped structure 41. The zener diode 4 is configured to receive a reverse bias when the composite power device 100 is powered on.

The resistor 5 is located in the circuit element forming region B and is disposed at a distance from the zener diode 4, and the resistor 5 includes: a resistor doped structure 51 and a resistor metal structure 52. Wherein the resistor doped structure 51 is formed on the cover insulating layer 23 and covered by the dielectric layer 7. The resistor doping structure 51 is a P-type doped semiconductor or an N-type doped semiconductor. The resistor metal structure 52 is formed on the dielectric layer and partially penetrates the dielectric layer 7 to be electrically connected to the resistor doped structure 51, and the resistor 5 is configured to generate a resistance when the composite power device 100 is powered on.

The conventional diode 6 is located in the circuit element forming region B and is disposed at a distance from the zener diode 4, and the conventional diode 6 includes: a conventional diode doping structure 61 and a conventional diode metal structure 62. Wherein the conventional diode doping structure 61 is formed on the covering insulating layer 23 and covered by the dielectric layer 7. The conventional diode doping structure 61 includes a P-type doping region 61P and an N-type doping region 61N connected to each other. The conventional diode metal structure 62 is formed on the dielectric layer 7 and partially penetrates through the dielectric layer 7 to be electrically connected to the P-type doped region 61P and the N-type doped region 61N of the conventional diode doped structure 61. Wherein the conventional diode is configured to receive a forward bias. Wherein, the conventional diode 6 is adjacently arranged on the metal oxide semiconductor field effect transistor 3.

[ second embodiment ]

Referring to fig. 4 and 5, a composite power device 100' is also provided according to a second embodiment of the present invention. Fig. 4 is a partial schematic view of a composite power element according to a second embodiment of the present invention, and fig. 5 is an equivalent circuit diagram of a composite power element according to a second embodiment of the present invention.

The structure of the composite power device 100 'of the second embodiment of the present invention is substantially the same as that of the first embodiment, except that the composite power device 100' of the present embodiment has a plurality of conventional diodes 6 (V) connected in series with each other_D1To V_DN)。

As shown in fig. 4, more specifically, in the present embodiment, the number of the conventional diodes 6 is plural, and a plurality of the conventional diodes 6 (V) are provided_D1To V_DN) Are disposed in series with each other on the insulating cover layer 23 and are located in the conventional diode forming region B3 of the circuit element forming region B. The number of the plurality of the conventional diodes 6 may be, for example, two or more.

More specifically, a plurality of the conventional diodes 6 connected in series with each other are arranged in a manner of "N-type doped region/P-type doped region/N-type doped region/P-type doped region …" being staggered with each other. In any two adjacent conventional diodes 6 connected in series, the metal pin 621 of one of the conventional diodes 6 connected to the P-type doped region 61P is directly contacted and electrically connected to the metal pin 621 of the other of the conventional diodes 6 connected to the N-type doped region 61N. Furthermore, the conventional diode doping structure 61 of one of the conventional diodes 6 is not directly contacted with the conventional diode doping structure 61 of the other of the conventional diodes 6.

Further, as shown in fig. 4, among a plurality of the conventional diodes 6 connected in series with each other, a first conventional diode V_D1(e.g. the rightmost conventional diode V in FIG. 4_D1) The metal pin 621 connected to the P-type doped region 61P may be electrically connected to one of the gate fill structures 31 (such as the gate fill structure on the rightmost side in fig. 2) of the gate fill structures 31 in the mosfet 3 through a conductive wire (not shown). Furthermore, the Nth conventional diode V_DNThe metal pin 621 (the leftmost conventional diode 6 in FIG. 4) connected to the N-type doped region 61N can pass throughA conductive wire (not shown) electrically connected to the source metal structure 33 of the mosfet 3, but the present invention is not limited thereto.

As shown in fig. 5, since the composite type power element 100' of the present embodiment has a plurality of conventional diodes 6 (V) connected in series with each other_D1To V_DN) Therefore, V can be changed by adjusting the number of the conventional diodes 6_GSFurther, the driving voltage of the composite Power device 100' is controlled to achieve the feasibility of driving various Power field effect transistors Power MOSFETs.

Accordingly, the concept of the structural design can arbitrarily integrate various Power field effect transistor Power MOSFETs with different voltages/currents according to the application requirements of the terminal product. Wherein the output voltage may be, for example, V_OUT＝V_G-V_D＝V_Z-(V_D1+V_D2+…V_DN)。

[ advantageous effects of the embodiments ]

The beneficial effects of the present invention are that the composite power device provided by the embodiments of the present invention can integrate the formation of different electronic devices (such as zener diode, resistor, and conventional diode) into the process of the mosfet (especially the process after depositing polysilicon) to form the required power device, without adding additional processes, thereby simplifying the process complexity and reducing the volume of the terminal product.

Further, since the composite type power element of the present embodiment can be designed with a plurality of conventional diodes (V) connected in series with each other_D1To V_DN) Therefore, V can be changed by adjusting the number of the conventional diodes_GSAnd further, the driving voltage of the composite Power element is controlled, so that the feasibility of driving various field effect transistors (Power MOSFETs) with different Power is achieved.

In addition, the structural design of the composite power device of this embodiment can reduce the number of electronic devices required to be placed on the system circuit board, because some electronic devices are integrated into the integrated device process of the present invention, the size of the terminal product can be reduced.

The above disclosure is only a preferred and practical embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention, so that all the modifications of the equivalent technology made by the disclosure and drawings are included in the scope of the claims of the present invention.

Claims

1. A composite power element, characterized by comprising:

a substrate structure including a base layer and an epitaxial layer formed on the base layer; the epitaxial layer is concavely provided with at least one groove, the substrate structure is defined with a transistor forming area and a circuit element forming area adjacent to the transistor forming area along the length direction of the substrate structure, and the groove is positioned in the transistor forming area;

an insulating layer formed on the epitaxial layer and the inner wall of the trench in an extending manner; the part of the insulating layer, which is positioned on the inner wall of the groove, is defined as a groove insulating layer which surrounds and forms a groove, and the rest part of the insulating layer is defined as a covering insulating layer;

a dielectric layer formed on the insulating layer;

a metal oxide semiconductor field effect transistor located in the transistor forming region and comprising:

a gate filling structure formed in the groove of the trench insulation layer;

a substrate doping structure formed in the epitaxial layer and located in the peripheral region of the trench;

a source metal structure formed on the dielectric layer and partially penetrating the dielectric layer to electrically connect the substrate doped structure; and

a drain metal structure formed on a bottom surface of the substrate layer; and

a zener diode located in the circuit element formation region and including:

a Zener diode doping structure formed on the coating insulating layer and covered by the dielectric layer; the Zener diode doping structure comprises a P-type doping area and an N-type doping area which are mutually connected; and

a Zener diode metal structure formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region of the Zener diode doped structure; wherein the Zener diode is configured to receive a reverse bias voltage when the composite power device is energized.

2. The composite power device of claim 1, wherein the Zener diode metal structure comprises two metal pins spaced apart from each other and partially penetrating the dielectric layer to electrically connect to the N-doped region and the P-doped region of the Zener diode doped structure, respectively; when the composite power element is electrified, the potential of the metal pin connected with the P-type doped region is lower than that of the metal pin connected with the N-type doped region, so that the reverse bias voltage is generated.

3. The composite power element according to claim 1, characterized by further comprising:

a resistor located in the circuit element forming region and disposed at a distance from the zener diode, and the resistor comprising:

a resistor doped structure formed on the insulating cover layer and covered by the dielectric layer; the resistor doping structure is a P-type doping semiconductor or an N-type doping semiconductor; and

a resistor metal structure formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the resistor doping structure, wherein the resistor is configured to generate a resistance when the composite power device is powered on.

4. The composite power element according to claim 3, characterized by further comprising:

a conventional diode located in the circuit element formation region and disposed at a distance from the zener diode, and the conventional diode includes:

a conventional diode doping structure formed on the cover insulating layer and covered by the dielectric layer; the conventional diode doping structure comprises a P-type doping area and an N-type doping area which are mutually connected; and

a conventional diode metal structure formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region of the conventional diode doping structure; wherein the conventional diode is configured to receive a forward bias voltage;

wherein the conventional diode is disposed adjacent to the MOSFET.

5. The composite power device of claim 4, wherein the conventional diode metal structure comprises two metal pins, the two metal pins are spaced apart from each other and partially penetrate the dielectric layer to electrically connect to the N-type doped region and the P-type doped region of the conventional diode doped structure, respectively; when the composite power element is electrified, the potential of the metal pin connected to the P-type doped region is higher than that of the metal pin connected to the N-type doped region, so that the forward bias voltage is generated.

6. The composite power device of claim 5 wherein in said conventional diode, said metal leg connected to said P-type doped region is configured to be electrically connected to said gate fill structure of said MOSFET by a wire, and said metal leg connected to said N-type doped region is configured to be electrically connected to said source metal structure of said MOSFET by a wire.

7. The composite power element according to claim 5, wherein the number of the conventional diodes is plural, and the plural conventional diodes are disposed in series with each other on the coating insulating layer.

8. The composite power device of claim 7, wherein in any two adjacent conventional diodes connected in series with each other, the metal pin of one of the conventional diodes connected to the P-type doped region is directly contacted and electrically connected to the metal pin of the other of the conventional diodes connected to the N-type doped region; and wherein the conventional diode doping structure of one of the conventional diodes is not in direct contact with the conventional diode doping structure of the other of the conventional diodes.

9. The composite power device of claim 7 wherein, among a plurality of said conventional diodes connected in series, the metal leg of the first conventional diode connected to said P-type doped region is electrically connected to said gate fill structure of said MOSFET by a wire, and the metal leg of the last conventional diode connected to said N-type doped region is electrically connected to said source metal structure of said MOSFET by a wire.