CN211579936U - A kind of amplifier fast power modulation circuit - Google Patents

Abstract

The utility model relates to an amplifier fast power modulation circuit, comprising a common source transistor, the source of the common source transistor is grounded, the gate of the common source transistor is connected to a bias voltage through a bias resistor, and the drain of the common source transistor is connected to a bias voltage. The power supply terminal is connected, and the gate of the common source transistor is coupled to the radio frequency signal input terminal. The amplifier circuit according to the present invention further comprises a power supply modulation switch, the control port of the power supply modulation switch is connected to the modulation circuit, and the output lower port of the power supply modulation switch Connected to the bias voltage, the output upper port of the power modulation switch is coupled to the radio frequency signal input terminal.

Description

A kind of amplifier fast power modulation circuit

technical field

The utility model relates to the field of radio frequency microwave communication, in particular to an amplifier fast power modulation circuit.

Background technique

In radio frequency microwave systems such as wireless communication and radar, amplifiers are widely used in various transceiver links to amplify weak signals. In a time-division communication system, the receiving and transmitting modes need to be switched continuously, so the system requires a fast switching time for the transceiver link. As a vital active device in the transceiver chain, the switching time of the amplifier will directly determine the transceiver. The switching time of the link. Therefore, there is a need to invent an amplifier circuit with fast power supply modulation.

As a common implementation of fast power modulation, drain power modulation is widely used in III-V family amplifiers. The schematic diagram is shown in Figure 1. The main problem is that it is not suitable for use in high supply voltage systems. Because, in a high power supply voltage system, when the switch tube P1 is turned on, the gate-source voltage of the P1 tube will be too large, which will affect the life of the P1 tube, and even directly lead to the breakdown of the gate-source of the P1 tube.

Traditional gate power modulation is another common power modulation implementation. Its schematic block diagram is shown in Figure 2. The amplifier is turned on and off by controlling the gate bias voltage VBIAS_N1 of the amplifier tube N1. The switching time depends on Rg*Cpar, where Cpar is the parasitic capacitance on the gate node of the common source MOS transistor. However, because the system often requires the amplifier to have low noise, the value of Rg is relatively large. Therefore, the switching time of such a traditional gate power modulation amplifier will be very long, and its switching time is shown in Figure 3.

Utility model content

In order to meet the requirements of various time-division communication systems on the switching time of the transceiver link, without affecting the performance of the existing amplifier, and being able to adapt to the high power supply voltage requirements, it is necessary to propose a new type of fast power supply modulation applied to the amplifier. Circuit configuration.

According to an aspect of the present invention, an amplifier fast power modulation circuit is provided, which includes a common source transistor, the source of the common source transistor is grounded, and the gate of the common source transistor is connected to a bias voltage through a bias resistor, The drain of the common source transistor is connected to the power supply terminal, and the gate of the common source transistor is coupled to the radio frequency signal input terminal, and also includes a power supply modulation switch, the control port of the power supply modulation switch is connected to the modulation circuit, the The upper output port of the power modulation switch is coupled to the input terminal of the radio frequency signal, and the lower output port of the power modulation switch is connected to a bias voltage, so that the two output ports of the power modulation switch are connected in parallel with the bias resistor .

According to another aspect of the present invention, the fast power modulation circuit, wherein the power modulation switch is an NMOS transistor or a PMOS transistor.

The fast power modulation circuit according to another aspect of the present invention further includes a load circuit, wherein the drain of the common source transistor is connected to the power supply terminal through the load circuit.

The fast power modulation circuit according to another aspect of the present invention further includes a feedback circuit, and the source of the common source transistor is grounded through the feedback circuit.

According to another aspect of the present invention, the fast power modulation circuit further includes a bias capacitor, and the bias resistor and the bias capacitor are connected in series and then grounded.

According to another aspect of the present invention, the fast power modulation circuit, wherein the modulation circuit includes a series-connected first inverter, an RC delay circuit, a NOR gate circuit and an odd number of second inverters.

According to another aspect of the present invention, the fast power modulation circuit, wherein the modulation circuit further comprises an odd number of third inverters connected in series for generating an enabling signal of the first bias voltage.

Compared with the gate voltage establishment and release time of the traditional gate power modulation amplifier, the fast power modulation circuit according to the present invention has a faster gate voltage establishment and release time, and is not limited by the power supply voltage of the amplifier, and can be applied to high power supply voltages system.

Description of drawings

Figure 1 is a schematic diagram of a common drain power modulation.

FIG. 2 is a schematic diagram of the principle of conventional gate power modulation.

FIG. 3 is a schematic diagram of switching time of conventional gate power modulation in FIG. 2 .

FIG. 4(A) is a schematic diagram of an amplifier fast power modulation circuit according to an embodiment of the present invention.

4(B) and 4(C) are schematic diagrams of specific embodiments of a power modulation switch.

FIG. 5 is a schematic diagram of a control timing of the circuit configuration of FIG. 4(A).

FIG. 6 is a schematic diagram of a logic circuit structure implementing the circuit structure of the control sequence of FIG. 5 .

FIG. 7 is a timing chart of the logic circuit configuration of FIG. 6 .

FIG. 8 is a specific implementation of a bias voltage enabling circuit according to an embodiment of the present invention.

FIG. 9 is an enable timing diagram of the bias voltage according to one embodiment of the present invention.

FIG. 10 is a schematic diagram showing the comparison of the set-up and release time of the bias voltage of the circuit of the present invention and the conventional gate power modulation amplifier.

Detailed ways

The present utility model will be further described below with reference to specific embodiments and accompanying drawings.

FIG. 4(A) is a schematic diagram of an amplifier fast power modulation circuit according to an embodiment of the present invention. As shown in FIG. 4(A), the power modulation circuit according to the present invention includes a common source transistor N1, wherein the source of the common source transistor N1 is grounded, the gate is connected to the bias voltage VBIAS_N1 through the bias resistor Rg, and the drain is connected to the power supply terminal, and the gate of the common source transistor N1 is coupled to the radio frequency signal input terminal RFIN.

On the basis of the traditional gate power modulation structure shown in FIG. 2 , the present invention adds a power modulation switch SW to realize the fast power modulation of the amplifier. In terms of circuit implementation, the control port of the power modulation switch SW is connected to the modulation circuit, the lower output port is connected to the bias voltage VBIAS_N1, and the upper output port is coupled to the RF signal input port, so that the upper and lower output ports of the power modulation switch SW are connected to the bias resistor. Rg is connected in parallel, as shown in Figure 4(A), when the power modulation switch SW is closed, the power modulation switch SW is equivalent to a low-value resistor, which forms a voltage from the bias voltage VBIAS_N1 to the gate of the common source transistor N1 Low resistance channel for voltage Vg1. When the amplifier is switched between on and off, the gate voltage Vg1 of the common source transistor N1 can be quickly established or released through this low-impedance path, thereby realizing the fast switching of the amplifier.

According to an embodiment of the present invention, the power modulation switch SW may be an NMOS transistor as shown in FIG. 4(B) or a PMOS transistor as shown in FIG. 4(C). Those skilled in the art can understand that the power modulation switch SW is not limited to the specific embodiments shown in FIG. 4(B) and FIG. 4(C).

Further, the fast power modulation function proposed by the present invention needs to be realized through the control sequence shown in FIG. 5 , and its specific working principle is as follows: when the amplifier enable signal EN_AMP changes from low to high, the control signal SW_CTR of the power modulation switch will remain high for a period of time, during which time the power modulation switch is always closed, providing a low resistance channel through which the bias voltage VBIAS_N1 can quickly charge the gate parasitic capacitance Cpar of transistor N1 , so as to realize the rapid establishment of the gate voltage Vg1 of the transistor N1; when the gate voltage Vg1 is established, the control signal SW_CTR of the power modulation switch becomes low level, and the power modulation switch is turned off. At this time, the gate voltage Vg1 of the transistor N1 Maintained by the high resistance channel Rg, the amplifier returns to the normal working mode; when the amplifier enable signal EN_AMP changes from high to low, the control signal SW_CTR of the power modulation switch SW will change from low to high, thus closing the power modulation switch SW, the low resistance The channel is established, thereby realizing the rapid release of the gate voltage Vg1 of the transistor N1; then, the gate control signal SW_CTR of the power modulation switch SW will continue to remain high until the next switching cycle. Thus, the fast power supply modulation circuit of the present invention applied to the amplifier is realized.

The power modulation circuit according to the above-mentioned embodiment of the present invention has fast gate voltage establishment and release time, as shown in FIG. In addition, the power modulation circuit according to the embodiment of the present invention is not limited by the power supply voltage of the amplifier, and can be applied to a high power supply voltage system.

Another aspect of the present invention provides a circuit structure for realizing the control sequence shown in FIG. 5 , which is specifically shown in FIG. 6 . Among them, 601, 604, 605, and 606 are inverters, 602 is an RC delay circuit, and 603 is a NOR gate circuit.

Further, the logic circuit shown in FIG. 6 further includes inverters 607 , 608 and 609 , and the logic circuit shown in FIG. 6 can also generate the EN_VBIAS_N1 signal for generating the gate bias voltage VBIAS_N1 of the common source transistor N1 . The logic circuit shown in Figure 6 will produce the waveform shown in Figure 7.

Further, a specific implementation form of the enabling circuit of the gate bias voltage VBIAS_N1 of the common source transistor N1 is shown in FIG. 8 , wherein the control signal EN_VBIAS_N1 comes from the logic circuit shown in FIG. 6 , and the enabling circuit shown in FIG. 8 The circuit will produce the timing shown in Figure 9.

The embodiments of the present utility model are described in detail above in conjunction with the accompanying drawings, but the present utility model is not limited to the above-mentioned embodiments, within the scope of knowledge possessed by those of ordinary skill in the art, without departing from the purpose and spirit of the present utility model. The various changes made below should all belong to the scope of coverage of the patent for this utility model.

For example, in some embodiments, the transistor may be implemented by a field effect transistor (FET), specifically including a junction field effect transistor (JFET), a high electron mobility transistor (High Electron Mobility Transistor, HEMT), metal semiconductor field effect transistor (Metal Semiconductor FET, MESFET) metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and so on.

In some embodiments, an N-type field effect transistor (N Metal-Oxide-Semiconductor Field-Effect Transistor, NMOS FET) or a P-type field effect transistor (P Metal-Oxide-Semiconductor Field-Effect Transistor, PMOS FET) is used to achieve the above transistor.

In the drawings, some structural or method features may be shown in specific arrangements and/or sequences. It should be understood, however, that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, the features may be arranged in a manner and/or order different from that shown in the illustrative figures. Additionally, the inclusion of structural or method features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments such features may not be included or may be combined with other features.

It should be noted that, in the examples and description of the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or Any such actual relationship or order between these entities or operations is implied. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a" does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the present disclosure The spirit and scope of the application.

Claims (7)

1. An amplifier fast power modulation circuit, comprising a common source transistor, the source of the common source transistor is grounded, the gate of the common source transistor is connected to a bias voltage through a bias resistor, and the drain of the common source transistor is connected to a bias voltage. The power supply terminal is connected, and the gate of the common source transistor is coupled to the radio frequency signal input terminal, characterized in that, it also includes: a power modulation switch, a control port of the power modulation switch is connected to a modulation circuit, an output lower port of the power modulation switch is connected to the bias voltage, and an output upper port of the power modulation switch is coupled to the radio frequency signal input terminal, so that the upper and lower output ports of the power modulation switch are connected in parallel with the bias resistor. 2 . The amplifier fast power modulation circuit according to claim 1 , wherein the power modulation switch is an NMOS transistor or a PMOS transistor. 3 . 3 . The amplifier fast power modulation circuit according to claim 1 , further comprising a load circuit, and the drain of the common source transistor is connected to the power supply terminal through the load circuit. 4 . 4 . The amplifier fast power modulation circuit according to claim 1 , further comprising a feedback circuit, and the source of the common source transistor is grounded through the feedback circuit. 5 . 5 . The amplifier fast power modulation circuit according to claim 1 , further comprising a bias capacitor, wherein the bias resistor and the bias capacitor are connected in series and then grounded. 6 . 6. The amplifier fast power supply modulation circuit according to any one of claims 1-5, wherein the modulation circuit comprises a first inverter connected in series, an RC delay circuit, a NOR gate circuit and an odd number of second inverter. 7 . The amplifier fast power modulation circuit according to claim 6 , wherein the modulation circuit further comprises an odd number of third inverters connected in series for generating an enable signal of the bias voltage. 8 .

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