CN211404065U - Read operation circuit and semiconductor memory - Google Patents

Abstract

An embodiment of the present application provides a read operation circuit and a semiconductor memory, including: the DBI coding module is used for reading out read data from the storage block and determining whether the read data are inverted or not according to the high data bit number in the read data so as to output global bus data for global bus transmission and DBI data for DBI signal line transmission, and the DBI port is used for receiving the DBI data; the parallel-serial conversion circuit is used for carrying out parallel-serial conversion on the global bus data to generate output data of a DQ port; the data buffer module is connected to the storage block through a global bus; and the precharge module is connected to the precharge signal line and used for setting the initial state of the global bus to be low. According to the technical scheme of the embodiment of the application, more data of '0' can be transmitted on the global bus of the Precharge pull-down architecture, so that the turnover frequency of the internal global bus can be reduced, the current is greatly compressed, and the power consumption is reduced.

Description

Read operation circuit and semiconductor memory

technical field

The present application relates to the technical field of semiconductor memory, and in particular, to a read operation circuit, a semiconductor memory and a read operation method.

Background technique

This section is intended to provide a background or context for the embodiments of the application that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section.

Semiconductor memory includes Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM) , Read-Only Memory (Read-Only Memory, ROM for short), flash memory, etc.

In the DRAM protocol of the Solid State Technology Association (Joint Electron Device Engineering Council, JEDEC), there are specific requirements for the speed and power saving of DRAM. How to make DRAM more power-saving while also ensuring signal integrity and reliability of data transmission and storage is an urgent problem to be solved in the industry.

Utility model content

Embodiments of the present application provide a read operation circuit and a semiconductor memory to solve or alleviate one or more technical problems in the prior art.

In a first aspect, an embodiment of the present application provides a read operation circuit, which is applied to a semiconductor memory. The semiconductor memory includes a DQ port, a DBI port, and a storage block, and the read operation circuit includes:

The DBI encoding module is connected to the storage block, and is used to read the read data from the storage block, and determine whether to flip the read data according to the number of bits of the high data in the read data, so as to output the global bus for global bus transmission. Bus data and DBI data for DBI signal line transmission, DBI port is used to receive DBI data;

The parallel-serial conversion circuit is connected between the DQ port and the DBI encoding module through the global bus, and is used to perform parallel-serial conversion on the global bus data to generate the output data of the DQ port;

The data buffer module is connected to the storage block through the global bus;

The precharge module, connected to the precharge signal line, is used to set the initial state of the global bus to be low.

In one embodiment, the DBI encoding module is configured to output the inverted data of the read data as global bus data when the number of bits of the high data in the read data is greater than a preset value, and set the DBI data to and when the number of bits of the high data in the read data is less than or equal to the preset value, output the original read data as the global bus data, and set the DBI data to be low.

In one embodiment, the M-bit DBI data is in one-to-one correspondence with M groups of read data, and the M-bit DBI data is in one-to-one correspondence with M groups of global bus data, and the parallel-to-serial conversion circuit is further connected between the DBI encoding module and the DBI port. It is used to convert the M-bit DBI data to the DBI port after parallel-serial conversion, where M is an integer greater than 1.

In one embodiment, each set of read data is N bits, where N is an integer greater than 1, and the number of bits used by the DBI encoding module for high data in an input set of read data is greater than N/2 In the case of the input set of read data, the inverted data of the input set of read data is output as a corresponding set of global bus data, and the one-bit DBI data corresponding to the input set of read data is set to high; and in the input set of read data In the case that the number of bits of the high data in the read data is less than or equal to N/2, the input set of read data is output as a corresponding set of global bus data, and a set of input read data corresponding to one set is output. bit DBI data is set low.

In one embodiment, the DBI encoding module includes:

DBI encoding unit, the input end of the DBI encoding unit is connected to the storage block, the output end of the DBI encoding unit is connected to the DBI signal line, and the DBI encoding unit is used in the read data when the number of bits of the high data is greater than the preset value under the condition that the DBI data is set to high; and when the number of digits of the high data in the read data is less than or equal to the preset value, the DBI data is set to be low;

Data selector, the input end of the data selector is connected to the DBI coding unit, and is used for receiving the read data through the DBI coding unit, the input end of the data selector also receives DBI data through the DBI signal line, and the output end of the data selector passes the global The bus is connected to the parallel-serial conversion circuit, and the data selector is used to output the inverted data of the read data as the global bus data when the DBI data is high; and when the DBI data is high, the original read data. Output as global bus data.

In one embodiment, the data selector includes a plurality of data selection units, and the data selection units include:

The first inverter, the input end of the first inverter receives DBI data through the DBI signal line;

The second inverter, the input end of the second inverter is connected to the DBI encoding unit for receiving read data from the DBI encoding unit;

The first transmission gate, the input terminal of the first transmission gate is connected to the output terminal of the second inverter, the output terminal of the first transmission gate is connected to the global bus, and is used to output the global bus data, and the anti-control terminal of the first transmission gate be connected to the output end of the first inverter, and the positive control end of the first transmission gate receives DBI data through the DBI signal line;

The second transmission gate, the input end of the second transmission gate is connected to the DBI encoding unit, for receiving read data from the DBI encoding unit, the output end of the second transmission gate is connected to the global bus, for outputting the global bus data, the second transmission gate The negative control terminal of the transmission gate receives DBI data through the DBI signal line, and the positive control terminal of the second transmission gate is connected to the output terminal of the first inverter.

In one embodiment, the data selector includes a plurality of data selection units, and the data selection units include:

The third inverter, the input end of the third inverter receives DBI data through the DBI signal line;

the 4th inverter, the input end of the 4th inverter is connected to the DBI coding unit, for receiving read data from the DBI coding unit;

The first logical AND gate, the first input terminal of the first logical AND gate is connected to the DBI encoding unit for receiving read data from the DBI encoding unit, and the second input terminal of the first logical AND gate is connected to the third inverter the output terminal;

The second logic AND gate, the first input end of the second logic AND gate receives DBI data through the DBI signal line, and the second input end of the second logic AND gate is connected to the output end of the fourth inverter;

A logical OR gate, the two input terminals of the logical OR gate are respectively connected to the output terminal of the first logical AND gate and the output terminal of the second logical AND gate, and the output terminal of the logical OR gate is connected to the global bus for outputting the global bus data .

In one embodiment, the data buffer module includes a plurality of PMOS transistors, the gates of the PMOS transistors are connected to the memory block, and the drains of the PMOS transistors are connected to the global bus; and the precharge module includes a plurality of NMOS transistors and a plurality of hold circuits , the gate of the NMOS transistor is connected to the precharge signal line, the drain of the NMOS transistor is connected to the global bus, and the input and output terminals of the holding circuit are connected to the global bus.

In a second aspect, an embodiment of the present application provides a semiconductor memory, including a DQ port, a DBI port, a memory block, and any of the above read operation circuits.

By adopting the above technical solutions, the embodiments of the present application can realize that more data is transmitted as "0" on the global bus of the Precharge Low (pull-down) architecture, thereby reducing the number of internal global bus flips, greatly compressing current, and reducing power consumption.

The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will become apparent by reference to the drawings and the following detailed description.

Description of drawings

In the drawings, unless stated otherwise, the same reference numbers refer to the same or like parts or elements throughout the several figures. The drawings are not necessarily to scale. It should be understood that these drawings depict only some embodiments disclosed in accordance with the present application and should not be considered as limiting the scope of the present application.

FIG. 1 schematically shows a block diagram of a partial structure of a semiconductor memory according to an implementation manner of this embodiment;

FIG. 2 schematically shows a block diagram of a partial structure of a semiconductor memory in another implementation manner of this embodiment;

FIG. 3 schematically shows a circuit diagram (corresponding to one memory block) of a data buffer module in an implementation manner of this embodiment;

FIG. 4 schematically shows a circuit diagram (corresponding to a plurality of storage blocks) of a data buffer module according to an implementation manner of this embodiment;

Figure 5 schematically shows a schematic diagram of the DBI function;

FIG. 6 schematically shows a block diagram of a DBI encoding module in an implementation manner of this embodiment;

FIG. 7-1 schematically shows a block diagram of a data selection unit in an implementation manner of this embodiment;

FIG. 7-2 schematically shows a block diagram of a data selection unit in another implementation manner of this embodiment.

Description of reference numbers:

10: controller;

20: semiconductor memory;

21: Parallel-serial conversion circuit;

22: data buffer module;

23: DBI encoding module;

24: DQ port;

25: DBI port;

26: memory block;

27: precharge module;

221: PMOS tube;

222: NMOS tube;

223: hold circuit;

231: DBI coding unit;

232: data selector;

232': data selection unit;

232A: the first inverter;

232B: the second inverter;

232C: the first transmission gate;

232D: the second transmission gate;

232E: the third inverter;

232F: the fourth inverter;

232G: the first logic AND gate;

232F: The second logic AND gate;

232K: Logical OR gate.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus their repeated descriptions will be omitted.

FIG. 1 schematically shows a block diagram of a partial structure of a semiconductor memory in an implementation manner of this embodiment. As shown in FIG. 1 , the semiconductor memory 20 includes a DQ port 24 , a data bus inversion (DBI) port 25 , a bank 26 and a read operation circuit. The read operation circuit includes a global bus (Global Bus), a DBI signal line, a parallel-serial conversion circuit 21 , a data buffer module (Data BufferData Buffer) 22 and a DBI encoding module (Encoder) 23 . In one embodiment, the semiconductor memory 20 is a DRAM, such as a fourth-generation double-rate synchronous dynamic random access memory (Double Data Rate SDRAM 4, DDR4 for short).

In an example, as shown in FIG. 1 , an active (Active) command opens a uniquely designated storage block 26 , and a read operation can only be performed on one storage block 26 . That is, when one of the eight memory blocks 26 (ie, Bank<7:0>) is working, the other banks are not working. Through the read operation circuit, the read data D<127:0> in the memory block 26 outputs the 8-bit output data DQ<7:0> through the DQ port 24 . It should be noted that the number of storage blocks 26, the number of data bits of each storage block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment. For example, one DQ port 24 may be used for outputting 16-bit output data; there may also be two DQ ports 24, that is, each DQ port 24 is used for outputting 8-bit output data.

For example, as shown in Figure 2, the output data DQ<7:0> is obtained by performing a read operation on a group of memory blocks Bank<7:0> by the above-mentioned one read operation circuit; the output data DQ<15:8> is obtained by the above-mentioned read operation Another read operation circuit of , is obtained by performing a read operation on another group of memory blocks Bank<15:8>. Correspondingly, in the eight memory blocks 26 (ie, Bank<15:8>) corresponding to DQ<15:8>, when one Bank is working, other Banks are not working.

The semiconductor memory 20 has an array structure, and the structure of each unit may be the same, but due to different input data, the data output by each unit may be different. The read operation circuit of this embodiment is described below by taking one of the memory blocks as an example.

The DBI encoding module 23 is connected to the storage block 26, and is used for reading the read data from the storage block 26, such as D<127:0>, and according to the number of bits of the high data in the read data, to determine whether to reverse the read data to output global bus data for global bus transmission and DBI data for DBI signal line transmission. Wherein, when the data is high, the data can be equal to "1", and when the data is "low", the data can be equal to "0". The inversion of data can be understood as changing from "0" to "1", or, from "1" to "0". The inversion of a data line or a signal line can be understood as a high level to a low level, or a low level to a high level.

In one embodiment, the DBI encoding module 23 is configured to output the inverted data of the read data as global bus data when the number of bits of the high data in the read data is greater than a preset value, and output the DBI data set to high; and in the case that the number of bits of the high data in the read data is less than or equal to the preset value, output the original read data as the global bus data, and set the DBI data to be low.

In an example, the multi-bit read data is not grouped, that is, the DBI data may be one bit, and the DBI data output by the DBI encoding module 23 may be directly output to the DBI port 25 without going through the parallel-serial conversion circuit 21 . In one example, multi-bit read data may be grouped. For example: in one embodiment, read data and global bus data are divided into M groups, DBI data is M bits, M bits of DBI data are in one-to-one correspondence with M groups of read data, and M bits of DBI data are associated with M bits. The group global bus data is in one-to-one correspondence, and the parallel-to-serial conversion circuit 21 is also connected between the DBI encoding module 23 and the DBI port 25, and is used to output the M-bit DBI data to the DBI port after parallel-serial conversion, where M is greater than 1. Integer. It should be noted that the parallel-serial conversion circuit 21 may include two parallel-serial conversion modules, which are respectively used to perform parallel-serial conversion on the global bus data and DBI data, which is not limited in this embodiment.

Further, each group of read data may be N bits, where N is an integer greater than 1, and the DBI encoding module 23 is used in the case where the number of bits of high data in the input group of read data is greater than N/2 Next, output the inverted data of the input group of read data as a corresponding group of global bus data, and set the one-bit DBI data corresponding to the input group of read data to high; and in the input group of read data When the number of bits of the high data in the data is less than or equal to N/2, the input set of read data is output as a corresponding set of global bus data, and the one-bit DBI corresponding to the input set of read data is output. data is set low.

For example, the read data D<127:0> is divided into 16 groups, each group of read data is 8 bits, and each group of read data corresponds to one bit of DBI data. Accordingly, the DBI data is 16 bits, such as DBI<15:0>. The global bus data D'<127:0> is also divided into 16 groups accordingly. Each bit of DBI data corresponds to a set of global bus data. For a set of read data D<127:120>, if the number of bits equal to "1" in D<127:120> is greater than 4 bits, the corresponding DBI<15>=1, and a set of global bus data D is output '<120:127> is equal to the flip data of D<127:120>; if the number of bits equal to "1" in the read data is less than or equal to 4 bits, then the corresponding DBI<15>=0, and a set of global buses output The data D'<120:127> is D<127:120>.

Then, when DBI<15>=1, the global bus data D'<127:120> output from the DBI encoding module 23 is the inversion data of the read data D<127:120> of the storage block 26 (such as Bank0); When DBI<15>=0, the global bus data D'<127:120> output from the DBI encoding module 23 is the read data D<127:120> of the storage block 26 (such as Bank0), that is, the read data D'<127:120>=D<127:120>. Similarly, when DBI<1>=1, the global bus data D'<15:8> output from the DBI encoding module 23 is the inverted data of the read data D<15:8> of the storage block 26 (eg Bank0) ; When DBI<1>=0, the global bus data D'<15:8> output from the DBI encoding module 23 is the read data D<15:8> of the storage block 26 (such as Bank0), that is, the global bus Data D'<15:8>=D<15:8>. When DBI<0>=1, the global bus data D'<7:0> output from the DBI encoding module 23 is the inverted data of the read data D<7:0> of the storage block 26 (eg Bank0); when DBI When <0>=0, the global bus data D'<7:0> output from the DBI encoding module 23 is the read data D<7:0> of the storage block 26 (such as Bank0), that is, the global bus data D' <7:0>=D<7:0>.

In one example, the global bus is multiple and divided into M (M is an integer greater than 1) groups, and each global bus transmits one bit of global bus data. For example: there are 128 global buses, and the 128 global buses are divided into 16 groups. Global bus <0> transmits global bus data D'<0>; global bus <1> transmits global bus data D'<1>; ...; global bus <127> transmits global bus data D'<127>.

In one example, there are 16 DBI signal lines, and each DBI signal line transmits 1-bit DBI data. For example, DBI signal line <0> transmits DBI data DBI<0>, and is associated with global bus data D'<7:0> Correspondingly, it indicates whether D'<7:0> is the inverted data; DBI signal line <1> transmits DBI data DBI<1>, and corresponds to the global bus data D'<15:8>, which indicates D'<15 :8> Whether it is the inverted data; ...; DBI signal line <15> transmits DBI data DBI<15>, and corresponds to the global bus data D'<127:120>, indicating whether D'<127:120> is the inverted data.

The parallel-serial conversion circuit 21 is connected between the DQ port 24 and the DBI encoding module 23 through the global bus, and is used for performing parallel-serial conversion on the global bus data to generate the output data of the DQ port 24 . For example, the parallel-serial conversion circuit 21 performs parallel-serial conversion on the 128-bit global bus data D'<127:0> of Bank0, and then generates 8-bit output data DQ<7:0>, which is passed through the data bus. transmitted to DQ port 24. Therefore, in the global bus data D'<127:0> transmitted on the global bus, there are many data "0". Accordingly, in the semiconductor memory 20 shown in FIG. 2 , 256-bit global bus data (including 128-bit global bus data corresponding to DQ<7:0> and 128-bit global bus data corresponding to DQ<15:8> data), there are many data with "0".

The data buffer module 22 is connected to the storage block 26 through the global bus, and the precharge module 27 is connected to the precharge signal line (Precharge) for setting the initial state of the global bus to be low. That is to say, in this embodiment, the semiconductor memory 20 adopts the global bus transmission structure of the Precharge pull-down.

FIG. 3 schematically shows a circuit diagram (corresponding to one storage block 26 ) of the data buffering module 22 and the precharging module 27 in an implementation manner of this embodiment. FIG. 4 schematically shows a circuit diagram of the data buffer module 22 and the precharge module 27 (corresponding to 8 memory blocks 26 ) in an implementation manner of this embodiment.

As shown in FIG. 3 and FIG. 4 , the data buffer module 22 includes a plurality of PMOS (Positive Channel Metal Oxide Semiconductor) transistors 221 , and the precharge module 27 includes a plurality of NMOS (Negative Channel Metal Oxide Semiconductor) transistors 222 and a plurality of hold circuits 223. The gate of the PMOS transistor 221 is connected to the memory block 26, the drain of the PMOS transistor 221 is connected to the global bus; the gate of the NMOS transistor 222 is connected to the precharge signal line, and the drain of the NMOS transistor 222 is connected to the global bus; The input and output terminals of circuit 223 are connected to the global bus, thereby forming a positive feedback circuit.

The function of Precharge is to set the initial state of each global bus to low. The specific process is that Precharge generates a pull-down pulse (pulse, about 2ns), pulls down a corresponding global bus for a while, and the hold circuit 223 forms a positive feedback and This global bus is locked at a low level, but the ability of the holding circuit 223 to pull up and pull down current is relatively weak; when a certain global bus needs to become a high level, the data line ( That is, the data line connected to the gate of the corresponding PMOS transistor 221) is pulled down (also a pulse, about 2ns), so that the corresponding PMOS transistor 221 will pull up the global bus for a while (the pull-up capability is greater than the hold-up capability). The pull-down capability of the circuit 223), and then the global bus will be locked to a high level through positive feedback to complete the flipping action of the data line. Since there are many "0" data in the global bus data D'<127:0>, less flipping actions are required. Therefore, the IDD4R (read current) of the semiconductor memory will be reduced, so that the power consumption of the semiconductor memory can be reduced.

The function of the DBI port 25 is described below with reference to FIG. 5 . The data output from the semiconductor memory 20 includes the DBI data of the DBI port 25 and the output data of the DQ port 24 . When the DBI data of the DBI port 25 is equal to 1, the output data such as DQ<7:0> needs to be inverted and output to the controller 10; when the DBI data of the DBI port 25 is equal to 0, the original output data can be directly sent to the controller device 10. The on-die termination (ODT) of the semiconductor memory 20 can absorb the current of the DQ port 24 to prevent the signal from being reflected on the internal circuit of the semiconductor memory 20 . The size of the ODT is adjusted to match the controller 10 during the operation of the semiconductor memory 20 . In one example, the ODT structure is a pull-down structure, and when the data of the DQ port 24 is "1" (ie, high), the leakage current through the ODT is large, which increases power consumption. In the present embodiment, since the output data of the DQ port 24 contains many "0" data, the power consumption of the semiconductor memory can be further reduced.

In the related art, when the DBI function is enabled, when the semiconductor memory is performing a read operation, the module for inverting and encoding data is set at the position where the data is about to exit the semiconductor memory, that is, in the parallel-serial conversion area. after the module. Therefore, in the related art, there are many data "1"s transmitted by the global bus inside the semiconductor memory, which will cause the IDD4R to be too large and the power consumption to be high.

According to the semiconductor memory 20 of the present embodiment, in the process of reading data from the semiconductor memory 20, when the global bus data is 256 bits, the 256-bit global bus data needs to be inverted, and only the 32-bit DBI data is inverted, IDD4R The current will be greatly compressed.

In one embodiment, as shown in FIG. 6 , the DBI encoding module 23 includes a DBI encoding unit 231 and a data selector 232 .

The input end of the DBI encoding unit 231 is connected to the storage block 26 through a local bus, the output end of the DBI encoding unit 231 is connected to the DBI signal line, and is connected to the input end of the data selector 232 . The DBI encoding unit is used to set the DBI data to be high when the number of digits of the high data in the read data is greater than the preset value; and the number of digits of the high data in the read data is less than or equal to the preset value case, set DBI data low.

In one example, the DBI encoding unit 231 may include a plurality of DBI encoding subunits, and each DBI encoding subunit is used to process a set of read data, thereby outputting one bit of DBI data. For example, the data selection unit may have 16 DBI coding subunits, corresponding to 16 groups of read data respectively, and then output 16-bit DBI data, wherein each group of read data may have 8 bits.

The input end of the data selector 232 is connected to the DBI encoding unit 231 for receiving the read data through the DBI encoding unit 231, the input end of the data selector 232 also receives the DBI data through the DBI signal line, and the output end of the data selector 232 passes through the DBI signal line. The global bus is connected to the parallel-serial conversion circuit 21 . The data selector 232 is configured to output the inverted data of the read data as the global bus data when the DBI data is high; and output the original read data as the global bus data when the DBI data is high.

In one embodiment, the data selector 232 includes a plurality of data selection units 232', each of which is used to process one bit of DBI data and a set of read data. For example, there may be 16 data selection units 232', corresponding to 16 groups of read data and one bit of DBI data, and each group of read data has 8 bits.

Figures 7-1 and 7-2 show two different implementations of the data selection unit 232'.

As shown in FIG. 7-1, the data selection unit 232' includes a first inverter 232A, a second inverter 232B, a first transmission gate 232C and a second transmission gate 232D. The input end of the first inverter 232A receives DBI data through the DBI signal line; the input end of the second inverter 232B is connected to the DBI encoding unit 231 for receiving read data from the DBI encoding unit 231; the first transmission gate 232C The input terminal of the first transmission gate 232C is connected to the output terminal of the second inverter 232B, and the output terminal of the first transmission gate 232C is connected to the global bus for outputting the global bus data. The upper control terminal of the first inverter 232A is connected to the output terminal of the first inverter 232A, and the positive control terminal (the lower control terminal in FIG. 7-1 ) of the first transmission gate 232C receives DBI data through the DBI signal line; the second transmission gate 232D The input end is connected to the DBI coding unit 231, for receiving the read data from the DBI coding unit 231, the output end of the second transmission gate 232D is connected with the global bus, for outputting the global bus data, the anti-control of the second transmission gate 232D The terminal receives DBI data through the DBI signal line, and the positive control terminal of the second transmission gate 232D is connected to the output terminal of the first inverter 232A.

Taking DBI<0> and read data D<7:0> as an example, as shown in Figure 7-1, when DBI=1, the global bus data D'<7:0> is read data D<7: 0> inversion data; when DBI=0, the global bus data D'<7:0> is the read data D<7:0>.

It should be noted that a group of second inverters 232B, first transmission gates 232C and second transmission gates 232D are used to process one bit of read data and output one bit of corresponding global bus data. That is to say, corresponding to the 8-bit read data D<7:0>, the second inverter 232A, the first transmission gate 232C and the second transmission gate 232D should also have 8 groups, and then output an 8-bit global Bus Data D<7:0>.

As shown in FIG. 7-2, the data selection unit 232' includes a third inverter 232E, a fourth inverter 232F, a first logical AND gate 232G, a second logical AND gate 232H, and a logical OR gate 232K. The input end of the third inverter 232E receives DBI data through the DBI signal line; the input end of the fourth inverter 232F is connected to the DBI encoding unit 231 for receiving read data from the DBI encoding unit 231; the first logical AND The first input end of the gate 232G is connected to the DBI encoding unit 231 for receiving read data from the DBI encoding unit 231, and the second input end of the first logical AND gate 232G is connected to the output end of the third inverter 232E; The first input terminal of the second logical AND gate 232H receives DBI data through the DBI signal line, the second input terminal of the second logical AND gate 232H is connected to the output terminal of the fourth inverter 232F; the two inputs of the logical OR gate 232K The terminals are respectively connected to the output terminal of the first logical AND gate 232G and the output terminal of the second logical AND gate 232H, and the output terminal of the logical OR gate 232K is connected to the global bus for outputting global bus data.

Taking DBI<0> and read data D<7:0> as an example, as shown in Figure 7-2, when DBI=1, the global bus data D'<7:0> is read data D<7: 0> inversion data; when DBI=0, the global bus data D'<7:0> is the read data D<7:0>.

It should be noted that a group of fourth inverters 232F, first logical AND gate 232G, second logical AND gate 232H and logical OR gate 232K are used to process one bit of read data and output one bit of corresponding global bus data. That is to say, corresponding to the 8-bit read data D<7:0>, the third inverter 232E, the fourth inverter 232F, the first logical AND gate 232G, the second logical AND gate 232H and the logical OR The gate 232K should also have 8 groups, and then output 8-bit global bus data D<7:0>.

In practical applications, the semiconductor memory 20 of this embodiment also includes other structures such as a sense amplifier, a precharge circuit, etc., which are all in the prior art and will not be described in detail here in this embodiment.

The read operation circuit provided by the embodiment of the present application is applied to a semiconductor memory whose global bus transmission structure is Precharge pull-down. By arranging the DBI encoding module between the parallel-serial conversion circuit and the storage block, the transmission on the global bus can be "0". There are more data, thus reducing the number of internal global bus flips, which can greatly compress the current and reduce power consumption.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. However, those skilled in the art will appreciate that the technical solutions of the present application may be practiced without one or more of the specific details, or other methods, components, materials, devices, steps, etc. may be employed. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first", "second" may expressly or implicitly include one or more of that feature. In the description of the present application, "plurality" means two or more, unless otherwise expressly and specifically defined.

Furthermore, although the spirit and principles of the present application have been described with reference to several specific embodiments, it should be understood that the present application is not limited to the specific embodiments disclosed, nor does the division of aspects mean that features in these aspects cannot be combined For the benefit, this division is for convenience of presentation only. This application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the technical field disclosed in the present application can easily think of various changes or Replacement, these should be covered within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (9)

1. A read operation circuit, applied to a semiconductor memory, is characterized in that, the semiconductor memory comprises a DQ port, a DBI port and a memory block, and the read operation circuit comprises: A DBI encoding module, connected to the storage block, is configured to read out the read data from the storage block, and determine whether to flip the read data according to the number of bits of the high data in the read data, To output global bus data for global bus transmission and DBI data for DBI signal line transmission, the DBI port is used to receive the DBI data; a parallel-serial conversion circuit, connected between the DQ port and the DBI encoding module through the global bus, for performing parallel-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module, connected to the storage block through the global bus; a precharge module, connected to the precharge signal line, for setting the initial state of the global bus to be low, the precharge module includes a plurality of NMOS transistors, and the gates of the NMOS transistors are connected to the precharge signal line, the drain of the NMOS transistor is connected to the global bus. 2. read operation circuit according to claim 1, is characterized in that, described DBI coding module is also used for inputting preset value, and according to the number of digits of high data in described read data and described preset value outputs the DBI data and the global bus data. 3. read operation circuit according to claim 1, is characterized in that, described read data and described global bus data are all divided into M group, described DBI data is M bit, M bit DBI data and M group The read data is in one-to-one correspondence, and the M-bit DBI data is in one-to-one correspondence with M groups of global bus data. The parallel-serial conversion circuit is also connected between the DBI encoding module and the DBI port, and is used to convert the M-bit DBI The data is output to the DBI port after parallel-serial conversion, wherein M is an integer greater than 1. 4. The read operation circuit according to claim 3, wherein each group of read data is N bits, wherein N is an integer greater than 1, and the DBI encoding module is used for a group of read data according to the input The relationship between the number of bits of the high data and N/2 outputs a corresponding one-bit DBI data and a corresponding set of global bus data. 5. read operation circuit according to claim 1, is characterized in that, described DBI coding module comprises: DBI encoding unit, the input end of the DBI encoding unit is connected to the storage block, the output end of the DBI encoding unit is connected to the DBI signal line, the DBI encoding unit is used for inputting a preset value, and according to the The number of digits of the high data in the read data and the preset value output the DBI data; a data selector, the input end of the data selector is connected to the DBI encoding unit for receiving the read data through the DBI encoding unit, and the input end of the data selector is also passed through the DBI signal line receiving the DBI data, the output end of the data selector is connected to the parallel-serial conversion circuit through the global bus, and the data selector is configured to output the global bus according to the DBI data and the read data data. 6. The read operation circuit according to claim 5, wherein the data selector comprises a plurality of data selection units, and the data selection unit comprises: a first inverter, the input end of the first inverter receives the DBI data through the DBI signal line; a second inverter, the input end of the second inverter is connected to the DBI encoding unit for receiving the read data from the DBI encoding unit; a first transmission gate, the input end of the first transmission gate is connected to the output end of the second inverter, and the output end of the first transmission gate is connected to the global bus for outputting the global bus data, the inverse control end of the first transmission gate is connected to the output end of the first inverter, and the positive control end of the first transmission gate receives the DBI data through the DBI signal line; The second transmission gate, the input end of the second transmission gate is connected to the DBI encoding unit for receiving the read data from the DBI encoding unit, and the output end of the second transmission gate is connected to the global bus connection for outputting the global bus data, the inverse control terminal of the second transmission gate receives the DBI data through the DBI signal line, and the positive control terminal of the second transmission gate is connected to the first transmission gate the output of the inverter. 7. The read operation circuit according to claim 5, wherein the data selector comprises a plurality of data selection units, the data selection units comprising: a third inverter, the input end of the third inverter receives the DBI data through the DBI signal line; a fourth inverter, the input end of the fourth inverter is connected to the DBI encoding unit for receiving the read data from the DBI encoding unit; A first logical AND gate, the first input terminal of the first logical AND gate is connected to the DBI encoding unit, and is used for receiving the read data from the DBI encoding unit, and the first input terminal of the first logical AND gate is used to receive the read data from the DBI encoding unit. The two input terminals are connected to the output terminal of the third inverter; a second logical AND gate, the first input terminal of the second logical AND gate receives the DBI data through the DBI signal line, and the second input terminal of the second logical AND gate is connected to the fourth inverter the output of the device; a logical OR gate, two input terminals of the logical OR gate are respectively connected to the output terminal of the first logical AND gate and the output terminal of the second logical AND gate, and the output terminal of the logical OR gate is connected to the output terminal of the logical OR gate A global bus connection for outputting the global bus data. 8 . The read operation circuit according to claim 1 , wherein the data buffer module comprises a plurality of PMOS transistors, the gates of the PMOS transistors are connected to the memory block, and the PMOS transistors are connected to the memory block. 9 . The drains of the transistors are connected to the global bus; and the precharge module further includes a plurality of hold circuits whose input and output terminals are connected to the global bus. 9. A semiconductor memory, comprising a DQ port, a DBI port, a memory block and the read operation circuit according to any one of claims 1 to 8.

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