Disclosure of Invention
In view of this, embodiments of the present disclosure provide a power switching circuit and an electronic device to solve a problem that a current power supply circuit cannot support simultaneous access to multiple charging devices.
According to a first aspect, an embodiment of the present application provides a power switching circuit, including: a main power supply unit and at least one auxiliary power supply unit; when the main power supply unit and the auxiliary power supply unit are simultaneously connected with external power, the power supply switching circuit outputs electric energy through the output end of the main power supply unit; when any one of the main power supply unit and the auxiliary power supply unit is connected with an external power, the power supply switching circuit outputs electric energy through the output end of the power supply unit connected with the external power.
With reference to the first aspect, in some embodiments of the present application, the main power supply unit includes: a resistor R794, a transistor Q29, a resistor R812 and a double PMOS chip Q56; the resistor R794 is connected between the external power of the main power supply unit and the base of the transistor Q29; the emitter of the transistor Q29 is grounded, the collector of the transistor Q29 is connected with the first end of the resistor R812, and the second end of the resistor R812 is respectively connected with the first gate, the second gate, the first source and the second source of the double PMOS chip Q56; the first drain of the double PMOS chip Q56 is electrically connected with the external power supply unit, and the second drain of the double PMOS chip Q56 is used for outputting electric energy when the external power supply unit is powered on.
With reference to the first aspect, in some embodiments of the present application, the main power supply unit further includes: a resistor R809 and a capacitor C764; a first end of the resistor R809 is connected with a second end of the resistor R812, and a second end of the resistor R809 is respectively connected with a first source and a second source of the double PMOS chip Q56; the capacitor C764 is connected in parallel to two ends of the resistor R809.
With reference to the first aspect, in some embodiments of the present application, the main power supply unit further includes: resistor R795, transistor Q41, and resistor R968; a first end of the resistor R795 is electrically connected with the external power of the main power supply unit, and a second end of the resistor R795 is connected with the base of the transistor Q41; the emitter of the transistor Q41 is grounded, the collector of the transistor Q41 is connected with the first end of the resistor R968, and the second end of the resistor R968 is connected with a direct current power supply; the collector of the transistor Q41 is also used to output a signal indicating whether the external power of the main power supply unit is powered up.
With reference to the first aspect, in some embodiments of the present application, the secondary power supply unit includes: the resistor R714, the transistor Q31, the resistor R796, the double PMOS chip U40 and the transistor Q55; the base of the transistor Q55 is electrically connected with the outside of the main power supply unit, the emitter of the transistor Q55 is grounded, and the collector of the transistor Q55 is connected with the base of the transistor Q31; the resistor R714 is connected between the external power of the auxiliary power supply unit and the base of the transistor Q31; the emitter of the transistor Q31 is grounded, the collector of the transistor Q31 is connected with a first end of the resistor R796, and a second end of the resistor R796 is respectively connected with a first gate, a second gate, a first source and a second source of the double PMOS chip U40; the first drain of the double PMOS chip U40 is electrically connected with the external power supply unit, and the second drain of the double PMOS chip U40 is used for outputting electric energy when only the external power supply unit is powered on.
With reference to the first aspect, in some embodiments of the present application, the secondary power supply unit further includes: resistor R810 and capacitor C267; a first end of the resistor R810 is connected to a second end of the resistor R796, and a second end of the resistor R810 is connected to a first source and a second source of the dual PMOS chip U40, respectively; the capacitor C267 is connected in parallel across the resistor R810.
With reference to the first aspect, in some embodiments of the present application, the secondary power supply unit further includes: a resistor R1001 and a capacitor C978; the resistor R1001 is connected between the base of the transistor Q55 and the external power of the main power supply unit; the capacitor C978 is connected between the base of the transistor Q55 and ground.
With reference to the first aspect, in some embodiments of the present application, the secondary power supply unit further includes: resistor R769 and transistor Q32; a first terminal of the resistor R769 receives a control signal for controlling whether the auxiliary power supply unit is enabled, and a second terminal of the resistor R769 is connected with the base of the transistor Q32; the emitter of the transistor Q32 is grounded, and the collector of the transistor Q32 is connected to the base of the transistor Q31.
With reference to the first aspect, in some embodiments of the present application, the secondary power supply unit further includes: resistor R769 and transistor Q32; a first terminal of the resistor R769 receives a control signal for controlling whether the auxiliary power supply unit is enabled, and a second terminal of the resistor R769 is connected with the base of the transistor Q32; the emitter of the transistor Q32 is grounded, and the collector of the transistor Q32 is connected to the base of the transistor Q31.
According to a second aspect, an embodiment of the present application provides an electronic device, including the power switching circuit as described in the first aspect or any implementation manner of the first aspect.
In the power switching circuit provided by the embodiment of the application, the main power supply unit and each auxiliary power supply unit are allowed to be simultaneously connected to external power, and only the main power supply unit is controlled to be connected under the condition that the main power supply unit and each auxiliary power supply unit are simultaneously connected to the external power, so that the power switching circuit provided by the embodiment of the application can realize charging under the condition that a plurality of power supply units are simultaneously powered on, and the problem that the conventional power supply circuit cannot support simultaneous connection of a plurality of charging devices is solved.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to explain the technical solution described in the present application, the following description will be given by way of specific examples.
An embodiment of the present application provides a power switching circuit, as shown in fig. 1, the power switching circuit may include: a main power supply unit and at least one auxiliary power supply unit.
When the main power supply unit and each auxiliary power supply unit are simultaneously connected with external power, the power supply switching circuit outputs electric energy through the output end of the main power supply unit.
When any one of the main power supply unit and the auxiliary power supply unit is connected with the external power, the power supply switching circuit outputs electric energy through the output end of the power supply unit connected with the external power.
In the power supply switching circuit shown in fig. 1, one main power supply unit and one auxiliary power supply unit are schematically drawn. In practical application, a user can freely set the number of the auxiliary power supply units according to needs, and the embodiment of the application does not limit the number.
In a particular real-time manner, as shown in fig. 2, the main power supply unit may include: resistor R794, transistor Q29, resistor R812 and double PMOS chip Q56.
Specifically, the resistor R794 is connected between the external power of the main power supply unit and the base of the transistor Q29. The emitter of the transistor Q29 is grounded, the collector of the transistor Q29 is connected to the first terminal of the resistor R812, and the second terminal of the resistor R812 is connected to the first gate, the second gate, the first source and the second source of the dual PMOS chip Q56, respectively.
The first drain of the double PMOS chip Q56 is electrically connected to the external power of the main power supply unit, and the second drain of the double PMOS chip Q56 is used for outputting power when the external power of the main power supply unit is powered on.
Optionally, a resistor R809 and a capacitor C764 may be added to the main power supply unit.
Specifically, a first end of the resistor R809 is connected to a second end of the resistor R812, and a second end of the resistor R809 is connected to a first source and a second source of the dual PMOS chip Q56, respectively. The capacitor C764 is connected in parallel across the resistor R809.
The resistor R809 and the capacitor C764 form an RC delay circuit, so that the voltage on the first gate and the second gate of the dual PMOS chip Q56 can be slowly reduced, the dual PMOS chip Q56 can be slowly turned on, and slow start of power supply is realized.
Optionally, a resistor R795, a transistor Q41, and a resistor R968 may be additionally provided in the main power supply unit.
Specifically, a first terminal of the resistor R795 is electrically connected to the outside of the main power supply unit, and a second terminal of the resistor R795 is connected to the base of the transistor Q41. The emitter of the transistor Q41 is grounded, the collector of the transistor Q41 is connected to a first terminal of a resistor R968, and a second terminal of the resistor R968 is connected to a dc power supply. The collector of the transistor Q41 is also used to output a signal indicating whether the external power of the main power supply unit is powered up.
When the external power of the main power supply unit is powered on, BASE _ PWR in fig. 2 is high, the transistor Q41 is turned on, and the signal AP _ BASE output by the collector of the transistor Q41 is a low level signal; when the external power of the main power supply unit is turned off, BASE _ PWR in fig. 2 is low, Q41 is turned off, and the transistor Q41 is turned off, so that AP _ BASE output by the collector of the transistor Q41 is a high signal. The signal AP _ BASE output by the collector of the transistor Q41 can reflect whether the main power supply unit is powered up.
In another embodiment, as shown in fig. 2, the auxiliary power supply unit may include: resistor R714, transistor Q31, resistor R796, double PMOS chip U40 and transistor Q55.
Specifically, the base of the transistor Q55 is electrically connected to the outside of the main power supply unit, the emitter of the transistor Q55 is grounded, and the collector of the transistor Q55 is connected to the base of the transistor Q31. The resistor R714 is connected between the external power of the auxiliary power supply unit and the base of the transistor Q31. The emitter of the transistor Q31 is grounded, the collector of the transistor Q31 is connected to a first terminal of a resistor R796, and a second terminal of the resistor R796 is connected to the first gate, the second gate, the first source and the second source of the dual PMOS chip U40, respectively.
The first drain of the double PMOS chip U40 is electrically connected to the external power of the auxiliary power supply unit, and the second drain of the double PMOS chip U40 is used for outputting power when only the external power of the auxiliary power supply unit is powered on.
Only when the external power of the main power supply unit is powered down and the external power of the auxiliary power supply unit is powered up, i.e. when the BASE _ PWR in fig. 2 is low and the USB _ VCC is high, the transistor Q31 is turned on, so that the dual PMOS chip U40 is turned on, and the output end of the auxiliary power supply unit outputs electric energy.
Optionally, a resistor R810 and a capacitor C267 may be additionally provided in the auxiliary power supply unit.
A first terminal of the resistor R810 is connected to a second terminal of the resistor R796, and a second terminal of the resistor R810 is connected to a first source and a second source of the dual PMOS chip U40, respectively. The capacitor C267 is connected in parallel across the resistor R810.
The resistor R810 and the capacitor C267 form an RC delay circuit, which can slowly decrease the voltage on the first gate and the second gate of the dual PMOS chip U40, so that the dual PMOS chip U40 is turned on slowly, slow start of power supply is realized, and damage to the back-end circuit due to an excessively high and excessively fast pulse voltage when the external power of the auxiliary power supply unit is suddenly powered on, i.e., when the USB _ VCC in fig. 2 is inserted instantaneously is avoided.
Optionally, a resistor R1001 and a capacitor C978 may be additionally provided in the auxiliary power supply unit.
Specifically, the resistor R1001 is connected between the base of the transistor Q55 and the external power of the main power supply unit. Capacitor C978 is connected between the base of transistor Q55 and ground.
When the external power of the main power supply unit and the external power of the auxiliary power supply unit are powered on simultaneously, i.e., both BASE _ PWR and USB _ VCC in fig. 2 are high, it is necessary to preferentially supply power to the outside through the main power supply unit.
BASE _ PWR in fig. 2 can control the turn-off or turn-on of the transistor Q31 through the transistor Q55. When both BASE _ PWR and USB _ VCC in fig. 2 are high, the transistor Q55 is turned on, so that the transistor Q31 is turned off, the dual PMOS chip U40 is turned off, and the auxiliary power unit is turned off. At the same time, the transistor Q29 is turned on, thereby turning on the dual PMOS chip Q56 and turning on the main power supply unit.
When the external power of the main power supply unit and the external power of the auxiliary power supply unit are powered on simultaneously, and the main power supply unit supplies power preferentially, if the main power supply unit is removed suddenly, the dual-PMOS chip Q56 needs to be ensured to be turned off first, and then the dual-PMOS chip U40 needs to be turned on. The power supply switching circuit provided by the embodiment of the application can avoid that the double PMOS chips U40 and the double PMOS chips Q56 are opened simultaneously, and the output electric energy of the auxiliary power supply unit is prevented from flowing backwards to the main power supply unit. Because the double PMOS chips are in an incomplete conduction state, when the double PMOS chip U40 and the double PMOS chip Q56 are simultaneously turned on, the levels of the output V _ CHG of the main power supply unit and the auxiliary power supply unit in the power supply switching circuit are clamped below 5V, and normal power supply cannot be realized.
In addition, the problem can be solved by increasing the resistor R794, reducing the resistor R1001 and increasing the capacitor C978 to ensure that the double PMOS chip Q56 is turned off first and then the double PMOS chip U40 is turned on again.
Optionally, a resistor R769 and a transistor Q32 may be added to the auxiliary power supply unit.
A first terminal of the resistor R769 receives a control signal for controlling whether the auxiliary power supply unit is enabled, and a second terminal of the resistor R769 is connected to the base of the transistor Q32. The emitter of the transistor Q32 is grounded, and the collector of the transistor Q32 is connected to the base of the transistor Q31.
When the auxiliary power supply unit adopts the USB adapter as external power, the use state management of the USB can be realized through the resistor R769 and the transistor Q32.
In fig. 2, AP _ USB may be used to switch the use state of USB. The usage status of a general USB may include USB boost and USB Charge. The USB HOST indicates that the USB is set in the HOST device state, the corresponding peripheral device may be a mouse, a keyboard, a hard disk, a USB disk, an MP3, or a USB gamepad, and the peripheral device may read corresponding data information in the USB HOST state. USB Charge indicates that the USB setting is in the USB charger state.
When AP _ USB is high in FIG. 2, USB HOST is enabled; when AP _ USB is low in FIG. 2, USB Charge is enabled.
An embodiment of the present application further provides an electronic device, as shown in fig. 3, where the electronic device 200 includes the power switching circuit 100 as shown in fig. 1 or fig. 2. In the electronic apparatus 200 shown in fig. 3, the configuration of the electronic apparatus 200 is schematically described based on the power supply switching circuit shown in fig. 1. When the user uses the electronic device 200, the power switching circuit shown in fig. 2 may be selected as needed, which is not limited in the embodiment of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.