CN210201811U - Phase-locked loop suitable for high-speed interface - Google Patents

Abstract

The utility model relates to a phase-locked loop field just discloses a phase-locked loop suitable for high-speed interface, including 32MHz crystal oscillator, frequency divider, phase discriminator, FPGA, loop filter, voltage controlled oscillator, amplifier, wave filter, the output of 32MHz crystal oscillator and the input signal connection of frequency divider, the output of frequency divider and the input signal connection of phase discriminator, FPGA's output respectively with the input signal connection of frequency divider and phase discriminator, the output of phase discriminator and loop filter's input electric connection, loop filter output and voltage controlled oscillator's input electric connection, voltage controlled oscillator's output respectively with the input electric connection of amplifier and wave filter, this utility model, it is slow to have solved response speed, can not realize miniature low-power consumption requirement, output signal phase noise difference, clutter suppression are low, Large volume, heavy weight, complex debugging and slow response speed.

Description

Phase-locked loop suitable for high-speed interface

Technical Field

The utility model relates to a phase-locked loop field specifically is a phase-locked loop suitable for high-speed interface.

Background

A pll is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage controlled oscillator to generate a target frequency, and as known to those who have learned the automatic control principle, the pll is a typical feedback control circuit that uses an externally input reference signal to control the frequency and phase of an internal oscillation signal of a loop, so as to achieve automatic tracking of an output signal frequency to an input signal frequency, and is generally used in a closed-loop tracking circuit.

At present, the realization of a frequency source in a microwave system is mainly realized by adopting a phase-locked loop, the phase-locked loop mainly comprises an analog phase-locked loop, a digital phase-locked loop and a memory (microcomputer controlled) phase-locked loop, the microcomputer controlled phase-locked loop can control and generate the required frequency in the frequency range of a VCO, most of the microcomputer controlled phase-locked loops on the market are controlled by a single chip, but the single chip has the characteristic of slow response speed because of the fact that a software command is needed and the self instruction is sequentially executed, so that the requirements of miniature low power consumption cannot be realized, the phase noise of an output signal is poor, the clutter suppression is low, the volume is large, the weight is heavier, the debugging is complex, the response speed is slow, and the industrial requirements of images, communication and the like cannot be met.

SUMMERY OF THE UTILITY MODEL

The utility model is not enough to prior art, the utility model provides a phase-locked loop suitable for high-speed interface has the requirement of realizing miniature low-power consumption, output signal phase noise is good, the clutter suppression is high, small, light in weight, the debugging is simple, response speed is fast, can satisfy the image, the advantage of trade demands such as communication, it is slow to have solved response speed, miniature low-power consumption requirement has not been realized, output signal phase noise is poor, the clutter suppression is low, and is bulky, weight is heavier, the debugging is complicated, response speed is slow, can not satisfy the image, the problem of trade demands such as communication.

For realizing the miniature low-power consumption requirement of above-mentioned realization, output signal phase noise is good, the clutter restraines height, small, light in weight, debugging are simple, and response speed is fast, can satisfy the purpose of trades demands such as image, communication, the utility model provides a following technical scheme:

the utility model provides a phase-locked loop suitable for high-speed interface, includes 32MHz crystal oscillator, frequency divider, phase discriminator, FPGA, loop filter, voltage controlled oscillator, amplifier, wave filter, the output of 32MHz crystal oscillator and the input signal connection of frequency divider, the output of frequency divider and the input signal connection of phase discriminator, FPGA's output respectively with the input signal connection of frequency divider and phase discriminator, the output of phase discriminator and loop filter's input electric connection, loop filter output and voltage controlled oscillator's input electric connection, voltage controlled oscillator's output respectively with the input electric connection of amplifier and wave filter, the output of wave filter and the input signal connection of frequency divider.

Preferably, the 32MHz crystal oscillator is a crystal oscillator, and the MHz crystal oscillator is a slice cut from a quartz crystal according to a certain azimuth angle.

Preferably, the frequency divider is a circuit device in the sound box, and the frequency divider separates the input analog audio signal into different parts of high pitch, middle pitch, low pitch, and the like.

Preferably, the phase detector is a device capable of identifying a phase difference of input signals, and the phase detector is a circuit that makes an output voltage have a certain relationship with a phase difference between two input signals.

Preferably, the FPGA is a field programmable gate array, the FPGA is a product of further development on the basis of programmable devices such as PAL, GAL, etc., and the FPGA appears as a semi-custom circuit in the field of application specific integrated circuits ASIC.

Preferably, the loop filter is one of the modules in the working principle of the frequency hopping source.

Preferably, the voltage-controlled oscillator is an oscillating circuit (VCO) having an output frequency corresponding to an input control voltage.

Preferably, the amplifier is a device capable of amplifying the voltage or power of an input signal, and the amplifier is composed of a tube or a transistor, a power transformer and other electrical components.

Preferably, the filter is a filter circuit composed of a capacitor, an inductor and a resistor.

Compared with the prior art, the utility model provides a phase-locked loop suitable for high-speed interface possesses following beneficial effect:

1. the phase-locked loop suitable for the high-speed interface has the advantages that 32MHz reference signals generated by a 32MHz crystal oscillator are filtered and then sent to a phase discriminator, the FPGA4 sends data to the phase discriminator, the phase discriminator can carry out correct parameter configuration, the phase discriminator compares the reference signals with feedback signals, output tuning voltage passes through a loop filter and then reaches a voltage-controlled oscillator, the voltage-controlled oscillator outputs fundamental wave signals, the fundamental wave signals are output in two paths, one path of the fundamental wave signals returns to the phase discriminator to serve as the feedback signals, the other path of the fundamental wave signals is input to a fundamental wave filter, then the signals enter an amplifier to be amplified, filtered and attenuated, the problems that the response speed is low, the miniature low-power-consumption requirements cannot be met, the phase noise of the output signals is poor, the clutter suppression is low, the volume is large, the weight is heavy, the debugging is complex, the response speed.

2. This phase-locked loop suitable for high-speed interface has more corresponding fast characteristics than traditional single chip microcomputer control, can strengthen the research and development technical ability in the aspect of the frequency source, has improved the occupation rate of this type of product in the market to be applied to the cell-phone, on products such as wifi interference ware, and export brazil, pass through user's test acceptance, use in user department and obtain the recognition.

Drawings

Fig. 1 is a schematic structural diagram of the present invention.

In the figure: 1. a 32MHz crystal oscillator; 2. a frequency divider; 3. a phase discriminator; 4. an FPGA; 5. a loop filter; 6. a voltage controlled oscillator; 7. an amplifier; 8. and a filter.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, a phase-locked loop suitable for a high-speed interface includes a 32MHz crystal oscillator 1, a frequency divider 2, a phase detector 3, an FPGA4, a loop filter 5, a voltage-controlled oscillator 6, an amplifier 7, a filter 8, an output end of the 32MHz crystal oscillator 1 is in signal connection with an input end of the frequency divider 2, an output end of the frequency divider 2 is in signal connection with an input end of the phase detector 3, an output end of the FPGA4 is in signal connection with input ends of the frequency divider 2 and the phase detector 3, an output end of the phase detector 3 is electrically connected with an input end of the loop filter 5, an output end of the loop filter 5 is electrically connected with an input end of the voltage-controlled oscillator 6, an output end of the voltage-controlled oscillator 6 is electrically connected with input ends of the amplifier 7 and the filter 8, and.

Further, the 32MHz crystal oscillator 1 is a crystal oscillator, the 32MHz crystal oscillator 1 means that a slice is cut from a quartz crystal according to a certain azimuth angle, and the 32MHz crystal oscillator 1 generates a 32MHz reference signal.

Furthermore, the frequency divider 2 is a circuit device in the sound box, the frequency divider 2 separates the input analog audio signal into different parts of high pitch, middle pitch, low pitch, etc., the frequency divider 2 distinguishes the sound signals of different frequency bands, and the sound signals are respectively amplified and then sent to the loudspeakers of corresponding frequency bands for playback.

Further, the phase detector 3 is a device capable of identifying the phase difference of input signals, the phase detector 3 is a circuit which enables the phase difference between output voltage and two input signals to have a definite relationship, the phase detector 3 finds the phase difference between the input signals and feedback signals, then the phase difference is represented in a reasonable mode, a function which represents the definite relationship between the phase difference and the output voltage is called as a phase detection characteristic, and the phase detector 3 is one of basic components of a phase-locked loop.

Furthermore, the FPGA4 is a field programmable gate array, the FPGA4 is a product further developed on the basis of programmable devices such as PAL and GAL, the FPGA4 appears as a semi-custom circuit in the field of ASIC, the FPGA4 not only solves the disadvantages of the custom circuit, but also overcomes the defect of limited gate circuits of the original programmable device, the structure of the FPGA4 is a lookup table structure, and the operation speed directly depends on the crystal oscillation speed due to the hardware circuit, so that the system is stable, and is particularly suitable for places requiring high-speed interface circuits in the communication field and the like.

Furthermore, the loop filter 5 is one of the modules in the working principle of the frequency hopping source, the loop filter 5 attenuates high-frequency error components at the output end of the phase discriminator 3 to improve the anti-interference performance, and when the loop jumps out of a locking state, the loop is improved to be stored in a short period, and signals are rapidly recovered.

Further, the voltage-controlled oscillator 6 is an oscillating circuit (VCO) having an output frequency corresponding to an input control voltage, the frequency of the oscillator VCO is a function of the input signal voltage, and the operating state of the oscillator or the parameters of the components of the oscillating circuit are controlled by the input control voltage, thereby forming the voltage-controlled oscillator 6.

Further, the amplifier 7 is a device capable of amplifying the voltage or power of an input signal, the amplifier 7 is composed of a tube or a transistor, a power transformer and other electrical components, and the amplifier 7 is used in various devices such as communication, broadcasting, radar, television, automatic control, and the like.

Further, the filter 8 is a filter circuit composed of a capacitor, an inductor and a resistor, and the filter 8 can effectively filter a frequency point of a specific frequency in the power line or frequencies other than the frequency point to obtain a power signal of the specific frequency or eliminate the power signal of the specific frequency.

The working principle is as follows: the 32MHz crystal oscillator 1 generates a 32MHz reference signal, the reference signal is filtered and then sent to the phase discriminator 3, the FPGA4 sends data to the phase discriminator 3, the phase discriminator 3 can carry out correct parameter configuration, the phase discriminator 3 compares the reference signal with a feedback signal, an output tuning voltage passes through the loop filter 5 and then reaches the voltage controlled oscillator 6, the voltage controlled oscillator 6 outputs a fundamental wave signal, the fundamental wave signal is divided into two paths to be output, one path returns to the phase discriminator 3 as the feedback signal, the other path is input to the amplifier 7, then the signal passes through the amplification, filtering and attenuation output signals, the requirements are met through the matching of the 32MHz crystal oscillator 1, the frequency divider 2, the phase discriminator 3, the FPGA4, the loop filter 5, the voltage controlled oscillator 6, the amplifier 7 and the filter 8, compared with the traditional single chip microcomputer control, the utility model has the characteristics of fast corresponding speed, the response speed is slow, the requirement of micro low power consumption can, poor phase noise of output signals, low clutter suppression, large volume, heavy weight, complex debugging, low response speed and incapability of meeting the requirements of industries such as images, communication and the like.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (9)

1. The utility model provides a phase-locked loop suitable for high-speed interface, includes 32MHz crystal oscillator (1), frequency divider (2), phase discriminator (3), FPGA (4), loop filter (5), voltage controlled oscillator (6), amplifier (7), filter (8), its characterized in that: the output of 32MHz crystal oscillator (1) and the input signal connection of frequency divider (2), the output of frequency divider (2) and the input signal connection of phase discriminator (3), the output of FPGA (4) respectively with the input signal connection of frequency divider (2) and phase discriminator (3), the output of phase discriminator (3) and the input electric connection of loop filter (5), the input electric connection of loop filter (5) output and voltage controlled oscillator (6), the output of voltage controlled oscillator (6) respectively with the input electric connection of amplifier (7) and wave filter (8), the output of wave filter (8) and the input signal connection of frequency divider (2).

2. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the 32MHz crystal oscillator (1) is a crystal oscillator, and the 32MHz crystal oscillator (1) is a slice cut from a quartz crystal according to a certain azimuth angle.

3. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the frequency divider (2) is a circuit device in the sound box, and the frequency divider (2) separates an input analog audio signal into different parts of high pitch, middle pitch, low pitch and the like.

4. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the phase detector (3) is a device capable of identifying the phase difference of input signals, and the phase detector (3) is a circuit which enables the phase difference between output voltage and two input signals to have a definite relation.

5. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the FPGA (4) is a field programmable gate array, the FPGA (4) is a product which is further developed on the basis of programmable devices such as PAL and GAL, and the FPGA (4) appears as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC).

6. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the loop filter (5) is one of the modules in the working principle of the frequency hopping source.

7. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the voltage-controlled oscillator (6) is an oscillating circuit (VCO) with output frequency corresponding to input control voltage.

8. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the amplifier (7) is a device capable of amplifying the voltage or power of an input signal, and the amplifier (7) is composed of a tube or a transistor, a power transformer and other electrical components.

9. A phase locked loop adapted for use in a high speed interface as claimed in claim 1, wherein: the filter (8) is a filter circuit consisting of a capacitor, an inductor and a resistor.

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