CN210201800U

CN210201800U - An Inverted Detection Clock Generation Circuit Without High Level Intersection

Info

Publication number: CN210201800U
Application number: CN201921167394.4U
Authority: CN
Inventors: Fuhua Li; 李富华; Jingxing Dai; 戴晶星; Qing Wu; 吴庆; Jialin Yin; 殷嘉琳
Original assignee: Suzhou University
Current assignee: Suzhou University
Priority date: 2018-09-13
Filing date: 2019-07-24
Publication date: 2020-03-27
Anticipated expiration: 2029-07-24

Abstract

When the detection clock signal Q2 and the detection clock signal Q4 that probably take place in order to solve high frequency anti-phase detection clock signal Q2 and Q4 are the high level simultaneously, lead to novel signal to descend the problem that the border detection circuit became invalid, the utility model provides an there is not the anti-phase detection clock generating circuit of high level intersection, it passes through the combination of NOR gate and delay timer with clock signal Fclk, has avoided the high frequency anti-phase detection clock signal Q2 and the situation of Q4 high level to appear simultaneously in all chronologies.

Description

Reverse phase detection clock generation circuit without high level intersection

Technical Field

The utility model belongs to digital integrated circuit design field, it is comparatively specific, involve an anti-phase detection clock generating circuit that does not have high level intersection.

Background

The 2018105290672 patent application and 201820810334 patent application relate to a set of high frequency inverted sense clock signals Q2 and Q4, and the sense clock signal Q4 is at a low level when the sense clock signal Q2 and the sense clock signal Q4 are in an ideal state, i.e., when the sense clock signal Q2 is at a high level; or when the detection clock signal Q2 is at a low level, the detection clock signal Q4 is a novel signal falling edge detection circuit designed under the condition of a high level, and the circuit can solve the problem that the traditional double-trigger edge detection circuit cannot detect or can miss detection of the change of the falling edge of the data pulse signal when the frequency of the data pulse signal is more than or equal to the frequency halving of the detection clock.

All the D latches are triggered by the levels of the high-frequency inverted detection clock signals Q2 and Q4, and in a normal condition, when the detection clock signal Q2 is at a high level, the detection clock signal Q4 is at a low level, only the D latch connected with the detection clock signal Q2 can be triggered, and the D latch connected with the detection clock signal Q4 cannot be triggered; when the test clock signal Q4 is high, the test clock signal Q2 should be low, and only the D latch connected to the test clock signal Q4 can be triggered, but the D latch connected to the test clock signal Q2 cannot be triggered.

In general, the clock signal Fclk may pass through an inverter to obtain an inverted clock signal, but due to a certain delay effect of the inverter, the inverted clock signal and the original clock signal Fclk may generate an intersection of a high level or a low level after a period of time elapses.

However, all D latches in the novel signal falling edge detection circuit are controlled by the high-frequency inverted detection clock signals Q2 and Q4 and enabled at a high level, so that once the detection clock signal Q2 intersects with the detection clock signal Q4 and the intersection is at a high level, all D latches are enabled together, and the novel signal falling edge detection circuit fails.

SUMMERY OF THE UTILITY MODEL

In view of this, in order to solve the problem that the detection clock signal Q2 and the detection clock signal Q4 that the above high-frequency inverted detection clock signals Q2 and Q4 may occur are high level at the same time, which results in the failure of the novel signal falling edge detection circuit, the utility model provides an inverted detection clock generating circuit without high level intersection, which avoids the situation that the high-frequency inverted detection clock signals Q2 and Q4 are high level at the same time in all time sequences by combining the nor gate and the delayer with the clock signal Fclk.

An inverted detection clock generation circuit without a high level intersection, comprising: the clock signal Fclk, the Reset terminal Reset-1, the first nor gate 1, the second nor gate 2, the third nor gate 3, the first DELAY1, the second DELAY2, the first inverter 4, the second inverter 5, the third inverter 6, and the fourth inverter 7, wherein: an original clock signal Fclk is respectively connected with a first signal input end of a third nor gate 3 and a second signal input end of a first nor gate 1, and a Reset end Reset-1 is respectively connected with the third nor gate 3 and the first signal input end of the first nor gate 1; a signal output terminal of the first nor gate 1 is connected to a second signal input terminal of the second nor gate 2, a signal output terminal of the second nor gate 2 outputs a detection clock signal clk _ Q2 after passing through a second DELAY2, the detection clock signal clk _ Q2 is driven by a third inverter 6 and a fourth inverter 7, and a detection clock signal Q2 is output; the detection clock signal clk _ Q2 is simultaneously connected to the second signal input terminal of the third nor gate 3, the signal output terminal of the third nor gate 3 outputs the detection clock signal clk _ Q4 after passing through the first DELAY unit DELAY1, the detection clock signal clk _ Q4 is driven by the first inverter 4 and the second inverter 5, and the detection clock signal Q4 is output; the detection clock signal Q4 is connected to a first signal input terminal of the second nor gate 2; the initial state of the inverted detection clock generating circuit without high level intersection is set as that the original clock signal Fclk is set to be high level, the Reset terminal Reset-1 is set to be high level, the detection clock signal clk _ Q2 is set to be high level, and the detection clock signal clk _ Q4 is set to be low level.

Further, the DELAY of the first DELAY1 and the DELAY of the second DELAY2 may be the same or different.

Further, the DELAY of the first DELAY1 and the second DELAY2 is 1ns-3 ns.

Furthermore, the first nor gate 1, the second nor gate 2, the third nor gate 3, the first inverter 4, the second inverter 5, the third inverter 6 and the fourth inverter 7 have time delays, and the time delays are respectively 0.2ns-0.3 ns.

Further, the size of the second inverter 5 is 1.2 to 6 times the size of the first inverter 4, and preferably, the size of the second inverter 5 is 2 to 4 times the size of the first inverter 4.

Further, the size of the fourth inverter 7 is 1.2 to 6 times the size of the third inverter 6, and preferably, the size of the fourth inverter 7 is 2 to 4 times the size of the first inverter 4.

Further, the Reset terminal Reset-1 is obtained by passing the enable terminal Reset of application No. 2018105290672 and application No. 201820810334 through an inverter. When the enable terminal Reset exits Reset, the Reset terminal Reset-1 is released.

The operation principle of the inverted detection clock generation circuit without high level intersection as described above is as follows:

first, the logic of the nor gate is to be understood, the nor gate has two signal inputs and one signal output, and assuming that the signal at the first signal input is a, the signal at the second signal input is B, and the signal at the signal output is Y, the truth table of the nor gate is as follows:

A	B	Y
			0	0	1
0	1	0
			1	0	0
1	1	0

remarking: a "0" in the truth table indicates that the signal is low and a "1" indicates high.

To summarize, the case of the truth table for nor gates is: as long as one of the signal a at the first signal input terminal or the signal B at the second signal input terminal is "1", the signal Y at the signal output terminal outputs "0"; otherwise, that is, the signal a at the first signal input terminal and the signal B at the second signal input terminal are simultaneously "0", the signal Y at the signal output terminal outputs "1".

Assuming that only the first DELAY1 and the second DELAY2 of all the electrical elements generate DELAY, the DELAY of the other electrical elements is negligible.

In an initial state, that is, in a first working state, the original clock signal Fclk is "1", the Reset terminal Reset-1 is "1", the second signal input terminal of the first nor gate 1 is "1", the first signal input terminal of the first nor gate 1 is "1", and the signal output terminal of the first nor gate 1 is "0"; the first signal input terminal and the second signal input terminal of the second nor gate 2 are both "0", the signal output terminal of the second nor gate 2 is "1", and at this time, the detection clock signal Q2 is "1", and according to the characteristic of the nor gate increment table, as long as the signal of one input terminal is 1, the output terminal signal is "0", so the signal output terminal of the third nor gate 3 is "0", and at this time, the detection clock signal Q4 is "0".

In the second operating state, the Reset terminal Reset-1 is released to low level, and the signal of the Reset terminal Reset-1 is "0", but does not affect the signals at the output terminals of the first nor gate 1 and the third nor gate 3. Because the first signal input terminal of the first nor gate 1 and the first signal input terminal of the third nor gate 3 are still "1" at this time, and according to the truth table characteristic of the nor gate, as long as the signal of one input terminal is 1, the signal of the output terminal is "0", and the output terminals of the first nor gate 1 and the third nor gate 3 are completely the same as those in the first operating state, the states of the detection clock signal Q2 and the detection clock signal Q4 are not changed, and the original clock signal Fclk is still "1" at this time.

In a third operating state, the original clock signal Fclk transits from "1" to "0", when the first signal input terminal and the second signal input terminal of the first nor gate 1 are respectively "0", when the signal output terminal of the first nor gate 1 is "1", that is, the second signal input terminal of the second nor gate 2 is "1", according to the truth table characteristic of the nor gate, as long as the signal at one input terminal is 1, the output terminal signal is "0", when the detection clock signal Q2 transits from "1" to "0" after the DELAY of the second DELAY2, and in the third operating state, the first signal input terminal of the third nor gate 3 is "0", the second signal input terminal generates the detection clock signal clk _ Q2 only after the second nor gate 2 has undergone the DELAY of the second DELAY ay2, and transmits the clk _ Q2 to the second signal input terminal of the third nor gate 3, the third nor gate 3 will have a new signal input, so in the third operating state, the second signal input terminal of the third nor gate 3 always keeps "1", and the signal output terminal of the third nor gate 3 is "0", so that the detection clock signal Q4 still keeps "0".

In the fourth operating state, the detection clock signal clk _ Q2 transmits a new state "0" to the second signal input terminal of the third nor gate 3, when the first signal input terminal of the third nor gate 3 is "0", the result of the signal output terminal of the third nor gate 3 jumps from "1" to "0", then after the DELAY of the first DELAY device DELAY1, the detection clock signal clk _ Q4 is output, and after the first inverter 4 and the second inverter 5, the detection clock signal Q4 is obtained, so that in the fourth operating state, the detection clock signal Q4 is "0", and jumps to "1" immediately after the fourth operating state is finished. At this time, the detection clock signal Q2 remains unchanged.

In the fifth operating state, the state is an intermediate stable state, and the original clock signal Fclk, the detection clock signal Q2 and the detection clock signal Q4 are all kept unchanged. Waiting for the original clock signal Fclk to jump from "0" to "1" in the next operating state.

In the sixth operating state, the original clock signal Fclk jumps from "0" to "1", at this time, the first signal input terminal of the third nor gate 3 is "1", the signal output terminal of the third nor gate 3 is "0" according to the characteristics of the nor gate, the detection clock signal clk _ Q4 is output after the DELAY of the first DELAY1, and the detection clock signal clk _ Q4 outputs the detection clock signal Q4 after passing through two inverters, so that the detection clock signal Q4 keeps "1" in the sixth operating state and jumps to "0" at the end of the sixth state. Meanwhile, in the sixth operating state, the first signal input terminal of the second nor gate 2 is clocked to "1", and the first signal input terminal of the second nor gate 2 does not transition to "0" until the sixth operating state is completed, so that in the sixth operating state, the detection clock signal Q2 is held to "0".

In the seventh operating state, the first signal input terminal of the second nor gate 2 receives the signal "0" of the detection clock signal clk _ Q4, at this time, the second signal input terminal of the second nor gate 2 is "0", so the signal output terminal of the second nor gate 2 is "1", after the DELAY of the second DELAY device DELAY2, the detection clock signal clk _ Q2 is output, and the detection clock signal clk _ Q2 passes through two inverters to obtain the detection clock signal Q2. Therefore, in the seventh operating state, the detection clock signal Q2 remains "0", and after the seventh operating state is completed, the transition to "1" is made. At this time, the state of the detection clock signal Q4 remains "0".

In the eighth operating state, the state is an intermediate stable state, and the original clock signal Fclk, the detection clock signal Q2 and the detection clock signal Q4 all remain unchanged at the end of the seventh operating state. That is, the original clock signal Fclk is "1", the detection clock signal Q2 is "1", and the detection clock signal Q4 is "0". Waiting for the original clock signal Fclk to transition from "1" to "0" in the next operating state. The eighth operating mode has been got back to the condition of second operating mode this moment, so works as the utility model discloses a do not have the opposite phase detection clock generating circuit of high level intersection and normally work the back, can be from constantly repeating the process from second operating mode to eighth operating mode always.

In the fourth operating state and the seventh operating state, the detection clock signal Q2 and the detection clock signal Q4 are also at low level, but all D latches in the novel signal falling edge detection circuit claimed in application 2018105290672 and patent application 201820810334 are triggered at high level, so that when the detection clock signal Q2 and the detection clock signal Q4 are at low level at the same time, the novel signal falling edge detection circuit is not affected.

Fig. 2 is a timing diagram of a single cycle of the present invention inverted detection clock generation circuit without high level intersection. From fig. 2, it can be clearly seen that the utility model relates to a there is not the inverted phase detection clock generating circuit of high level intersection can not take place the situation that detection clock signal Q2 and detection clock signal Q4 are the high level simultaneously.

Drawings

Fig. 1 is a schematic structural diagram of the anti-phase detection clock generating circuit without high level intersection according to the present invention.

Fig. 2 is a timing diagram of a single cycle of the present invention inverted detection clock generation circuit without high level intersection.

Original clock signal	Fclk
		Reset terminal	Reset-1
First NOR gate	1
		Second NOR gate	2
Third NOR gate	3
		First time delay unit	DELAY1
Second delayer	DELAY2
		Detecting clock signals	clk_Q2
Detecting clock signals	clk_Q4
		A first inverter	4
Second inverter	5
		Third inverter	6
Fourth inverter	7
		Detecting clock signals	Q2
Detecting clock signals	Q4

Detailed Description

Specific embodiment example 1:

as shown in fig. 1, it is a schematic structural diagram of the inverted detection clock generating circuit without high level intersection according to the present invention; it includes: the clock signal Fclk, the Reset terminal Reset-1, the first nor gate 1, the second nor gate 2, the third nor gate 3, the first DELAY1, the second DELAY2, the first inverter 4, the second inverter 5, the third inverter 6, and the fourth inverter 7, wherein: an original clock signal Fclk is respectively connected with a first signal input end of a third nor gate 3 and a second signal input end of a first nor gate 1, and a Reset end Reset-1 is respectively connected with the third nor gate 3 and the first signal input end of the first nor gate 1; a signal output terminal of the first nor gate 1 is connected to a second signal input terminal of the second nor gate 2, a signal output terminal of the second nor gate 2 outputs a detection clock signal clk _ Q2 after passing through a second DELAY2, the detection clock signal clk _ Q2 is driven by a third inverter 6 and a fourth inverter 7, and a detection clock signal Q2 is output; the detection clock signal clk _ Q2 is simultaneously connected to the second signal input terminal of the third nor gate 3, the signal output terminal of the third nor gate 3 outputs the detection clock signal clk _ Q4 after passing through the first DELAY unit DELAY1, the detection clock signal clk _ Q4 is driven by the first inverter 4 and the second inverter 5, and the detection clock signal Q4 is output; the detection clock signal Q4 is connected to a first signal input terminal of the second nor gate 2; the initial state of the inverted detection clock generating circuit without high level intersection is set as that the original clock signal Fclk is set to be high level, the Reset terminal Reset-1 is set to be high level, the detection clock signal clk _ Q2 is set to be high level, and the detection clock signal clk _ Q4 is set to be low level.

The DELAY of the first DELAY device DELAY1 and the DELAY of the second DELAY device DELAY2 are both 2 ns; the size of the second inverter 5 is 2 times the size of the first inverter 4; the size of the fourth inverter 7 is 4 times the size of the first inverter 4.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. An inversion detection clock generation circuit without high level intersection, comprising: original clock signal Fclk, enable terminal Reset-1, first NOR gate (1), second NOR gate (2 ), the third NOR gate (3), the first delay device DELAY1, the second delay device DELAY2, the first inverter (4), the second inverter (5), the third inverter (6 ), the fourth inverter (7), characterized in that: the original clock signal Fclk is respectively connected with the first signal input end of the third NOR gate (3) and the second of the first NOR gate (1) The signal input terminals are connected, and the enabling terminal Reset-1 is respectively connected with the third NOR gate (3) and the first signal input terminal of the first NOR gate (1); the signal output of the first NOR gate (1) The terminal is connected to the second signal input terminal of the second NOR gate (2), and the signal output terminal of the second NOR gate (2) outputs the detection clock signal clk_Q2 after passing through the second delay device DELAY2, and the detection clock signal clk_Q2 passes through The third inverter (6) and the fourth inverter (7) increase the drive, and output the detection clock signal Q2; the detection clock signal clk_Q2 is simultaneously connected to the second signal input end of the third NOR gate (3), The signal output end of the third NOR gate (3) outputs the detection clock signal clk_Q4 after passing through the first delay device DELAY1, and the detection clock signal clk_Q4 is driven by the first inverter (4) and the second inverter (5). , and output the detection clock signal Q4; the detection clock signal Q4 is connected to the first signal input end of the second NOR gate (2); the initial state setting of the inversion detection clock generation circuit that does not have a high level intersection The original clock signal Fclk is set to a high level, the enable terminal Reset-1 is set to a high level, the detection clock signal clk_Q2 is set to a high level, and the detection clock signal clk_Q4 is set to a low level.

2 . The inversion detection clock generating circuit without high level intersection according to claim 1 , wherein the delays of the first delay device DELAY1 and the second delay device DELAY2 are the same or different. 3 .

3 . The inversion detection clock generating circuit without high level intersection according to claim 1 , wherein the delays of the first delay device DELAY1 and the second delay device DELAY2 are 1ns-3ns. 4 .

4. The inversion detection clock generation circuit without high level intersection as claimed in claim 1, characterized in that: the first NOR gate (1), the second NOR gate (2), the third NOR gate (3), the first inverter (4), the second inverter (5), the third inverter (6) and the fourth inverter (7) all have delays, and the delays are respectively 0.2ns -0.3ns.

5. The inversion detection clock generation circuit without high level intersection as claimed in claim 1, characterized in that: the size of the second inverter (5) is 1.2 times the size of the first inverter (4) times - 6 times.

6. The inversion detection clock generation circuit without high-level intersection as claimed in claim 1, characterized in that: the size of the second inverter (5) is 2 times the size of the first inverter (4). times - 4 times.

7. The inversion detection clock generation circuit without high level intersection as claimed in claim 1, characterized in that: the size of the fourth inverter (7) is 1.2 of the size of the third inverter (6) times - 6 times.

8. The inversion detection clock generating circuit without high-level intersection as claimed in claim 1, characterized in that: the size of the fourth inverter (7) is 2 times the size of the first inverter (4). times - 4 times.