CN210038709U - Power monitoring management buckle - Google Patents

Abstract

The utility model discloses a power monitoring and management sub-board, the management sub-board comprises a connector and a power management chip, and an SMBUS interface of the power management chip is connected to an SMBUS interface of a BMC of a board card to be managed through the connector; The voltage of the power module of the board to be managed is connected to the VP pin of the power supply input channel of the power management chip through the connector, and the EN pin of the power module to transmit an enable signal is connected to the connector through the connector. PDIO pin of the power management chip. The power monitoring and management daughter board is independent of the board to be managed, and is interconnected with the board to be managed through connectors, thereby reducing the number of chips used, saving project costs and board layout space.

Description

A power monitoring and management board

technical field

The utility model relates to the field of power monitoring of server boards, in particular to a power monitoring and management sub-board.

Background technique

With the advent of the era of big data, all kinds of network data are increasing explosively. As an important part of data transmission and processing, the security and reliability of the server are particularly important. In order to ensure the safe and reliable operation of the server, a monitoring and management system has been added to the design. As the source of power for the server, the monitoring and management of the power supply is very important. There are generally multiple power supplies in the server board, and these power supplies have certain requirements for the power-on sequence; at the same time, it is also necessary to monitor the voltage of these power supplies in real time, and record the abnormal power failure in time for subsequent problem analysis. And maintenance.

In the prior art, power monitoring and management are mainly composed of CPLD (Complex Programmable Logic Device, complex programmable logic device), ADC (Analog-to-Digital Converter, analog-to-digital converter), PSOC (Programmable embedded System-on) in the server board. -Chip, programmable embedded chip system) and BMC (Baseboard Management Controller, baseboard management controller), however, for the server high-density board, the board space is limited, the above solutions use a large number of chips, occupying more layout space problem.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the present invention provides a power monitoring and management sub-board, which adopts a sub-board design independent of the board to be managed, which reduces the number of board chips and saves the layout space of the board.

To achieve the above object, the utility model adopts the following technical solutions:

A power monitoring and management sub-board, the management sub-board includes a connector and a power management chip, and an SMBUS (System Management Bus) interface of the power management chip is connected to a BMC of a to-be-managed board through the connector SMBUS interface; the voltage of the power module of the board to be managed is connected to the power input channel VP pin of the power management chip through the connector, and the EN pin of the power module transmission enable signal is connected through the connection The device is connected to the PDIO pin of the power management chip.

Further, the power management chip is ADM1266.

Further, the connector includes a connector A and a connector B, the connector A is connected to the power management chip and the power module of the board to be managed; the connector B is connected to the power management chip and the BMC of the board to be managed.

Further, the SMBUS interface of the BMC also connects the FRU and the temperature sensor chip in the management board through the connector B; the connector B also includes the GPIO interface and the power interface of the power management chip, and the power interface is connected to the power management chip. The chip and the power conversion chip supply power, and the power conversion chip converts and provides the required operating voltage to the FRU and the temperature sensor chip.

Further, the connector A and the connector B are defined by OCP2.0.

Further, the power conversion chip is TPS53515.

Further, the FRU is an AT24C02C chip.

Further, the temperature sensor chip is TPM112.

The beneficial effects of the present utility model are:

The utility model designs a power monitoring and management sub-board, which is independent of the board to be managed, and is interconnected with the board to be managed through a connector, thereby reducing the number of chips used, project cost and board layout space. The power monitoring and management sub-board uses ADM1266 as the power monitoring chip to control the power-on sequence of each power supply. It also integrates the SMBUS bus interface, which enables the BMC to monitor and manage the SMBUS devices in the sub-board, which is convenient for reading the internal information of the board for maintenance. Manage, obtain and adjust the current system temperature to improve the reliability of system operation.

Description of drawings

Figure 1 is a schematic structural diagram of the present invention.

Detailed ways

In order to clearly illustrate the technical characteristics of the present solution, the present utility model will be described in detail below through specific embodiments and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present disclosure may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted from the present invention to avoid unnecessarily limiting the present invention.

The utility model provides a power monitoring and management sub-board, the management sub-board comprises a connector and a power management chip, and an SMBUS interface of the power management chip is connected to the SMBUS interface of a BMC of a board card to be managed through the connector; The voltage of the power module of the board to be managed is connected to the power input channel VP pin of the power management chip through the connector, and the EN pin of the power module transmission enable signal is connected to the connector through the connector. PDIO pin of the power management chip.

FIG. 1 is a schematic structural diagram of an embodiment of the present invention. The power management chip of the power monitoring and management board adopts ADM1266, and the connectors are divided into connector A and connector B.

Connector A is connected to the power module of the board to be managed and the power management chip ADM1266, the voltage signal of the power module is connected to the power input channels VP_1~VP_N of the power management chip ADM1266, and the power input channel is internally connected to the ADC module of the chip. The power module is connected to the pin through connector A, and the ADC module converts the input power voltage into digital quantity, and compares it with the preset threshold to determine whether the power output meets the set requirements; the power module transmits the enable signal. The EN pin is connected to the PDIO_1~PDIO_N pins of the power management chip. The logic module inside the power management chip ADM1266 controls the power-on sequence of each power supply according to the power status read back by the ADC and combined with the external signals (such as in-position, reset, etc.) input by GPIO. Such as undervoltage, overvoltage, power failure, etc.) to record and store faults in time.

Connector B is used to transmit the SMBUS bus, 12V power supply and the GPIO interface of the ADM1266.

The BMC of the board to be managed communicates with the chip of the management sub-board through the standard SMBUS interface.

ADM1266, FRU and temperature sensor chip for configuration management. The SMBUS bus is sent from the BMC, and the digital quantity of the power supply voltage converted by the ADC module inside the ADM1266 can be transmitted to the BMC web interface for real-time display; when the power supply fails, the BMC can also record the faults in the Black BOX of the ADM1266 through the SMBUS bus. Read it back for fault analysis and positioning; BMC can also update the firmware of the ADM1266 through SMBUS. The FRU uses the AT24C02C chip to store the asset information of the daughter board, mainly including the product name (Product Number), the serial number of the machine (Serial Number), etc. The BMC reads the internal information of the daughter board FRU through SMBUS, which is convenient for subsequent adjustment. Board maintenance and management. The temperature sensor chip TPM112 is used to monitor the internal temperature of the system. BMC obtains the current system temperature from the temperature sensor chip through SMBUS, and then selects an appropriate cooling strategy to adjust the fan speed, so that the system can work within a stable temperature range and improve system performance. reliability.

The 12V power supply supplies power to the ADM1266 chip, and at the same time, it is converted to 3V3 through the TPS53515 power conversion chip, and supplies power to the FRU and temperature sensor chip in the daughter board.

The GPIO interface of the ADM1266 transmits external signals (such as in-position, reset, etc.) and is used in conjunction with the logic module to control the power-on sequence of each power supply.

Connector A and connector B use the connectors defined by OCP2.0 respectively, which can provide 200 IO channels.

Although the specific embodiments of the present invention have been described above with reference to the accompanying drawings, they are not intended to limit the protection scope of the present invention. For those skilled in the art, on the basis of the above description, other modifications or variations in different forms can also be made. There is no need and cannot be exhaustive of all implementations here. On the basis of the technical solutions of the present invention, various modifications or deformations that can be made by those skilled in the art without creative work are still within the protection scope of the present invention.

Claims (8)

1. A power supply monitoring and management buckle plate is characterized in that the management buckle plate comprises a connector and a power supply management chip, wherein an SMBUS interface of the power supply management chip is connected with an SMBUS interface of a BMC of a board card to be managed through the connector; the voltage of the power module of the board card to be managed is connected with a VP pin of a power input channel of the power management chip through the connector, and an EN pin of the power module for transmitting an enabling signal is connected with a PDIO pin of the power management chip through the connector.

2. The power monitoring management pinch plate of claim 1, wherein the power management chip is ADM 1266.

3. The power monitoring management buckle plate of claim 2, wherein the connector comprises a connector A and a connector B, and the connector A is connected with a power management chip and a power module of a board card to be managed; the connector B is connected with the power management chip and the BMC of the board card to be managed.

4. The power monitoring management pinch plate of claim 3, wherein the SMBUS interface of the BMC is further connected with an FRU and a temperature sensor chip in the management pinch plate through a connector B; the connector B further comprises a GPIO interface and a power interface of the power management chip, the power interface supplies power to the power management chip and the power conversion chip, and the power conversion chip converts and provides required working voltage for the FRU and the temperature sensor chip.

5. The power monitoring management buckle of claim 4, wherein said connector A and connector B are defined as OCP 2.0.

6. The power monitoring management pinch plate of claim 4, wherein the power conversion chip is TPS 53515.

7. The power monitoring management buckle of claim 4, wherein said FRU is an AT24C02C chip.

8. The power monitoring management pinch plate of claim 4, wherein the temperature sensor chip is the TPM 112.

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